A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a substrate; a circuit layer disposed on the substrate; an interlayer insulating layer disposed on the circuit layer; a first electrode disposed on the interlayer insulating layer; a second electrode disposed on the interlayer insulating layer, and spaced apart from the first electrode; a first insulation disposed on the interlayer insulating layer; a second insulation disposed on the interlayer insulating layer, and spaced apart from the first insulation; a first memory cell and a second memory cell disposed on the first electrode, and spaced apart from each other; a third memory cell and a fourth memory cell disposed on the second electrode, and spaced apart from each other; a third electrode disposed on the first memory cell and the third memory cell; a fourth electrode disposed on the second memory cell and the fourth memory cell, and spaced apart from the third electrode; and an upper insulation disposed between the third electrode and the fourth electrode, wherein each of the first, second, third and fourth memory cells includes a selection device layer, an intermediate electrode disposed on the selection device layer and a variable resistance layer disposed on the intermediate electrode, wherein the first electrode is disposed between the first insulation and the second insulation, wherein a width of an upper portion of the first memory cell is less than a width of a lower portion of the first memory cell, and wherein an upper surface of the first insulation is uneven such that a side portion of the upper surface of the first insulation is disposed higher than a center portion of the upper surface of the first insulation.
2. The semiconductor device of claim 1 , wherein an upper surface of the second insulation includes a recess.
3. The semiconductor device of claim 1 , wherein the first insulation is disposed between the first electrode and the second electrode.
4. The semiconductor device of claim 1 , further comprising a third insulation disposed on the interlayer insulating layer, and disposed between the first memory cell and the second memory cell and between the third memory cell and the fourth memory cell.
5. The semiconductor device of claim 1 , wherein each of the first, second, third and fourth memory cells further includes a spacer disposed on a sidewall of the variable resistance layer, and wherein a sidewall of the selection device layer, a sidewall of the intermediate electrode and a sidewall of the spacer have the substantially same slope.
6. The semiconductor device of claim 1 , wherein a width of the variable resistance layer is less than a width of the selection device layer.
7. The semiconductor device of claim 1 , wherein a width of a top portion of the first electrode is greater than a width of a middle portion of the first electrode.
8. The semiconductor device of claim 1 , wherein a width of a widest portion of the third electrode is less than a width of a widest portion of the first electrode.
9. The semiconductor device of claim 1 , wherein a height of the third electrode is greater than a height of the first electrode.
10. A semiconductor device comprising: a substrate; an interlayer insulating layer disposed on the substrate; a first electrode disposed on the interlayer insulating layer; a second electrode disposed on the interlayer insulating layer, and spaced apart from the first electrode; a first insulation disposed on the interlayer insulating layer; a second insulation disposed on the interlayer insulating layer, and spaced apart from the first insulation; a first memory cell and a second memory cell disposed on the first electrode, and spaced apart from each other; a third memory cell and a fourth memory cell disposed on the second electrode, and spaced apart from each other; a third electrode disposed on the first memory cell and the third memory cell; a fourth electrode disposed on the second memory cell and the fourth memory cell, and spaced apart from the third electrode; a third insulation disposed between the third electrode and the fourth electrode; a fifth memory cell and a sixth memory cell disposed on the third electrode, and spaced apart from each other; a seventh memory cell and an eighth memory cell disposed on the fourth electrode, and spaced apart from each other; a fifth electrode disposed on the fifth memory cell and the seventh memory cell; a sixth electrode disposed on the sixth memory cell and the eighth memory cell, and spaced apart from the fifth electrode; and a fourth insulation disposed between the fifth electrode and the sixth electrode, wherein each of the first, second, third, fourth, fifth, sixth, seventh and eighth memory cells includes a selection device layer, an intermediate electrode disposed on the selection device layer and a variable resistance layer disposed on the intermediate electrode, wherein the first electrode is disposed between the first insulation and the second insulation, wherein a width of an upper portion of the first memory cell is less than a width of a lower portion of the first memory cell, and wherein a side portion of an upper surface of the first insulation is disposed higher than a center portion of the upper surface of the first insulation.
11. The semiconductor device of claim 10 , wherein the upper surface of the first insulation is uneven.
12. The semiconductor device of claim 10 , wherein an upper surface of the third insulation is uneven such that a side portion of the upper surface of the third insulation is disposed higher than a center portion of the upper surface of the third insulation.
13. The semiconductor device of claim 10 , further comprising a circuit layer disposed on the substrate and below the interlayer insulating layer.
14. The semiconductor device of claim 10 , wherein a width of an upper portion of the fifth memory cell is less than a width of a lower portion of the fifth memory cell.
15. The semiconductor device of claim 10 , wherein a width of an upper portion of the third electrode is different from a width of a lower portion of the third electrode.
16. A semiconductor device comprising: a substrate; a first interlayer insulating layer disposed on the substrate; a first electrode disposed on the first interlayer insulating layer; a second electrode disposed on the first interlayer insulating layer, and spaced apart from the first electrode; a first insulation disposed on the first interlayer insulating layer; a second insulation disposed on the first interlayer insulating layer, and spaced apart from the first insulation; a first memory cell and a second memory cell disposed on the first electrode, and spaced apart from each other; a third memory cell and a fourth memory cell disposed on the second electrode, and spaced apart from each other; a third electrode disposed on the first memory cell and the third memory cell; a fourth electrode disposed on the second memory cell and the fourth memory cell, and spaced apart from the third electrode; a third insulation disposed between the third electrode and the fourth electrode; a fifth memory cell and a sixth memory cell disposed on the third electrode, and spaced apart from each other; a seventh memory cell and an eighth memory cell disposed on the fourth electrode, and spaced apart from each other; a fifth electrode disposed on the fifth memory cell and the seventh memory cell; a sixth electrode disposed on the sixth memory cell and the eighth memory cell, and spaced apart from the fifth electrode; a fourth insulation disposed between the fifth electrode and the sixth electrode; a ninth memory cell and a tenth memory cell disposed on the fifth electrode, and spaced apart from each other; an eleventh memory cell and a twelfth memory cell disposed on the sixth electrode, and spaced apart from each other; a seventh electrode disposed on the ninth memory cell and the eleventh memory cell; an eighth electrode disposed on the tenth memory cell and the twelfth memory cell, and spaced apart from the seventh electrode; a fifth insulation disposed between the seventh electrode and the eighth electrode; a thirteenth memory cell and a fourteenth memory cell disposed on the seventh electrode, and spaced apart from each other; a fifteenth memory cell and a sixteenth memory cell disposed on the eighth electrode, and spaced apart from each other; a ninth electrode disposed on the thirteenth memory cell and the fifteenth memory cell; a tenth electrode disposed on the fourteenth memory cell and the sixteenth memory cell, and spaced apart from the ninth electrode; and a sixth insulation disposed between the ninth electrode and the tenth electrode, wherein each of the first through sixteenth memory cells includes a selection device layer, an intermediate electrode disposed on the selection device layer and a variable resistance layer disposed on the intermediate electrode, wherein the first electrode is disposed between the first insulation and the second insulation, wherein a width of an upper portion of the first memory cell is less than a width of a lower portion of the first memory cell, and wherein an upper surface of the first insulation is uneven.
17. The semiconductor device of claim 16 , wherein a side portion of the upper surface of the first insulation is disposed higher than a center portion of the upper surface of the first insulation.
18. The semiconductor device of claim 16 , wherein an upper surface of the third insulation includes a recess.
19. The semiconductor device of claim 16 , further comprising a second interlayer insulating layer disposed on the fifth electrode, the sixth electrode and the fourth insulation.
20. The semiconductor device of claim 16 , wherein a height of the third electrode is greater than a height of the first electrode.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 24, 2020
December 14, 2021
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