A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A device comprising: a bulk semiconductor substrate; a semiconductor region over and connecting to the bulk semiconductor substrate; isolation regions over and contacting the bulk semiconductor substrate, wherein the semiconductor region comprises a first sidewall and a second sidewall opposite to each other, and wherein the isolation regions comprise a first portion and a second portion in physical contact with the first sidewall and the second sidewall, respectively; a first semiconductor strip overlapping the semiconductor region, wherein the isolation regions comprise top surfaces lower than the first semiconductor strip; a first gate dielectric encircling the first semiconductor strip; and a gate electrode comprising portions on opposite sides of the first semiconductor strip and the first gate dielectric.
2. The device of claim 1 further comprising: a silicon germanium oxide region overlapping the semiconductor region, wherein the silicon germanium oxide region is between the first semiconductor strip and the semiconductor region.
3. The device of claim 2 , wherein the silicon germanium oxide region physically contacts the first gate dielectric.
4. The device of claim 2 , wherein the silicon germanium oxide region is separated from the first gate dielectric by a portion of the gate electrode.
5. The device of claim 1 further comprising: a second semiconductor strip overlapping the first semiconductor strip; and a second gate dielectric encircling the second semiconductor strip, wherein the first gate dielectric contacts the second gate dielectric.
6. The device of claim 5 , wherein each of the first gate dielectric and the second gate dielectric comprises: a silicon oxide layer encircling the respective one of the first and the second semiconductor strips, and the silicon oxide layer encircling the first semiconductor strip is in contact with the silicon oxide layer encircling the second semiconductor strip; and a high-k dielectric layer comprising portions on opposite sides of, and contacting, the silicon oxide layer.
7. The device of claim 1 , wherein the first semiconductor strip has a round cross-sectional shape.
8. A device comprising: a first silicon strip; a first gate dielectric encircling the first silicon strip; a silicon germanium oxide layer overlapped by the first silicon strip and the first gate dielectric; a semiconductor region overlapped by the silicon germanium oxide layer; a gate electrode on the first gate dielectric; and source and drain regions connected to opposite ends of the first silicon strip.
9. The device of claim 8 , wherein the first silicon strip has a lengthwise direction parallel to a top surface of the silicon germanium oxide layer.
10. The device of claim 8 further comprising shallow trench isolation regions on opposite sides of, and contacting sidewalls of, the silicon germanium oxide layer and the semiconductor region.
11. The device of claim 10 , wherein the silicon germanium oxide layer has a first portion lower than top surfaces of the shallow trench isolation regions, and a second portion higher than the top surfaces of the shallow trench isolation regions.
12. The device of claim 8 further comprising: a second silicon strip overlapping the first silicon strip; and a second gate dielectric encircling the second silicon strip, wherein the first gate dielectric is joined to the second gate dielectric.
13. The device of claim 12 , wherein each of the first gate dielectric and the second gate dielectric comprises: a silicon oxide layer, wherein the silicon oxide layer of the first gate dielectric and the silicon oxide layer of the second gate dielectric are joined to each other; and a high-k dielectric layer, wherein the high-k dielectric layer of the first gate dielectric and the high-k dielectric layer of the second gate dielectric are joined to each other.
14. The device of claim 8 , wherein the silicon germanium oxide layer comprises: a lower portion; and an upper portion narrower than the lower portion.
15. The device of claim 8 , wherein the first silicon strip is intrinsic.
16. A device comprising: a plurality of semiconductor strips, with higher ones of the plurality of semiconductor strips overlapping lower ones of the plurality of semiconductor strips, wherein lengthwise directions of the plurality of semiconductor strips are parallel to each other; a plurality of gate dielectrics, each encircling one of the plurality of semiconductor strips, wherein the plurality of gate dielectrics are directly joined together; a gate electrode contacting the plurality of gate dielectrics; and a source/drain region connected to ends of the plurality of semiconductor strips.
17. The device of claim 16 further comprising a first isolation region and a second isolation region on opposite sides of, and lower than, the plurality of semiconductor strips.
18. The device of claim 17 , wherein the source/drain region extends into a region between the first isolation region and the second isolation region, and a bottom of the source/drain region is lower than top surfaces of the first isolation region and the second isolation region.
19. The device of claim 16 , wherein the plurality of gate dielectrics comprise a plurality of oxide layers, each encircling one of the plurality of semiconductor strips, and a plurality of high-k dielectric layers, each on opposite sides of one of the plurality of oxide layers, wherein the plurality of oxide layers are joined to form a continuous oxide region, and the plurality of high-k dielectric layers are joined to form a continuous high-k dielectric region.
20. The device of claim 16 further comprising a silicon germanium oxide layer overlapped by the plurality of semiconductor strips.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 15, 2019
December 28, 2021
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