Semiconductor package

1. A semiconductor package comprising: a frame having first and second surfaces opposing each other, having first and second through holes, and including a wiring structure connecting the first and second surfaces; a connection structure disposed on the first surface of the frame and having a redistribution layer connected to the wiring structure; a first semiconductor chip disposed on the connection structure in the first through hole and having a first surface having first pads connected to the redistribution layer and a second surface opposite to the first surface and having a second pad; a second semiconductor chip disposed on the connection structure in the second through hole and having an active surface having a connection pad connected to the redistribution layer and an inactive surface opposite to the active surface; an encapsulant encapsulating the first and second semiconductor chips; a wiring layer disposed on the encapsulant and the second surface of the frame and connected to the second pad of the first semiconductor chip and the wiring structure; and a heat dissipation layer disposed in a region of the encapsulant corresponding to the inactive surface of the second semiconductor chip, wherein the heat dissipation layer is positioned at the same level as that of the wiring layer.

2. The semiconductor package of claim 1 , wherein the wiring layer is connected to the second pad of the first semiconductor chip through a plurality of vias disposed in the encapsulant.

3. The semiconductor package of claim 1 , wherein the encapsulant has an opening exposing at least a portion of the second surface of the first semiconductor chip and the wiring layer is connected to the second pad by a conductive adhesive member in the opening of the encapsulant.

4. The semiconductor package of claim 1 , wherein the heat dissipation layer includes a same material as that of the wiring layer.

5. The semiconductor package of claim 1 , wherein the heat dissipation layer is connected to the inactive surface of the second semiconductor chip through a plurality of vias disposed in the encapsulant.

6. The semiconductor package of claim 1 , wherein the first semiconductor chip is a power device chip and the second semiconductor chip includes a control integrated circuit (IC) chip.

7. The semiconductor package of claim 6 , wherein the power device chip includes one of an insulated gate bipolar transistor (IGBT) including an emitter electrode, a gate electrode, and a collector electrode, or a field effect transistor (FET) chip including a source electrode, a gate electrode, and a drain electrode.

8. The semiconductor package of claim 7 , wherein one of the first pads is one of the emitter electrode and the collector electrode of the IGBT, another of the first pads is the gate electrode of the IGBT, and the second pad is another of the emitter electrode and the collector electrode of the IGBT, or one of the first pads is one of the source electrode and the drain electrode of the FET, another of the first pads is the gate electrode of the FET, and the second pad is another of the source electrode and the drain electrode of the FET.

9. The semiconductor package of claim 1 , wherein the frame further includes a third through hole and the semiconductor package further includes a third semiconductor chip or a passive component accommodated in the third through hole.

10. The semiconductor package of claim 1 , wherein the frame includes a plurality of insulating layers, the wiring structure includes a plurality of wiring patterns respectively disposed in the plurality of insulating layers and wiring vias connecting the plurality of wiring patterns, and the frame further includes an inductor including some of the plurality of wiring patterns and the at least one of the wiring vias.

11. The semiconductor package of claim 1 , wherein the frame includes first and second insulating layers sequentially disposed on the connection structure, and the wiring structure includes a first wiring pattern embedded in the first insulating layer and in contact with the connection structure, a second wiring pattern disposed on a side of the first insulating layer opposite to the side where the first wiring pattern is embedded, a third wiring pattern disposed on a side of the second insulating layer opposite to the side where the second wiring pattern is positioned, a first wiring via penetrating through the first insulating layer and connecting the first and second wiring patterns, and a second wiring via penetrating through the second insulating layer and connecting the second and third wiring patterns.

12. The semiconductor package of claim 1 , wherein the frame includes a first insulating layer and second and third insulating layers respectively disposed on opposing surfaces of the first insulating layer, and the wiring structure includes first and second wiring patterns respectively disposed on the opposing surfaces of the first insulating layer, a third wiring pattern disposed on the second insulating layer, a fourth wiring pattern disposed on the third insulating layer, a first wiring via penetrating through the first insulating layer and connecting the first and second wiring patterns, a second wiring via penetrating through the second insulating layer and connecting the second and third wiring patterns, and a third wiring via penetrating through the third insulating layer and connecting the third and fourth wiring patterns.

13. The semiconductor package of claim 1 , further comprising: a passivation layer covering the second surface of the frame and the wiring layer; and an underbump metal (UBM) layer electrically connecting the wiring structure through the passivation layer.

14. The semiconductor package of claim 1 , further comprising a passivation layer covering the connection structure and having a plurality of openings exposing portions of the redistribution layer.

15. A semiconductor package comprising: a frame having first and second surfaces opposing each other, having a first through hole and a second through hole, the frame including a plurality of insulating layers and a wiring structure connecting the first and second surfaces; a connection structure disposed on the first surface of the frame and having a redistribution layer connected to the wiring structure; a first semiconductor chip disposed in the first through holes, and having a first surface having first pads connected to the redistribution layer and a second surface opposite to the first surface of the first semiconductor chip and having a second pad; a second semiconductor chip disposed on the connection structure in the second through hole and having an active surface having a connection pad connected to the redistribution layer and an inactive surface opposite to the active surface; an encapsulant encapsulating the first semiconductor chip; and a wiring layer disposed on the encapsulant and the second surface of the frame and connected to the second pad of the first semiconductor chip and the wiring structure, wherein the wiring structure includes a plurality of wiring patterns respectively disposed in the plurality of insulating layers and wiring vias connecting the plurality of wiring patterns, and the frame further includes an inductor having some of the plurality of wiring patterns and at least one of the wiring vias.

16. The semiconductor package of claim 15 , wherein the first semiconductor chip is a power device chip including one of an insulated gate bipolar transistor (IGBT) including an emitter electrode, a gate electrode, and a collector electrode, or a field effect transistor (FET) chip including a source electrode, a gate electrode, and a drain electrode.

17. The semiconductor package of claim 16 , wherein one of the first pads of the power device chip is one of the emitter electrode and the collector electrode of the IGBT, another of the first pads of the power device chip is the gate electrode of the IGBT, and the second pad of the power device chip is another of the emitter electrode and the collector electrode of the IGBT, or one of the first pads of the power device chip is one of the source electrode and the drain electrode of the FET, another of the first pads of the power device chip is the gate electrode of the FET, and the second pad of the power device chip is another of the source electrode and the drain electrode of the FET.

18. The semiconductor package of claim 15 , wherein the frame further includes another through hole and the semiconductor package further includes a passive component accommodated in the another through hole.

19. A semiconductor package comprising: a frame having first and second surfaces opposing each other, having first and second through holes, and including a wiring structure connecting the first and second surfaces; a connection structure disposed on the first surface of the frame and having a redistribution layer connected to the wiring structure; a first semiconductor chip disposed on the connection structure in the first through hole and having a first surface having first pads connected to the redistribution layer and a second surface opposite to the first surface and having a second pad; a second semiconductor chip disposed on the connection structure in the second through hole and having an active surface having a connection pad connected to the redistribution layer and an inactive surface opposite to the active surface; an encapsulant encapsulating the first and second semiconductor chips; a wiring layer disposed on the encapsulant and the second surface of the frame and connected to the second pad of the first semiconductor chip and the wiring structure; and a heat dissipation layer disposed in a region of the encapsulant corresponding to the inactive surface of the second semiconductor chip, wherein the encapsulant has an opening exposing at least a portion of the inactive surface of the second semiconductor chip and the heat dissipation layer is connected to a conductive adhesive member in the opening of the encapsulant.