The present invention discloses a semiconductor structure of an image sensor, an associated chip and an electronic apparatus. The semiconductor structure includes a semiconductor substrate, and a plurality of pixel groups disposed on the bottom of the semiconductor substrate. Each of the pixel groups includes: a first pixel and a second pixel located in the same row and being adjacent to each other, and a third pixel and a fourth pixel located in another row and being adjacent to each other, wherein the first pixel and the third pixel are disposed diagonally. Each of the pixels includes four sub-pixels, and the four sub-pixels of each pixel share a floating diffusion region and the floating diffusion region is surrounded by photodetectors of the four sub-pixels. An output circuit is shared by the first pixel and the third pixel, and the shared output circuit of the first pixel and the third pixel is located between the first pixel and the third pixel, and extends to the left/right side of the first pixel and the right/left side of the third pixel. The present application is capable of enhancing image quality of the image sensor and improving performance of the output circuit.
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1. A semiconductor structure of an image sensor, being characterized in that: the semiconductor structure of the image sensor comprises: a semiconductor substrate, and a plurality of pixel groups disposed over the semiconductor substrate; each of the pixel groups comprises: a first pixel and a second pixel located in a same row and being adjacent to each other, and a third pixel and a fourth pixel located in another row and being adjacent to each other, wherein the first pixel and the third pixel are disposed diagonally and the first pixel and the third pixel are pixels of a same color; each of the first pixel, the second pixel, the third pixel and the fourth pixel comprises four sub-pixels arranged in two columns and two rows, the four sub-pixels of each pixel share a floating diffusion region, and the floating diffusion region is surrounded by photodetectors of the four sub-pixels, and the photodetectors are for converting light into electric charge; an output circuit is shared by the first pixel and the third pixel, the shared output circuit of the first pixel and the third pixel crosses a boundary between the first pixel and the third pixel and extends to a left/right side of the first pixel and a right/left side of the third pixel, the output circuit is for generating pixel output according to the electric charge, and the output circuit comprises a first source follower transistor; wherein, from a top view, a part of the first source follower transistor is located to one side of the boundary between the first pixel and the third pixel, and is at least adjacent to the photodetectors on the left/right side of the first pixel, and one other part of the first source follower transistor is located to one other side of the boundary between the first pixel and the third pixel, and is at least adjacent to the photodetectors on the right/left side of the third pixel; wherein the second pixel and the fourth pixel are disposed diagonally, and an output circuit is shared by the second pixel and the fourth pixel; and wherein the shared output circuit of the second pixel and the fourth pixel is located between the second pixel and the fourth pixel and extends to a left/right side of the second pixel and a right/left side of the fourth pixel.
The semiconductor structure of an image sensor is designed to improve pixel density and efficiency in color imaging. The structure includes a semiconductor substrate with multiple pixel groups, each containing four pixels arranged in a specific pattern. Within each group, two pixels in one row and two in another row are positioned diagonally, with adjacent pixels sharing an output circuit. Each pixel consists of four sub-pixels arranged in a 2x2 grid, all sharing a floating diffusion region surrounded by photodetectors that convert light into electric charge. The output circuit, which includes a source follower transistor, is shared between diagonally positioned pixels and crosses the boundary between them. The transistor is split, with parts located adjacent to the photodetectors of both pixels. This design allows for efficient charge processing while maintaining high pixel density. The shared output circuits reduce the overall footprint, enabling more compact image sensor designs. The arrangement ensures that pixels of the same color are diagonally aligned, optimizing color filtering and signal processing. This structure enhances imaging performance by improving pixel efficiency and reducing noise.
2. The semiconductor structure of the image sensor according to claim 1 , wherein the first pixel and the third pixel are both green pixels.
The semiconductor structure relates to an image sensor with a specific pixel arrangement designed to improve color accuracy and sensitivity. The structure includes multiple pixels arranged in a pattern where at least one pixel is a green pixel, and adjacent pixels are configured to enhance light capture and signal processing. The arrangement ensures that green pixels are strategically placed to optimize color balance and reduce noise in the captured image. The semiconductor structure may also include additional pixels of different colors, such as red and blue, to form a complete color filter array. The green pixels are positioned to maximize light absorption while minimizing interference from adjacent pixels, thereby improving overall image quality. The design is particularly useful in high-resolution imaging applications where accurate color reproduction and low-light performance are critical. The semiconductor structure may further incorporate additional layers or components to enhance pixel isolation and signal integrity, ensuring reliable operation under varying lighting conditions. This arrangement helps achieve better color fidelity and dynamic range in digital imaging systems.
3. The semiconductor structure of the image sensor according to claim 2 , wherein the output circuit further comprises a first row select transistor disposed at the third pixel, and the first row select transistor is adjacent to the photodetectors of the third pixel.
This invention relates to semiconductor structures for image sensors, specifically addressing the arrangement of output circuits and photodetectors within pixels to improve performance and integration. The structure includes a pixel array with multiple pixels, each containing photodetectors for capturing light and generating electrical signals. The output circuit of the pixel includes a first row select transistor positioned adjacent to the photodetectors of a third pixel, enhancing signal routing efficiency and reducing layout complexity. The row select transistor controls the readout of pixel signals, ensuring proper signal transmission to subsequent processing circuits. By placing the transistor near the photodetectors, the design minimizes signal path length, reducing noise and improving signal integrity. The structure may also include additional transistors, such as reset and source-follower transistors, to manage pixel operations like resetting and amplifying signals. The overall design optimizes pixel layout for high-density image sensors, improving performance in applications like digital cameras and medical imaging devices. The invention focuses on efficient signal routing and compact pixel design to enhance image sensor functionality.
4. The semiconductor structure of the image sensor according to claim 3 , wherein the output circuit further comprises a first reset transistor disposed at the first pixel, and the first reset transistor is adjacent to the photodetectors of the first pixel.
The invention relates to semiconductor structures for image sensors, specifically addressing the integration of reset transistors within pixel arrays to improve performance and efficiency. In conventional image sensors, reset transistors are often placed outside the pixel array or in a non-optimal location, leading to increased noise, slower reset times, and larger pixel sizes. The invention solves these issues by incorporating a first reset transistor directly within a first pixel of the image sensor, positioned adjacent to the photodetectors of that pixel. This placement reduces the distance between the reset transistor and the photodetectors, minimizing signal degradation and improving reset speed. The reset transistor is part of an output circuit that processes signals from the photodetectors, ensuring accurate and efficient image capture. By integrating the reset transistor within the pixel, the design also reduces the overall footprint of the image sensor, enabling higher pixel density and better spatial resolution. The invention is particularly useful in high-performance imaging applications where low noise, fast response, and compact design are critical.
5. The semiconductor structure of the image sensor according to claim 4 , wherein from a top view, the first row select transistor, the first source follower transistor and the first reset transistor are arranged in one column to form a transistor column.
The invention relates to semiconductor structures for image sensors, specifically addressing the arrangement of transistors within the pixel circuitry to improve layout efficiency and performance. In image sensors, pixel circuits typically include multiple transistors such as row select, source follower, and reset transistors, which are often arranged in a way that optimizes space and signal integrity. The invention describes a semiconductor structure where, when viewed from above, the first row select transistor, the first source follower transistor, and the first reset transistor are aligned in a single vertical column, forming a transistor column. This arrangement reduces the footprint of the pixel circuitry by minimizing lateral spacing between transistors, which is particularly beneficial in high-density image sensors where space is limited. The vertical alignment also improves signal routing efficiency, as the shared column allows for more direct electrical connections between the transistors, reducing parasitic capacitance and resistance. This configuration is part of a larger pixel circuit that may include additional transistors and components, but the key innovation lies in the specific columnar arrangement of these three critical transistors. The invention aims to enhance pixel density, reduce power consumption, and improve overall sensor performance by optimizing the physical layout of the transistor elements.
6. The semiconductor structure of the image sensor according to claim 3 , wherein the output circuit outputs the pixel output by using one source/drain of the first row select transistor as an output terminal.
The semiconductor structure relates to an image sensor, specifically addressing the efficient routing and output of pixel signals in a pixel array. The problem being solved involves optimizing the layout and connectivity of transistors within the pixel circuit to minimize area and improve signal integrity. Traditional image sensor designs often require complex routing schemes to connect pixel transistors to output lines, which can increase pixel size and reduce fill factor. This invention improves upon prior designs by simplifying the output path of the pixel signal. The semiconductor structure includes a pixel circuit with a first row select transistor, where one of its source/drain terminals serves as the output terminal for the pixel signal. This design eliminates the need for additional routing wires or transistors to direct the signal, reducing the overall pixel footprint. The first row select transistor is part of a larger pixel circuit that may include a photodiode, reset transistor, and amplification transistor. The photodiode converts incident light into an electrical signal, which is then amplified by the amplification transistor. The reset transistor initializes the pixel before each readout cycle. The row select transistor, controlled by a row select line, selectively connects the pixel output to a column output line when activated. By using one of the source/drain terminals of the row select transistor as the output terminal, the design streamlines the signal path, reducing parasitic capacitance and improving signal speed. This configuration is particularly useful in high-resolution image sensors where minimizing pixel size is critical.
7. The semiconductor structure of the image sensor according to claim 4 , wherein from a top view, the first source follower transistor is disposed between the first reset transistor and the first row select transistor.
The invention relates to semiconductor structures for image sensors, specifically addressing the spatial arrangement of transistors within the pixel circuitry to optimize performance and efficiency. Image sensors often require compact pixel designs to achieve high resolution while maintaining low power consumption and high-speed readout. A common challenge is efficiently arranging transistors such as reset, source follower, and row select transistors to minimize layout area and parasitic effects without compromising signal integrity. The semiconductor structure includes a first reset transistor, a first source follower transistor, and a first row select transistor. The key innovation is the arrangement of these transistors from a top view, where the source follower transistor is positioned between the reset transistor and the row select transistor. This layout optimizes the electrical connections and reduces parasitic capacitance, improving signal transfer efficiency and reducing noise. The source follower transistor, which amplifies the pixel signal, is centrally placed to minimize signal path length, while the reset and row select transistors are positioned to facilitate efficient pixel reset and readout operations. This configuration enhances pixel performance by reducing layout complexity and improving signal integrity, making it suitable for high-resolution and low-power image sensors.
8. The semiconductor structure of the image sensor according to claim 7 , wherein the first row select transistor and the first reset transistor are symmetrically disposed along the first source follower transistor.
The semiconductor structure relates to an image sensor design, specifically addressing the arrangement of transistors within a pixel cell to improve performance and efficiency. In image sensors, pixel cells typically include multiple transistors such as row select, reset, and source follower transistors, which are critical for signal readout and reset operations. A common challenge in such designs is optimizing the layout to minimize area, reduce parasitic effects, and ensure balanced electrical characteristics. This semiconductor structure features a pixel cell with a first row select transistor and a first reset transistor that are symmetrically disposed along a first source follower transistor. The symmetric arrangement helps balance electrical properties, such as resistance and capacitance, across the pixel cell, leading to improved signal integrity and reduced noise. The source follower transistor, positioned centrally, amplifies the pixel signal before readout, while the symmetrically placed row select and reset transistors ensure consistent and reliable operation. This layout minimizes layout-induced mismatches, which can degrade sensor performance. The design is particularly useful in high-resolution image sensors where precise signal handling is essential. By optimizing transistor placement, the structure enhances pixel uniformity and overall sensor efficiency.
9. The semiconductor structure of the image sensor according to claim 2 , wherein each of the four sub-pixels of each pixel comprises a transmission gate, and each transmission gate is located in a region where each of the photodetectors of the four sub-pixels is located.
The invention relates to an image sensor semiconductor structure designed to improve light detection efficiency. The problem addressed is the need for enhanced pixel performance in image sensors, particularly in terms of light sensitivity and signal transmission. The structure includes an array of pixels, each divided into four sub-pixels. Each sub-pixel contains a photodetector for capturing light and a transmission gate positioned directly within the region of the photodetector. The transmission gate facilitates the transfer of electrical signals generated by the photodetector, ensuring efficient signal readout. The placement of the transmission gate within the photodetector region optimizes space utilization and minimizes signal loss, leading to improved image quality. The structure is particularly useful in high-resolution imaging applications where precise light detection and rapid signal transmission are critical. The design ensures that each sub-pixel operates independently while contributing to the overall pixel's performance, enhancing the sensor's sensitivity and dynamic range. This configuration allows for more efficient light capture and processing, addressing limitations in conventional image sensor designs.
10. The semiconductor structure of the image sensor according to claim 9 , wherein from a top view, the transmission gates of the first pixel, the second pixel, the third pixel and the fourth pixel are evenly arranged in the pixel where they are located.
Image sensor technology. This invention addresses the arrangement of transmission gates within an image sensor. Specifically, it describes a semiconductor structure for an image sensor. From a top-down perspective, the transmission gates associated with a first pixel, a second pixel, a third pixel, and a fourth pixel are positioned in an evenly distributed manner within their respective pixels. This uniform spatial distribution of transmission gates aims to optimize performance or characteristics of the image sensor.
11. The semiconductor structure of the image sensor according to claim 1 , wherein the shared output circuit of the second pixel and the fourth pixel comprises a second source follower transistor, the second source follower transistor crosses a boundary between the second pixel and the fourth pixel, and at least extends to be adjacent to the light sensors on the left/right side of the second pixel and at least extends to be adjacent to the light sensors on the right/left side of the fourth pixel.
This invention relates to semiconductor structures for image sensors, specifically addressing the challenge of efficiently sharing output circuitry between adjacent pixels to reduce area and improve pixel density. The structure includes a shared output circuit for two pixels, such as a second pixel and a fourth pixel, which are part of a larger array. The shared output circuit comprises a second source follower transistor that spans the boundary between these two pixels. This transistor extends laterally to be adjacent to the light sensors on the left and right sides of the second pixel and the right and left sides of the fourth pixel, respectively. By positioning the source follower transistor in this manner, the design minimizes the footprint of the output circuitry while maintaining proximity to the light sensors of both pixels. This configuration allows for more compact pixel layouts, improving pixel density and overall image sensor performance without sacrificing signal integrity. The shared transistor reduces redundancy, conserving space and enabling higher-resolution sensors in the same or smaller chip area. The invention is particularly useful in advanced imaging applications where pixel density and efficiency are critical.
12. The semiconductor structure of the image sensor according to claim 11 , wherein the shared output circuit of the second pixel and the fourth pixel further comprises a second row select transistor and a second reset transistor, the second row select transistor is disposed at the fourth pixel, the second row select transistor is adjacent to the light sensors of the fourth pixel, the second reset transistor is disposed at the second pixel, and the second reset transistor is adjacent to the light sensors of the second pixel.
The invention relates to semiconductor structures for image sensors, specifically addressing the layout and arrangement of shared output circuits in pixel arrays to improve efficiency and performance. In conventional image sensors, each pixel typically includes its own output circuit, which can lead to increased area and complexity. This invention optimizes the design by sharing output circuits between adjacent pixels, reducing the overall footprint and improving pixel density. The semiconductor structure includes a pixel array with multiple pixels, each containing light sensors. The output circuits for certain pixels are shared, with specific transistors strategically placed to minimize layout area. For example, a shared output circuit between a second pixel and a fourth pixel includes a second row select transistor and a second reset transistor. The second row select transistor is positioned at the fourth pixel, adjacent to its light sensors, while the second reset transistor is located at the second pixel, adjacent to its light sensors. This arrangement ensures efficient signal routing and reduces the space required for the output circuitry, enhancing the overall performance of the image sensor. The invention improves pixel density and reduces manufacturing complexity by optimizing the placement of shared transistors within the pixel array.
13. The semiconductor structure of the image sensor according to claim 12 , wherein from a top view, the second row select transistor, the second source follower transistor and the second reset transistor are arranged in a column to form a transistor column.
The semiconductor structure relates to an image sensor design, specifically addressing the arrangement of transistors within the pixel circuitry to optimize space and performance. Traditional image sensor designs often suffer from inefficient transistor layouts, leading to larger pixel sizes and reduced sensor efficiency. This invention improves upon prior art by arranging key transistors in a columnar configuration to enhance spatial efficiency and electrical performance. The structure includes a second row select transistor, a second source follower transistor, and a second reset transistor, all aligned in a vertical column when viewed from above. This columnar arrangement minimizes the footprint of the transistor group, allowing for denser pixel layouts and improved sensor resolution. The transistors are interconnected to perform their respective functions in the pixel readout process, where the row select transistor controls pixel activation, the source follower transistor amplifies the pixel signal, and the reset transistor resets the pixel to a reference voltage. By grouping these transistors in a column, the design reduces wiring complexity and cross-talk between components, leading to more reliable signal processing. The overall structure enables higher pixel density and better performance in image sensors, particularly in applications requiring compact and high-resolution imaging.
14. The semiconductor structure of the image sensor according to claim 13 , wherein from a top view, the second source follower transistor is disposed between the second reset transistor and the second row select transistor.
The invention relates to semiconductor structures for image sensors, specifically addressing the spatial arrangement of transistors within the pixel circuitry to improve performance and efficiency. Image sensors often require compact pixel designs to achieve high resolution while maintaining low power consumption and high-speed readout. A common challenge is optimizing the layout of transistors, such as reset, source follower, and row select transistors, to minimize area and reduce parasitic effects. The invention describes a semiconductor structure for an image sensor where, when viewed from above, a second source follower transistor is positioned between a second reset transistor and a second row select transistor. This arrangement helps streamline the pixel layout, reducing signal interference and improving signal integrity. The source follower transistor amplifies the pixel signal before readout, while the reset transistor resets the pixel to a reference voltage, and the row select transistor controls the readout timing. By placing the source follower transistor between the reset and row select transistors, the design minimizes wiring complexity and parasitic capacitance, leading to faster readout speeds and better noise performance. The structure is particularly useful in backside-illuminated image sensors, where front-side real estate is constrained, and efficient transistor placement is critical for maintaining high pixel density. The invention enhances image sensor performance by optimizing transistor placement to reduce signal degradation and improve overall efficiency.
15. The semiconductor structure of the image sensor according to claim 14 , wherein the four sub-pixels of each pixel are of a same color.
The semiconductor structure relates to an image sensor with an array of pixels, each pixel comprising four sub-pixels arranged in a 2x2 grid. The sub-pixels within each pixel are of the same color, meaning all four sub-pixels detect the same wavelength of light. This design enhances color uniformity and reduces color aliasing by ensuring that each pixel captures a single color channel. The structure may include additional features such as microlenses, color filters, and light-sensitive elements like photodiodes or transistors to improve light collection efficiency. The arrangement allows for higher spatial resolution while maintaining consistent color representation, which is particularly useful in applications requiring precise color accuracy, such as medical imaging or high-end photography. The semiconductor structure may also incorporate anti-reflective coatings or other optical enhancements to further optimize light capture. By using identical sub-pixels within each pixel, the design simplifies signal processing and reduces noise, as all sub-pixels contribute to the same color channel. This approach differs from traditional Bayer filters, which use a mosaic of different color sub-pixels. The structure may be fabricated using standard semiconductor processes, including photolithography and etching, to form the sub-pixel arrays and associated circuitry.
16. The semiconductor structure of the image sensor according to claim 15 , wherein the second pixel is a blue pixel, the fourth pixel is red and the first pixel, the second pixel, the third pixel and the fourth pixel form a Bayer array.
The invention relates to a semiconductor structure for an image sensor, specifically addressing the arrangement of pixels to improve color capture and image quality. The structure includes multiple pixels, each configured to detect different color wavelengths. The second pixel is designed as a blue pixel, while the fourth pixel is configured as a red pixel. The first, second, third, and fourth pixels are arranged in a Bayer array pattern, which is a widely used color filter arrangement in digital imaging. The Bayer array alternates between green, red, and blue pixels in a specific grid to mimic the human eye's color sensitivity and enhance color accuracy. The semiconductor structure ensures efficient light detection and signal processing, optimizing the image sensor's performance for applications in digital cameras, smartphones, and other imaging devices. The arrangement minimizes color aliasing and improves spatial resolution, making it suitable for high-resolution imaging systems. The invention focuses on enhancing color fidelity and image clarity by leveraging the Bayer pattern's proven effectiveness in color interpolation and noise reduction.
17. A chip, being characterized in comprising: the semiconductor structure of the image sensor of claim 1 .
The invention relates to an image sensor chip designed to improve performance in semiconductor-based imaging devices. The chip incorporates a semiconductor structure that includes a substrate with a light-sensitive region for capturing photons and converting them into electrical signals. This region is optimized for high sensitivity and low noise, ensuring accurate image capture. The structure also features a passivation layer to protect the underlying components from environmental damage while maintaining optical transparency. Additionally, the chip includes a color filter array aligned with the light-sensitive region to enhance color accuracy. The semiconductor structure is further integrated with a microlens array to focus incoming light onto the light-sensitive region, improving light collection efficiency. The overall design aims to enhance image quality by reducing signal distortion and increasing dynamic range. The chip is particularly suited for applications requiring high-resolution imaging, such as digital cameras, medical imaging devices, and surveillance systems. The semiconductor structure's optimized layout and materials ensure reliable performance under varying lighting conditions, making it a versatile solution for modern imaging technologies.
18. An electronic apparatus, being characterized in comprising: the semiconductor structure of the image sensor of claim 1 .
This invention relates to an electronic apparatus incorporating an advanced semiconductor structure for an image sensor. The semiconductor structure includes a substrate with a pixel array, where each pixel contains a photodetector and a charge storage region. The photodetector converts incident light into electrical charges, which are then transferred to the charge storage region. The structure also features a transfer gate controlling the charge transfer between the photodetector and the charge storage region, and a readout circuit connected to the charge storage region to output the stored charges as an electrical signal. The apparatus is designed to improve image sensor performance by optimizing charge transfer efficiency and reducing noise, particularly in low-light conditions. The semiconductor structure may include additional elements such as isolation regions to prevent charge leakage and enhance pixel isolation. The electronic apparatus leverages this optimized semiconductor structure to achieve higher sensitivity, faster readout speeds, and improved image quality in applications like digital cameras, smartphones, and medical imaging devices. The invention addresses challenges in conventional image sensors, such as charge loss during transfer and high noise levels, by refining the semiconductor design and integration of the pixel array.
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January 22, 2020
January 25, 2022
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