A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A display having an active area with a notch, comprising: a substrate; organic light-emitting diode pixels on the substrate, wherein some of the organic light-emitting diode pixels are positioned on a first side of the notch and some of the organic light-emitting diode pixels are positioned on a second side of the notch; display driver circuitry; data lines coupled to the display driver circuitry and the organic light-emitting diode pixels; gate lines coupled to the display driver circuitry and the organic light-emitting diode pixels, wherein the organic light-emitting diode pixels are arranged in columns and rows, wherein the gate lines in a first area of the display that includes the notch are coupled to fewer of the organic light-emitting diode pixels than the gate lines in a second area of the display; and dummy pixels that are coupled to the gate lines in the first area.
Electronic display technology for improved visual uniformity around display cutouts. This invention pertains to a display device featuring organic light-emitting diode (OLED) pixels. The display includes an active area designed with a notch, which is a cutout or indentation. The OLED pixels are arranged on a substrate, with some pixels located on one side of the notch and others on the opposite side. The display is controlled by driver circuitry, including data and gate lines that connect to the OLED pixels. The pixels are organized in a grid of columns and rows. A key aspect is how the gate lines are managed in the region surrounding the notch. Specifically, gate lines in an area of the display that encompasses the notch are connected to a reduced number of OLED pixels compared to gate lines in other areas of the display. To compensate for this reduced pixel density or altered driving configuration near the notch, dummy pixels are incorporated. These dummy pixels are coupled to the gate lines within this first area. This arrangement aims to ensure consistent illumination and prevent visual artifacts such as uneven brightness or color shifts that might otherwise occur due to the presence of the notch and the modified pixel driving scheme in that specific region.
2. The display defined in claim 1 , wherein the dummy pixels do not emit light.
A display system includes a plurality of light-emitting pixels and a plurality of dummy pixels arranged in a matrix. The dummy pixels are positioned to reduce visual artifacts such as moiré patterns, false contours, or color breakup, which can occur due to interactions between the display and external structures like camera sensors or lenses. The dummy pixels are non-light-emitting and are interspersed among the light-emitting pixels to disrupt periodic patterns that could cause interference. The arrangement of dummy pixels is optimized to minimize visual distortions while maintaining display performance. The dummy pixels may be electrically inactive or may be configured to receive signals without emitting light, ensuring they do not contribute to the displayed image. This design improves display quality in applications where visual artifacts are problematic, such as in high-resolution screens or near camera systems. The dummy pixels are distributed in a pattern that balances artifact suppression and pixel density, ensuring smooth visual output. The system may also include control circuitry to manage the light-emitting pixels independently of the dummy pixels, allowing for precise image rendering while maintaining artifact reduction.
3. The display defined in claim 1 , wherein the dummy pixels do not contain emissive material for light-emitting diodes.
A display system includes a plurality of pixels arranged in an array, where each pixel comprises a plurality of subpixels. The display further includes a plurality of dummy pixels interspersed among the active pixels. These dummy pixels are non-emissive, meaning they do not contain emissive material typically used in light-emitting diodes (LEDs). The dummy pixels are positioned to reduce visual artifacts such as moiré patterns, improve display uniformity, or enhance image quality by disrupting unwanted interference patterns that may arise from the periodic arrangement of active pixels. The absence of emissive material in the dummy pixels ensures they do not contribute to the display's light output, allowing them to serve solely as structural or optical elements. The display may be used in various applications, including high-resolution screens, virtual reality displays, or other imaging systems where minimizing visual distortions is critical. The dummy pixels may be uniformly or non-uniformly distributed across the display to optimize performance based on specific design requirements.
4. The display defined in claim 1 , wherein the dummy pixels impose progressively decreasing amounts of loading on the gate lines of the first area at progressively increasing distances between the second area and the gate lines of the first area.
This invention relates to display technologies, specifically addressing the issue of signal distortion in gate lines of a display panel. The problem arises when dummy pixels are used to compensate for signal delays in active display areas, as these dummy pixels can introduce uneven loading on gate lines, leading to non-uniform signal propagation and display artifacts. The invention provides a display panel with a first area containing active display pixels and a second area containing dummy pixels. The dummy pixels are strategically arranged to impose progressively decreasing amounts of loading on the gate lines of the first area as the distance between the second area and the gate lines increases. This gradual reduction in loading ensures that signal propagation remains consistent across the display, preventing distortion and maintaining image quality. The dummy pixels are connected to the gate lines of the first area, and their loading effect is adjusted based on their proximity to the second area. By varying the number, size, or electrical properties of the dummy pixels, the loading on the gate lines is finely controlled. This approach compensates for signal delays without introducing additional distortion, resulting in a more uniform display performance. The solution is particularly useful in large-area displays where signal integrity is critical.
5. The display defined in claim 1 , wherein a first gate line in the first area of the display is coupled to a first number of dummy pixels, wherein a second gate line in the first area of the display is coupled to a second number of dummy pixels, and wherein the first number is greater than the second number.
A display system includes a first area with multiple gate lines and dummy pixels. The display is designed to address issues related to signal integrity and power efficiency in display panels, particularly in regions where dummy pixels are used to compensate for non-uniformities or to reduce power consumption. The first area of the display contains at least two gate lines, each connected to a different number of dummy pixels. Specifically, a first gate line in this area is coupled to a first number of dummy pixels, while a second gate line in the same area is coupled to a second number of dummy pixels, with the first number being greater than the second. This configuration allows for optimized control of dummy pixels, improving display performance by balancing signal distribution and reducing unnecessary power consumption. The system may also include additional areas with different gate line and dummy pixel arrangements to further enhance display functionality. The overall design ensures efficient use of resources while maintaining display quality.
6. The display defined in claim 5 , wherein the first gate line is a first distance from the second area, wherein the second gate line is a second distance from the second area, and wherein the second distance is greater than the first distance.
This invention relates to display technology, specifically addressing the arrangement of gate lines in a display panel to improve performance and reliability. The display includes a substrate with a first area and a second area, where the first area contains a plurality of pixels and the second area contains a plurality of gate lines. The gate lines are used to control the switching of transistors within the pixels. The first gate line is positioned at a first distance from the second area, while the second gate line is positioned at a second distance from the second area, with the second distance being greater than the first distance. This staggered arrangement of gate lines helps to reduce signal interference and improve the uniformity of the display. The display may also include a plurality of data lines intersecting the gate lines to form a pixel array, where each pixel includes a switching transistor and a pixel electrode. The switching transistor is connected to a gate line and a data line, and the pixel electrode is connected to the switching transistor. The display may further include a common electrode layer and a liquid crystal layer disposed between the substrate and the common electrode layer. The arrangement of the gate lines in the second area ensures that the electrical signals applied to the gate lines are distributed evenly, reducing the risk of signal distortion and improving the overall display quality. The invention is particularly useful in high-resolution displays where precise control of the gate signals is critical.
7. The display defined in claim 1 , wherein the dummy pixels do not include anodes.
A display system includes a plurality of pixels arranged in an array, where each pixel comprises a light-emitting element and a dummy pixel. The dummy pixels are positioned adjacent to the light-emitting elements to reduce visual artifacts such as color mixing or crosstalk. The dummy pixels are designed to block or absorb stray light, improving contrast and image clarity. In this specific configuration, the dummy pixels do not include anodes, which are typically used in light-emitting elements to inject charge carriers. By omitting the anodes, the dummy pixels are simplified in structure, reducing manufacturing complexity and cost while maintaining their functional role in light blocking. The display system may be used in high-resolution applications where minimizing visual distortions is critical, such as in OLED or microLED displays. The absence of anodes in the dummy pixels ensures they do not emit light, further enhancing contrast and preventing unintended light leakage. This design allows for precise control over light emission and absorption, improving overall display performance.
8. The display defined in claim 1 , wherein the dummy pixels are positioned in the notch.
Display technology and display screen design. The invention relates to a display device with a notch. The display includes a display panel and a plurality of pixels arranged on the display panel. A notch is formed in the display panel. The display further comprises dummy pixels. These dummy pixels are positioned within the area of the notch.
9. The display defined in claim 8 , wherein the dummy pixels are positioned on the substrate in an inactive area of the display.
A display system includes a substrate with an active area for displaying images and an inactive area surrounding the active area. The display further includes a plurality of dummy pixels positioned on the substrate in the inactive area. These dummy pixels are electrically connected to a plurality of signal lines, which are also connected to a plurality of active pixels in the active area. The dummy pixels are configured to receive signals from the signal lines but do not emit light. The signal lines are used to transmit data and control signals to the active pixels, and the dummy pixels help maintain signal integrity by balancing electrical loads and reducing signal reflections. The inactive area, where the dummy pixels are located, does not contribute to image display but supports the electrical and structural integrity of the display. The dummy pixels may be arranged in a pattern that mirrors the active pixels to ensure consistent signal distribution. This design improves display performance by minimizing signal distortion and enhancing uniformity across the active area.
10. The display defined in claim 1 , wherein rows in the first area of the display are interrupted by the notch.
A display system includes a screen with a first area and a second area, where the first area is configured to display a first set of content and the second area is configured to display a second set of content. The first area includes multiple rows of content, and a notch is positioned within the first area, causing interruptions in the rows of content. The notch is a cutout or indentation in the display, typically housing a front-facing camera, sensor, or other hardware component. The second area may be positioned adjacent to the first area and may display different content, such as notifications, status indicators, or additional user interface elements. The display system may be part of a mobile device, tablet, or other electronic device. The notch allows for the integration of necessary hardware while maintaining a near-full-screen display. The rows of content in the first area are visually divided or segmented by the notch, requiring the content to adapt to the notch's shape and position. The display may use software-based solutions to dynamically adjust content layout around the notch, ensuring a seamless user experience despite the physical interruption. The system may also include touch-sensitive regions that extend into the notch, allowing for user interaction with the hardware components housed within it. The overall design aims to maximize screen real estate while accommodating essential device features.
11. A display having an active area and an inactive area, comprising: a substrate with a notch, wherein the notch has first and second opposing sides; organic light-emitting diode pixels on the substrate that form the active area, wherein some of the organic light-emitting diode pixels are positioned on the first side of the notch and some of the organic light-emitting diode pixels are positioned on the second side of the notch; display driver circuitry; gate lines coupled to the display driver circuitry and rows of the organic light-emitting diode pixels; and dummy pixels that are coupled to at least some of the gate lines and that are formed in the inactive area between the active area and the notch.
This invention relates to display technology, specifically addressing the challenge of integrating organic light-emitting diode (OLED) pixels around a notch in a display substrate. The display includes an active area with OLED pixels and an inactive area surrounding it. A notch in the substrate divides the active area, with OLED pixels positioned on both sides of the notch. The display driver circuitry controls the OLED pixels via gate lines connected to rows of pixels. To ensure proper operation, dummy pixels are placed in the inactive area between the active area and the notch. These dummy pixels are connected to at least some of the gate lines, helping to maintain electrical stability and signal integrity across the display. The notch allows for the integration of additional components, such as cameras or sensors, while preserving the functionality of the OLED pixels on both sides. The dummy pixels prevent signal distortion and ensure uniform performance, even with the notch disrupting the typical pixel layout. This design enables full-screen displays with notches while maintaining display quality and reliability.
12. The display defined in claim 11 , wherein the dummy pixels do not emit light.
A display system includes a plurality of light-emitting pixels and a plurality of dummy pixels arranged in a matrix. The dummy pixels are positioned to reduce visual artifacts such as moiré patterns, flickering, or color breakup that can occur in high-resolution or high-refresh-rate displays. The dummy pixels are electrically connected to the light-emitting pixels but do not emit light, serving as non-emissive elements that disrupt interference patterns without contributing to image formation. The system may include a driver circuit configured to control the light-emitting pixels while ignoring or bypassing the dummy pixels during image rendering. The dummy pixels may be distributed in a pattern that optimizes artifact suppression while maintaining display uniformity. This approach enhances visual quality in displays used in virtual reality, augmented reality, or high-performance electronic devices by mitigating distortions caused by pixel arrangement or refresh rate mismatches. The dummy pixels may be physically identical to the light-emitting pixels but lack an active light-emitting layer or are otherwise disabled to prevent emission. The system may further include a substrate supporting the pixels and a controller to manage pixel activation, ensuring the dummy pixels remain inactive during operation. This design improves display performance without increasing power consumption or complexity.
13. The display defined in claim 11 , wherein the dummy pixels do not contain emissive material for light-emitting diodes.
A display system includes a plurality of display pixels and dummy pixels arranged in a matrix. The display pixels are configured to emit light for image display, while the dummy pixels are non-emissive and do not contain emissive material for light-emitting diodes. The dummy pixels are positioned to reduce visual artifacts, such as moiré patterns or color shifts, that may arise from interactions between the display and external optical elements like camera lenses or filters. The dummy pixels may be distributed in a pattern that disrupts periodic structures in the display, improving image quality when viewed through optical systems. The display may be an organic light-emitting diode (OLED) or microLED display, where the dummy pixels lack the emissive layers present in active display pixels. This design helps maintain high resolution while minimizing interference effects in applications like augmented reality or high-resolution imaging. The dummy pixels may also serve as structural or electrical elements without contributing to light emission.
14. The display defined in claim 11 , wherein the dummy pixels do not include anodes.
A display system addresses the challenge of improving image quality and reducing power consumption in electronic displays, particularly in organic light-emitting diode (OLED) displays. The system incorporates dummy pixels that mimic the behavior of active pixels but are optimized to reduce power usage and enhance visual performance. These dummy pixels are strategically placed to compensate for variations in brightness and color across the display, ensuring uniform output without the need for additional power-intensive components. Unlike active pixels, the dummy pixels do not include anodes, which are typically used to emit light in conventional OLED structures. By omitting anodes, the dummy pixels avoid unnecessary power consumption while still contributing to the display's overall functionality. This design allows for more efficient power management and improved display uniformity, making the system suitable for high-resolution and energy-efficient applications. The dummy pixels can be integrated into the display's pixel array to correct for defects or inconsistencies in the active pixels, further enhancing the display's reliability and performance. The system is particularly useful in applications where power efficiency and image quality are critical, such as in portable electronic devices and high-end displays.
15. The display defined in claim 11 , wherein the dummy pixels impose loading on the gate lines of rows interrupted by the notch.
A display system with a notch in its active area includes a plurality of gate lines and data lines forming an array of pixels. The notch creates gaps in the gate lines, which can lead to signal integrity issues due to uneven loading. To address this, dummy pixels are integrated into the display structure. These dummy pixels are connected to the gate lines of the rows interrupted by the notch, effectively balancing the electrical load on those lines. By matching the loading conditions of the interrupted gate lines to those of uninterrupted lines, the dummy pixels ensure uniform signal propagation and reduce distortions in the display. The dummy pixels may be placed adjacent to the notch or distributed along the affected gate lines to maintain consistent electrical characteristics. This approach improves display performance by mitigating signal delays and voltage drops that could otherwise degrade image quality in the vicinity of the notch. The solution is particularly useful in displays with irregular shapes or cutouts, such as those used in smartphones or wearable devices.
16. A display having an active area and an inactive area, comprising: a substrate with a notch, wherein the notch has first and second opposing sides connected by a third side; organic light-emitting diode pixels on the substrate that form the active area, wherein some of the organic light-emitting diode pixels are positioned on the first side of the notch and some of the organic light-emitting diode pixels are positioned on the second side of the notch; display driver circuitry; data lines coupled to the display driver circuitry and the organic light-emitting diode pixels; and gate lines coupled to the display driver circuitry and the organic light-emitting diode pixels, wherein the organic light-emitting diode pixels are arranged in columns and rows, wherein the gate lines in a first area of the display that includes the notch are coupled to fewer of the organic light-emitting diode pixels than the gate lines in a second area of the display, wherein the gate lines in the first area include a gate line that extends in the inactive area between the notch and the active area from the first side of the notch to the second side of the notch, wherein the gate line in the first area of the display is coupled to only one gate driver, and wherein an additional gate line in the second area of the display is coupled to first and second gate drivers.
This invention relates to a display with an active area and an inactive area, featuring a substrate that includes a notch. The notch has first and second opposing sides connected by a third side. Organic light-emitting diode (OLED) pixels are arranged on the substrate to form the active area, with some pixels positioned on the first side of the notch and others on the second side. The display includes driver circuitry, data lines, and gate lines. The data and gate lines connect the driver circuitry to the OLED pixels. The pixels are organized in columns and rows, with gate lines in a first area of the display (including the notch) connected to fewer pixels than gate lines in a second area. In the first area, a gate line extends through the inactive area between the notch and the active area, spanning from the first side to the second side of the notch. This gate line is coupled to only one gate driver. In contrast, an additional gate line in the second area is connected to both a first and a second gate driver. This design optimizes the routing of gate lines around the notch while maintaining efficient pixel control.
17. The display defined in claim 16 , wherein the gate line extends parallel to the third side of the notch in the inactive area between the notch and the active area from the first side of the notch to the second side of the notch.
This invention relates to display panel designs, specifically addressing the layout of gate lines in areas with notches. The problem solved is optimizing the arrangement of gate lines in display panels that have notches, such as those used in smartphones or other devices with non-rectangular screens. The notch creates an inactive area adjacent to the active display region, and improper gate line routing can lead to inefficiencies in signal transmission, increased manufacturing complexity, or reduced display performance. The invention describes a display panel with a notch in the inactive area, where the notch has a first side, a second side, and a third side. A gate line extends parallel to the third side of the notch, running between the notch and the active area. The gate line spans from the first side of the notch to the second side, ensuring continuous signal routing across the notch without disrupting the display's functionality. This parallel alignment minimizes signal path length, reduces resistance, and simplifies manufacturing by avoiding sharp bends or complex routing patterns. The design ensures uniform signal distribution and maintains display performance while accommodating the notch's geometry. The gate line's placement and orientation optimize space utilization in the inactive area, preventing interference with other components or structural elements. This solution is particularly useful in displays with irregular shapes or cutouts, where traditional gate line routing may be impractical.
18. The display defined in claim 16 , wherein the gate line is one of multiple gate lines in the first area that extends in the inactive area between the notch and the active area from the first side of the notch to the second side of the notch.
A display device includes a substrate with an active area for displaying images and an inactive area surrounding the active area. The inactive area contains a notch, which is a cutout or indentation in the substrate. The display device includes multiple gate lines in the inactive area that extend from a first side of the notch to a second side of the notch, crossing the inactive area between the notch and the active area. These gate lines are part of a circuit structure that controls the display elements in the active area. The gate lines are arranged to ensure proper electrical connectivity and signal transmission despite the presence of the notch, which may be used for accommodating components such as cameras, sensors, or other functional elements. The design allows for efficient routing of signals while maintaining the structural integrity of the display. The gate lines may be part of a thin-film transistor (TFT) array or other driving circuitry integrated into the display panel. The configuration ensures that the display operates correctly even with the notch present, providing flexibility in display design for modern electronic devices.
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March 23, 2020
January 25, 2022
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