A scan signal driver including: a plurality of stages for outputting scan signals and sensing signals, wherein a kth stage among the stages is connected to a kth scan signal line and a kth sensing signal line, and wherein the kth stage includes: a first output unit configured to output a scan clock signal input to a fit scan clock terminal to the kth scan signal line as a kth scan signal and to output a sensing clock signal input to a first sensing clock terminal to the kth sensing signal line as a k sensing signal when a pull-up node has a gate-on voltage; and a second output unit configured to output a carry clock signal input to a first carry clock terminal as a kth carry signal to a carry output terminal when the pull-up node has the gate-on voltage.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A scan signal driver, comprising: a plurality of stages for outputting scan signals and sensing signals, wherein a k th stage among the stages is connected to a k th scan signal line and a k th sensing signal line, and wherein the k th stage comprises: a first output unit configured to output a scan clock signal input to a first scan clock terminal to the k th scan signal line as a k th scan signal and to output a sensing clock signal input to a first sensing clock terminal to the k th sensing signal line as a k th sensing signal when a pull-up node has a gate-on voltage; and a second output unit configured to output a carry clock signal input to a first carry clock terminal as a k th carry signal to a carry output terminal when the pull-up node has the gate-on voltage, wherein a frame period comprises an active period and a vertical blank period, and wherein the k th stage further comprises: a sensing controller configured to apply the gate-on voltage to the pull-up node during the vertical blank period when a sensing control signal of the gate-on voltage is input to a sensing control terminal during the active period.
This invention relates to a scan signal driver for display panels, addressing the need for efficient signal generation and sensing during display operation. The driver includes multiple stages, each connected to a scan signal line and a sensing signal line. Each stage outputs scan signals, sensing signals, and carry signals based on clock inputs and a pull-up node voltage. During normal operation, the stage outputs a scan clock signal as a scan signal and a sensing clock signal as a sensing signal when the pull-up node is at a gate-on voltage. Simultaneously, a carry clock signal is output as a carry signal. The frame period is divided into an active period and a vertical blank period. A sensing controller in each stage applies the gate-on voltage to the pull-up node during the vertical blank period if a sensing control signal is received during the active period. This allows for sensing operations, such as detecting defects or panel characteristics, without disrupting the active display period. The design ensures synchronized signal generation and sensing, improving display functionality and diagnostic capabilities.
2. The scan signal driver of claim 1 , wherein the first output unit comprises: a first scan pull-up transistor configured to be turned on by the gate-on voltage of the pull-up node to output the scan clock signal to the k th scan signal line; and a first sensing pull-up transistor configured to be turned on by the gate-on voltage of the pull-up node to output the sensing clock signal to the k th sensing signal line.
Electronic display driver circuits. This invention relates to scan signal drivers for driving display panels and addresses the issue of efficiently and reliably outputting different types of clock signals to display lines. The described scan signal driver includes an output unit designed to drive a k th scan signal line and a k th sensing signal line. This output unit is characterized by a first scan pull-up transistor. This transistor is configured to be activated by a gate-on voltage present at a pull-up node. When activated, the first scan pull-up transistor is responsible for transmitting a scan clock signal to the k th scan signal line. Additionally, the output unit incorporates a first sensing pull-up transistor. Similar to the scan pull-up transistor, this sensing transistor is also activated by the gate-on voltage of the pull-up node. Upon activation, the first sensing pull-up transistor outputs a sensing clock signal to the k th sensing signal line. Therefore, the output unit utilizes separate pull-up transistors, controlled by a common gate-on voltage, to independently deliver a scan clock signal and a sensing clock signal to their respective signal lines.
3. The scan signal driver of claim 1 , wherein the second output unit comprises a carry pull-up transistor configured to be turned on by the gate-on voltage of the pull-up node to output the carry clock signal to the carry output terminal.
A scan signal driver circuit for display panels, particularly in organic light-emitting diode (OLED) displays, addresses the need for efficient signal propagation in gate driver circuits. The circuit includes a pull-up node that controls the output of scan signals and carry signals to adjacent stages. The second output unit within the driver circuit contains a carry pull-up transistor that is activated by a gate-on voltage at the pull-up node. When turned on, this transistor outputs a carry clock signal to a carry output terminal, enabling synchronized signal transmission to subsequent stages. This design ensures reliable signal propagation while minimizing power consumption and circuit complexity. The carry pull-up transistor operates in conjunction with other components, such as a pull-down unit and a carry pull-down unit, to maintain stable signal levels and prevent signal distortion. The overall structure enhances the efficiency and performance of the gate driver circuit in large-area displays, ensuring uniform and accurate signal distribution across the display panel.
4. The scan signal driver of claim 1 , wherein the first output unit applies a first gate-off voltage to the k th scan signal line and the k th sensing line when a pull-down node has the gate-on voltage, and wherein the second output unit applies the first gate-off voltage to the carry output terminal when the pull-down node has the gate-on voltage.
This invention relates to a scan signal driver circuit for display panels, particularly addressing issues in driving scan and sensing lines in display devices. The circuit includes a first output unit and a second output unit, each connected to a pull-down node that controls the application of voltages to scan and sensing lines. When the pull-down node is at a gate-on voltage, the first output unit applies a first gate-off voltage to both the k-th scan signal line and the k-th sensing line, ensuring synchronized deactivation. Simultaneously, the second output unit applies the same first gate-off voltage to a carry output terminal, preventing unintended signal propagation. This design improves signal integrity and reduces crosstalk between scan and sensing lines, enhancing display performance. The circuit ensures that all connected lines are properly reset to a gate-off state when the pull-down node is active, maintaining consistent timing and reducing power consumption. The invention is particularly useful in display technologies requiring precise control of scan and sensing signals, such as OLED or LCD panels with integrated touch sensing capabilities.
5. The scan signal driver of claim 4 , wherein the first output unit comprises: a first scan pull-down transistor configured to be turned on by the gate-on voltage of the pull-down node to output the first gate-off voltage input to a first gate-off terminal to the k th scan signal line; and a first sensing pull-down transistor configured to be turned on by the gate-on voltage of the pull-down node to output the first gate-off voltage of the first gate-off terminal to the k th sensing signal line.
This invention relates to a scan signal driver circuit for display panels, specifically addressing the need for efficient and reliable signal distribution in display driving systems. The circuit includes a first output unit designed to control both scan and sensing signal lines using a shared pull-down node. The first output unit contains a first scan pull-down transistor and a first sensing pull-down transistor. Both transistors are activated by a gate-on voltage from the pull-down node. When turned on, the first scan pull-down transistor outputs a first gate-off voltage from a first gate-off terminal to a k-th scan signal line, while the first sensing pull-down transistor simultaneously outputs the same gate-off voltage to a k-th sensing signal line. This dual-output design ensures synchronized control of both scan and sensing signals, reducing circuit complexity and improving signal integrity. The shared pull-down node minimizes power consumption and simplifies the overall driver architecture, making it suitable for high-resolution and large-area display applications. The invention enhances display driving efficiency by integrating multiple signal control functions into a compact and energy-efficient configuration.
6. The scan signal driver of claim 4 , wherein the second output unit comprises a carry pull-down transistor configured to be turned on by the gate-on voltage of the pull-down node to output the first gate-off voltage of the first gate-off terminal to the carry output terminal.
The invention relates to a scan signal driver circuit for display panels, specifically addressing the need for efficient signal transmission and noise reduction in gate driver circuits. The circuit includes a pull-down node that controls the operation of transistors within the driver. A second output unit is provided to generate a carry signal, which is used to propagate timing signals between stages in the driver. This unit includes a carry pull-down transistor that, when activated by a gate-on voltage at the pull-down node, outputs a first gate-off voltage from a first gate-off terminal to a carry output terminal. This ensures that the carry signal is properly reset to a low state, preventing signal interference and improving synchronization between driver stages. The circuit enhances reliability and performance in display panel driving by maintaining precise timing control and minimizing signal distortion. The pull-down node's voltage determines the transistor's on/off state, allowing the carry signal to be accurately controlled. This design is particularly useful in large-area displays where signal integrity is critical.
7. The scan signal driver of claim 4 , wherein the k stage comprises: a third pull-up node controller configured to hold the pull-up node at the first gate-off voltage when the scan clock signal or the sensing clock signal has the gate-on voltage and the pull-down node has the gate-on voltage; and an inverter configured to apply the first gate-off voltage to the pull-down node when the pull-up node has the gate-on voltage.
This invention relates to a scan signal driver circuit for display panels, specifically addressing the need for stable and reliable signal control in gate driver circuits. The circuit includes a k-stage pull-up node controller that ensures proper voltage levels at the pull-up and pull-down nodes during operation. The third pull-up node controller within the k-stage holds the pull-up node at a first gate-off voltage when either the scan clock signal or the sensing clock signal has a gate-on voltage and the pull-down node is also at a gate-on voltage. This prevents unintended activation of the pull-up node during these conditions. Additionally, an inverter in the k-stage applies the first gate-off voltage to the pull-down node when the pull-up node is at a gate-on voltage, ensuring that the pull-down node remains deactivated during pull-up node activation. The circuit improves signal integrity by preventing voltage conflicts and ensuring proper timing of gate-on and gate-off states, which is critical for accurate scan signal generation in display applications. The design enhances reliability and performance in gate driver circuits used in display panels.
8. The scan signal driver of claim 7 , wherein the third pull-up node controller comprises: a (10-1) th transistor configured to be turned on by the gate-on voltage of the scan clock signal or the gate-on voltage of the sensing clock signal to connect the pull-up node with the carry output terminal; and a (10-2) th transistor configured to be turned on by the gate-on voltage of the pull-down node to connect the (10-1) th transistor with the carry output terminal.
This invention relates to a scan signal driver circuit for display panels, specifically addressing the need for efficient signal transmission and stable operation in display driving circuits. The circuit includes a third pull-up node controller that enhances the reliability of carry signal output during scan and sensing operations. The controller comprises a first transistor and a second transistor. The first transistor is configured to connect a pull-up node to a carry output terminal when activated by either a gate-on voltage from a scan clock signal or a gate-on voltage from a sensing clock signal. This ensures that the carry signal is properly transmitted during both display scanning and panel sensing phases. The second transistor is configured to connect the first transistor to the carry output terminal when activated by a gate-on voltage from a pull-down node. This additional control mechanism prevents unintended signal interference and ensures stable carry signal output. The design improves the robustness of the scan signal driver by providing redundant control paths and minimizing signal distortion during switching operations. The circuit is particularly useful in high-resolution displays where precise timing and signal integrity are critical.
9. The scan signal driver of claim 7 , wherein the third pull-up node controller comprises: a (10-1) th transistor configured to be turned on by the gate-on voltage of the scan clock signal or the gate-on voltage of the sensing clock signal to connect the pull-up node with the carry output terminal; and a (10-2) th transistor configured to be turned on by the gate-on voltage of the scan clock signal or the gate-on voltage of the sensing clock signal to connect the (10-1) th transistor with the carry output terminal.
This invention relates to a scan signal driver circuit used in display panels, particularly for controlling the transmission of scan and sensing signals. The problem addressed is the need for a reliable and efficient way to manage signal propagation in display driver circuits, ensuring proper synchronization between scan and sensing operations. The scan signal driver includes a third pull-up node controller that regulates the connection between a pull-up node and a carry output terminal. This controller comprises two transistors: a first transistor (10-1) and a second transistor (10-2). The first transistor (10-1) is configured to connect the pull-up node to the carry output terminal when activated by either a gate-on voltage from a scan clock signal or a gate-on voltage from a sensing clock signal. The second transistor (10-2) is similarly activated by the same gate-on voltages and is positioned to connect the first transistor (10-1) to the carry output terminal. This dual-transistor arrangement ensures stable signal transmission, preventing signal distortion or delays during switching between scan and sensing modes. The design optimizes signal integrity and synchronization in display driver circuits, particularly in applications requiring both display scanning and touch sensing functionalities.
10. The scan signal driver of claim 7 , wherein the inverter comprises: an (11-1) th transistor configured to be turned on by the gate-on voltage of the pull-up node to apply the first gate-off voltage to the pull-down node; an (11-2) th transistor configured to be turned on by the gate-on voltage of the pull-up node to connect the pull-down node with a (13-1) th transistor; and a twelfth transistor configured to be turned on by the gate-on voltage of another carry clock signal input to a second carry clock terminal to apply the gate-on voltage to the pull-down node.
This invention relates to a scan signal driver circuit used in display devices, particularly for generating scan signals in organic light-emitting diode (OLED) displays or similar display technologies. The problem addressed is the need for a stable and efficient scan signal driver that can reliably control the timing and voltage levels of scan signals to drive gate lines in a display panel. The scan signal driver includes a pull-up node and a pull-down node, where the pull-up node controls the output of a scan signal based on a clock signal and a carry signal. The inverter circuit within the driver is designed to stabilize the pull-down node voltage. The inverter includes three transistors: a first transistor that applies a first gate-off voltage to the pull-down node when the pull-up node is at a gate-on voltage, a second transistor that connects the pull-down node to a third transistor when the pull-up node is at a gate-on voltage, and a third transistor that applies a gate-on voltage to the pull-down node when a carry clock signal is received at a second carry clock terminal. This configuration ensures that the pull-down node is properly discharged or charged to maintain stable scan signal output. The circuit improves reliability by preventing voltage fluctuations and ensuring precise timing control in the scan signal generation process.
11. The scan signal driver of claim 7 , wherein the inverter comprises a thirteenth transistor configured to be turned on by the gate-on voltage of the pull-down node to apply the gate-on voltage to the pull-down node.
A scan signal driver circuit for display panels, particularly in organic light-emitting diode (OLED) displays, addresses the need for stable and reliable gate signal control. The circuit includes a pull-down node that regulates the output of scan signals to gate lines. A key component is an inverter that ensures proper voltage levels at the pull-down node. The inverter contains a transistor that, when activated by a gate-on voltage, reinforces the pull-down node's voltage, preventing signal distortion and maintaining consistent gate line operation. This design improves the stability of scan signal transmission, reducing flicker and enhancing display uniformity. The transistor in the inverter operates in response to the pull-down node's voltage, creating a feedback loop that stabilizes the circuit's performance. The overall system ensures accurate timing and voltage levels for driving gate lines, which is critical for proper pixel activation in display panels. This solution is particularly useful in high-resolution and large-area displays where signal integrity is paramount. The circuit's design minimizes power consumption while maintaining high reliability, addressing common issues in display driver electronics.
12. The scan signal driver of claim 7 , wherein the inverter further comprises: a fourteenth transistor configured to be turned on by the gate-on voltage of the pull-down node to apply the gate-on voltage between an (11-1) th transistor and an (11-2) th transistor.
This invention relates to a scan signal driver circuit for display panels, specifically addressing the need for stable and reliable signal generation in organic light-emitting diode (OLED) or liquid crystal display (LCD) systems. The circuit includes an inverter with a pull-down node that controls the switching of transistors to generate precise scan signals. The inverter further incorporates a fourteenth transistor that, when activated by the gate-on voltage of the pull-down node, applies this voltage between an eleventh transistor and a twelfth transistor. This configuration ensures proper voltage distribution and switching behavior, preventing signal distortion and improving the overall stability of the scan signal output. The eleventh and twelfth transistors are part of a pull-up or pull-down network, where the fourteenth transistor enhances their operation by ensuring consistent voltage levels. This design minimizes leakage currents and enhances the circuit's robustness against voltage fluctuations, leading to more accurate and reliable scan signal generation in display driver applications. The invention is particularly useful in high-resolution displays requiring precise timing and signal integrity.
13. The scan signal driver of claim 1 , wherein the sensing controller comprises: a first transistor configured to be turned on by the gate-on voltage of the sensing control signal to apply the gate-on voltage to a sensing control node; and a second transistor configured to be turned on by the gate-on voltage of the sensing control node to apply a first control clock signal input to a first control clock terminal to the pull-up node.
This invention relates to a scan signal driver circuit used in display panels, particularly for driving gate lines in display devices. The problem addressed is the need for efficient and reliable control of scan signals during display operation, ensuring proper timing and signal integrity. The scan signal driver includes a sensing controller that regulates the operation of the driver circuit. The sensing controller comprises two transistors: a first transistor and a second transistor. The first transistor is configured to be activated by a gate-on voltage from a sensing control signal, which then applies this gate-on voltage to a sensing control node. The second transistor is activated by the gate-on voltage at the sensing control node, allowing it to pass a first control clock signal from a first control clock terminal to a pull-up node. This configuration ensures precise timing and control of the scan signals, improving the stability and performance of the display panel. The use of these transistors in the sensing controller enables efficient switching and signal propagation, reducing power consumption and enhancing reliability. The invention is particularly useful in high-resolution and large-area displays where precise timing control is critical.
14. The scan signal driver of claim 13 , wherein the sensing controller further comprises a third transistor configured to be turned on by the gate-on voltage of the sensing control node to connect the second transistor with the pull-up node.
A scan signal driver circuit for display panels, particularly organic light-emitting diode (OLED) displays, addresses the challenge of accurately sensing and compensating for threshold voltage variations in driving transistors. The circuit includes a sensing controller that detects these variations during a sensing period to improve display uniformity. The sensing controller comprises a first transistor that connects a pull-up node to a clock signal line, a second transistor that connects the pull-up node to a low-voltage line, and a third transistor that connects the second transistor to the pull-up node. The third transistor is controlled by a gate-on voltage at a sensing control node, enabling precise timing for the sensing operation. During sensing, the third transistor turns on in response to the gate-on voltage, establishing a conductive path between the second transistor and the pull-up node. This configuration ensures accurate voltage level adjustments at the pull-up node, which is critical for stabilizing the scan signal output. The circuit enhances display performance by mitigating threshold voltage shifts in driving transistors, thereby maintaining consistent brightness and image quality across the panel. The design is particularly suited for high-resolution and large-area displays where uniformity is paramount.
15. The scan signal driver of claim 13 , wherein the sensing controller comprises: a third transistor configured to be turned on by a gate-on voltage of a second control clock signal input to a second control clock terminal to connect the second transistor with the first control clock terminal; and a fourth transistor configured to be turned on by the gate-on voltage of the pull-up node to apply the gate-on voltage between the second transistor and the third transistor.
This invention relates to a scan signal driver circuit for display panels, specifically addressing the need for efficient and reliable signal transmission in display driving circuits. The circuit includes a sensing controller that enhances the stability and accuracy of scan signal generation by incorporating additional transistors to manage signal flow. The sensing controller comprises a third transistor and a fourth transistor. The third transistor is configured to be activated by a gate-on voltage from a second control clock signal applied to its second control clock terminal, establishing a connection between a second transistor and a first control clock terminal. This connection facilitates the transfer of control signals necessary for proper scan signal generation. The fourth transistor is activated by the gate-on voltage of a pull-up node, applying this voltage between the second transistor and the third transistor. This ensures that the control signals are accurately transmitted and maintained, improving the overall performance of the scan signal driver. The inclusion of these transistors in the sensing controller enhances the circuit's ability to handle signal variations and maintain consistent output, addressing issues related to signal integrity and timing in display driving applications. The design optimizes the flow of control signals, reducing errors and improving the reliability of the scan signal driver in display systems.
16. The scan signal driver of claim 13 , wherein the sensing controller further comprises: a third transistor configured to be turned on by a gate-on voltage of a second control clock signal input to a second control clock terminal to connect the second transistor with the pull-up node; and a fourth transistor configured to be turned on by the gate-on voltage of the pull-up node to apply the gate-on voltage between the second transistor and the third transistor.
A scan signal driver circuit for display panels, particularly organic light-emitting diode (OLED) displays, addresses the need for stable and efficient signal transmission to control pixel switching. The circuit includes a sensing controller that detects and compensates for variations in display performance, such as threshold voltage shifts in driving transistors. The sensing controller comprises a second transistor that connects a pull-up node to a scan signal output line, ensuring proper signal transmission. To enhance reliability, the sensing controller further includes a third transistor and a fourth transistor. The third transistor is activated by a gate-on voltage from a second control clock signal, linking the second transistor to the pull-up node. The fourth transistor, also activated by the pull-up node's voltage, reinforces the connection between the second and third transistors, ensuring consistent signal integrity. This configuration improves the stability of the scan signal driver by mitigating voltage fluctuations and enhancing the accuracy of pixel control, leading to improved display uniformity and longevity. The circuit is particularly useful in high-resolution and large-area displays where precise signal timing and stability are critical.
17. The scan signal driver of claim 1 , wherein the sensing controller comprises: a (1-1) th transistor configured to be turned on by the gate-on voltage of the sensing control signal to apply the gate-on voltage to a sensing control node; a (1-2) th transistor configured to be turned on by the gate-on voltage of the sensing control signal to connect a third transistor with the sensing node; and a fifth transistor configured to be turned on by the gate-on voltage of the sensing control node to apply the gate-on voltage between the (1-1) th transistor and the (1-2) th transistor.
This invention relates to a scan signal driver circuit for display panels, specifically addressing the need for efficient and reliable sensing control in display driving systems. The invention improves upon conventional scan signal drivers by incorporating a sensing controller with enhanced transistor configurations to optimize signal transmission and reduce power consumption. The sensing controller includes a first transistor that, when activated by a gate-on voltage from a sensing control signal, applies this voltage to a sensing control node. A second transistor, also activated by the gate-on voltage, connects a third transistor to a sensing node, facilitating signal routing. Additionally, a fifth transistor, when turned on by the voltage at the sensing control node, further applies the gate-on voltage between the first and second transistors, ensuring stable signal propagation. This configuration ensures precise control over the sensing operation, minimizing signal distortion and improving the accuracy of display panel diagnostics. The use of multiple transistors in the sensing controller allows for flexible and efficient signal management, addressing issues such as power inefficiency and signal integrity in conventional scan signal drivers. The invention is particularly useful in high-resolution display applications where accurate sensing and low power consumption are critical.
18. The scan signal driver of claim 1 , wherein the k th stage comprises: a first pull-up node controller configured to apply the gate-on voltage to the pull-up node when a carry signal of a previous stage with respect to the k th stage has a gate-on voltage; and a second pull-up node controller configured to apply the first gate-off voltage to the pull-up node when a carry signal of a subsequent stage with respect to the k th stage has a gate-on voltage.
This invention relates to a scan signal driver circuit used in display panels, particularly for controlling the timing and voltage levels of scan signals in stages of the driver. The problem addressed is ensuring stable and accurate scan signal generation while minimizing power consumption and signal interference between stages. The scan signal driver includes multiple stages, each generating a scan signal and a carry signal for the next stage. The k-th stage includes a first pull-up node controller that applies a gate-on voltage to a pull-up node when a carry signal from the previous stage (k-1) is at a gate-on voltage. This ensures proper timing synchronization between stages. Additionally, a second pull-up node controller applies a first gate-off voltage to the pull-up node when a carry signal from the subsequent stage (k+1) is at a gate-on voltage. This prevents signal interference and maintains stable operation by preventing unintended activation of the pull-up node due to subsequent stages. The pull-up node controls the output of the scan signal, and its voltage state determines whether the scan signal is active (gate-on) or inactive (gate-off). The first and second controllers work together to ensure that the pull-up node is only activated when intended, improving signal integrity and reducing power consumption. The carry signal from each stage propagates to the next stage, enabling sequential activation of scan signals across the display panel. This design enhances reliability and efficiency in display driver circuits.
19. The scan signal driver of claim 18 , wherein the first pull-up node controller comprises: a sixth transistor configured to be turned on by the gate-on voltage of the carry signal of the previous stage to apply the gate-on voltage to the pull-up node.
This invention relates to a scan signal driver circuit for display panels, specifically addressing the need for efficient and reliable signal propagation in shift registers used in display driving circuits. The circuit includes a pull-up node controller that ensures proper timing and stability of scan signals, which are essential for driving gate lines in display devices. The scan signal driver comprises a pull-up node controller that includes a sixth transistor. This transistor is configured to be turned on by the gate-on voltage of a carry signal from a previous stage. When activated, the sixth transistor applies the gate-on voltage to a pull-up node, which controls the output of the scan signal. This mechanism ensures that the scan signal is accurately synchronized with the carry signal from the preceding stage, maintaining proper signal propagation across multiple stages in the shift register. The pull-up node controller also includes additional transistors that work in conjunction with the sixth transistor to stabilize the pull-up node voltage. These transistors prevent unwanted voltage fluctuations, ensuring that the scan signal is generated at the correct time and with the appropriate voltage level. The circuit is designed to minimize power consumption while maintaining high reliability, making it suitable for use in large-area display panels where precise timing and signal integrity are critical.
20. The scan signal driver of claim 18 , wherein the first pull-up node controller comprises: a (6-1) th a transistor configured to be turned on by the gate-on voltage of the carry signal of the previous stage to apply the gate-on voltage to the pull-up node; a (6-2) th transistor configured to be turned on by the gate-on voltage of the carry signal of the previous stage to connect the (6-1) th transistor with the pull-up node; and a seventh transistor configured to be turned on by the gate-on voltage of the k th carry signal to apply the gate-on voltage between the (6-1) th transistor and the (6-2) th transistor.
This invention relates to a scan signal driver circuit used in display panels, specifically addressing the need for stable and efficient signal transmission in shift register circuits. The circuit includes a first pull-up node controller designed to manage the voltage levels at a pull-up node, which is critical for controlling the output of scan signals. The controller comprises three transistors: a first transistor that, when activated by a gate-on voltage from a carry signal of a previous stage, applies this voltage to the pull-up node; a second transistor that, also activated by the same gate-on voltage, connects the first transistor to the pull-up node; and a third transistor that, when turned on by a gate-on voltage from a k-th carry signal, applies the gate-on voltage between the first and second transistors. This configuration ensures proper voltage distribution and signal integrity, preventing signal distortion and improving the reliability of the scan signal driver. The circuit is particularly useful in display technologies requiring precise timing and stable signal propagation, such as organic light-emitting diode (OLED) and liquid crystal display (LCD) panels. The transistors are configured to work in tandem, ensuring that the pull-up node receives the correct voltage levels at the right time, which is essential for accurate scan signal generation.
21. The scan signal driver of claim 18 , wherein the second pull-up node controller comprises: an eighth transistor configured to be turned on by the gate-on voltage of the carry signal of the subsequent stage to connect the pull-up node with the carry output terminal.
This invention relates to a scan signal driver circuit used in display panels, particularly for controlling the timing of scan signals in display driving systems. The problem addressed is the need for precise and efficient control of scan signal propagation between stages in a shift register, ensuring accurate timing and reducing power consumption. The scan signal driver includes a pull-up node controller that regulates the voltage at a pull-up node, which in turn controls the output of scan signals. The pull-up node controller comprises multiple transistors that manage the charging and discharging of the pull-up node based on input signals. Specifically, the second pull-up node controller includes an eighth transistor that is activated by the gate-on voltage of a carry signal from a subsequent stage. When turned on, this transistor connects the pull-up node to the carry output terminal, allowing the carry signal to influence the pull-up node's voltage. This ensures proper synchronization between stages, preventing signal delays or misalignment in the scan signal propagation. The circuit design optimizes signal integrity and reduces power consumption by minimizing unnecessary voltage transitions. The transistors are configured to operate in a low-power mode when inactive, further enhancing efficiency. This solution is particularly useful in large-area displays where precise timing and energy efficiency are critical.
22. The scan signal driver of claim 18 , wherein the second pull-up node controller comprises: an (8-1) th transistor configured to turned on by the gate-on voltage of the carry signal of the subsequent stage to connect the pull-up node with a first gate-off terminal to which a first gate-off voltage is applied; and an (8-2) th transistor configured to be turned on by the gate-on voltage of the carry signal of the subsequent stage to connect the (8-1) th transistor with the first gate-off terminal.
This invention relates to a scan signal driver circuit for display panels, specifically addressing the need for stable and reliable signal transmission in shift registers used in display driving circuits. The circuit includes a pull-up node controller that regulates the voltage at a pull-up node to control the output of scan signals. The second pull-up node controller, a key component, comprises two transistors. The first transistor (8-1) is activated by a gate-on voltage from a carry signal of a subsequent stage, connecting the pull-up node to a first gate-off terminal that supplies a first gate-off voltage. The second transistor (8-2) is also activated by the same gate-on voltage, linking the first transistor to the first gate-off terminal. This configuration ensures that the pull-up node is properly reset to a stable off-state voltage, preventing signal distortion and improving the accuracy of scan signal generation. The circuit enhances the reliability of display driving by maintaining precise control over the pull-up node voltage, which is critical for proper timing and synchronization in display operations. The transistors are configured to operate in response to the carry signal, ensuring synchronized reset operations across multiple stages in the shift register. This design minimizes leakage currents and reduces power consumption while maintaining high signal integrity.
23. The scan signal driver of claim 22 , wherein the second pull-up node controller comprises a ninth transistor configured to be turned on by the gate-on voltage of the carry output terminal to connect the carry output terminal between the (8-1) th transistor and the (8-2) th transistor.
This invention relates to a scan signal driver circuit for display panels, specifically addressing the need for efficient and reliable signal propagation in gate driver circuits. The circuit includes a pull-up node controller that regulates the voltage at a pull-up node to control the output of scan signals. The pull-up node controller comprises multiple transistors that manage the charging and discharging of the pull-up node based on input signals and clock signals. A key feature is the inclusion of a second pull-up node controller that further refines the control of the pull-up node. This second controller includes a ninth transistor that is activated by a gate-on voltage from a carry output terminal. When turned on, this transistor connects the carry output terminal between an eighth transistor and an eighth-second transistor, ensuring proper signal routing and stability. The circuit improves signal integrity and reduces power consumption by precisely controlling the timing and voltage levels of the scan signals. The transistors are configured to minimize leakage currents and enhance the overall efficiency of the gate driver circuit. This design is particularly useful in large-area displays where precise timing and low power consumption are critical.
24. The scan signal driver of claim 1 , wherein the k th stage is connected to a (k+1) th scan signal line and a (k+1) th sensing signal line, and wherein the first output unit is configured to output another scan clock signal input to a second scan clock terminal to the (k+1) th scan signal line as a (k+1) scan signal, and to output another sensing clock signal input to a second sensing clock terminal to the (k+1) th sensing signal line as a (k+1) sensing signal when the pull-up node has the gate-on voltage.
In display driver circuits, particularly for organic light-emitting diode (OLED) displays, precise control of scan and sensing signals is critical for proper display operation and defect detection. Traditional scan signal drivers often lack efficient mechanisms to simultaneously drive scan and sensing lines, leading to increased circuit complexity and potential timing mismatches. This invention addresses these issues by enhancing a scan signal driver stage to independently control both scan and sensing signals in a cascaded manner. The driver includes a stage connected to a subsequent scan signal line and a subsequent sensing signal line. When a pull-up node in the stage reaches a gate-on voltage, the stage outputs a scan clock signal to the next scan signal line as a scan signal and a sensing clock signal to the next sensing signal line as a sensing signal. This design ensures synchronized and independent control of scan and sensing operations, improving display performance and defect detection accuracy. The stage's configuration allows for cascaded operation, where each stage drives the next, reducing circuit complexity and ensuring precise timing alignment between scan and sensing signals. This approach is particularly useful in high-resolution displays requiring simultaneous scan and sensing functions.
25. The scan signal driver of claim 24 , wherein the first output unit comprises: a second scan pull-up transistor configured to be turned on by the gate-on voltage of the pull-up node to output the another scan clock signal to the (k+1) th scan signal line; and a second sensing pull-up transistor configured to be turned on by the gate-on voltage of the pull-up node to output the another sensing clock signal to the (k+1) th sensing signal line.
This invention relates to a scan signal driver circuit for display panels, specifically addressing the need for efficient signal distribution in gate driver circuits. The circuit includes a first output unit that generates scan and sensing signals for adjacent scan lines. The first output unit contains a second scan pull-up transistor and a second sensing pull-up transistor, both controlled by a gate-on voltage from a pull-up node. When activated, the second scan pull-up transistor outputs a scan clock signal to the (k+1)th scan signal line, while the second sensing pull-up transistor outputs a sensing clock signal to the (k+1)th sensing signal line. This dual-transistor configuration ensures synchronized signal propagation, improving display panel performance by reducing signal delay and enhancing uniformity. The design is particularly useful in large-area displays where precise timing and signal integrity are critical. The pull-up node's gate-on voltage controls both transistors, ensuring coordinated operation between scan and sensing signals. This approach optimizes the gate driver's efficiency while maintaining signal accuracy across multiple scan lines.
26. The scan signal driver of claim 24 , wherein the first output unit applies a first gate-off voltage to the (k+1) th scan signal line and the (k+1) th sensing line when the pull-down node has the gate-on voltage.
This invention relates to a scan signal driver circuit used in display panels, particularly for controlling scan and sensing lines in a display. The problem addressed is the need to efficiently manage voltage levels in scan and sensing lines during display operation to prevent unwanted signal interference and ensure proper display functionality. The scan signal driver includes a first output unit that applies a first gate-off voltage to both the (k+1)th scan signal line and the (k+1)th sensing line when a pull-down node in the circuit has a gate-on voltage. This ensures that the (k+1)th scan and sensing lines are simultaneously stabilized at the gate-off voltage, preventing signal leakage or cross-talk between adjacent lines. The pull-down node controls the voltage level applied to the output lines, and when it is in the gate-on state, the first output unit actively drives both the scan and sensing lines to the gate-off voltage. This synchronization between the scan and sensing lines improves display uniformity and reduces power consumption by avoiding unnecessary voltage fluctuations. The circuit may also include additional components, such as a pull-up node and a second output unit, to further regulate the scan and sensing line voltages during different operational phases. The overall design enhances display performance by maintaining precise control over signal timing and voltage levels.
27. The scan signal driver of claim 26 , wherein the first output unit comprises: a second scan pull-down transistor configured to be turned on by the gate-on voltage of the pull-down node to output the first gate-off voltage input to a first gate-off terminal to the (k+1) th scan signal line; and a second sensing pull-down transistor configured to be turned on by the gate-on voltage of the pull-down node to output the first gate-off voltage of the first gate-off terminal to the (k+1) th sensing signal line.
This invention relates to a scan signal driver circuit for display panels, specifically addressing the need for stable and synchronized signal distribution in display driving systems. The circuit includes a scan signal driver with an output unit designed to control the transmission of gate-off voltages to subsequent scan and sensing signal lines. The output unit contains a second scan pull-down transistor and a second sensing pull-down transistor, both activated by a gate-on voltage from a pull-down node. When turned on, the second scan pull-down transistor outputs a first gate-off voltage to the (k+1)th scan signal line, while the second sensing pull-down transistor simultaneously outputs the same gate-off voltage to the (k+1)th sensing signal line. This ensures synchronized and reliable signal distribution, preventing signal interference and improving display uniformity. The transistors are configured to operate in response to the pull-down node's voltage state, ensuring precise timing and stability in the signal output. The design enhances the performance of display panels by maintaining consistent signal levels across multiple lines, reducing errors in pixel charging and improving overall display quality.
28. The scan signal driver of claim 26 , wherein the k th stage comprises: a first pull-up node controller configured to apply the gate-on voltage to the pull-up node when a carry signal of a previous stage with respect to the k th stage has a gate-on voltage; a second pull-up node controller configured to apply the first gate-off voltage to the pull-up node when a carry signal of a subsequent stage with respect to the k th stage has a gate-on voltage; and a third pull-up node controller configured to hold the pull-up node at the first gate-off voltage when the pull-down node has the gate-on voltage.
This invention relates to a scan signal driver circuit used in display panels, particularly for controlling the timing and voltage levels of scan signals in a gate driver circuit. The problem addressed is ensuring stable and accurate scan signal generation while preventing signal distortion or interference between adjacent stages in the driver circuit. The scan signal driver includes multiple stages, each generating a scan signal and a carry signal for the next stage. The kth stage of the driver circuit includes three pull-up node controllers. The first controller applies a gate-on voltage to the pull-up node when the carry signal from the previous stage (k-1) is at the gate-on voltage, enabling the kth stage to activate. The second controller applies a first gate-off voltage to the pull-up node when the carry signal from the subsequent stage (k+1) is at the gate-on voltage, ensuring that the kth stage is deactivated in response to the next stage's activation. The third controller maintains the pull-up node at the first gate-off voltage when the pull-down node is at the gate-on voltage, preventing unintended activation of the kth stage. This design ensures proper timing and stability of scan signals across multiple stages, reducing signal interference and improving display performance.
29. The scan signal driver of claim 28 , wherein the third pull-up node controller comprises: a (10-1) th transistor configured to be turned on by the gate-on voltage of the pull-down node to connect the pull-up node with the carry output terminal; and a (10-2) th transistor configured to be turned on by the gate-on voltage of the pull-down node to connect the (10-1) th transistor with the carry output terminal.
This invention relates to a scan signal driver circuit for display panels, specifically addressing the need for efficient signal transmission and stable operation in gate driver circuits. The circuit includes a third pull-up node controller that enhances the reliability of carry signal propagation. The controller comprises two transistors: a first transistor (10-1) that connects the pull-up node to the carry output terminal when activated by a gate-on voltage from the pull-down node, and a second transistor (10-2) that connects the first transistor to the carry output terminal under the same activation condition. This dual-transistor configuration ensures robust signal transfer, reducing signal distortion and improving synchronization in the gate driver. The pull-up node controls the output of scan signals, while the pull-down node stabilizes the circuit by resetting the pull-up node when necessary. The carry output terminal propagates timing signals to subsequent stages, ensuring sequential activation of scan lines. The invention optimizes signal integrity and operational stability in display driver circuits, particularly in large-area or high-resolution panels where precise timing is critical. The use of the pull-down node's gate-on voltage to control both transistors ensures synchronized and reliable signal transmission, minimizing errors in scan signal generation.
30. The scan signal driver of claim 28 , wherein the third pull-up node controller comprises: a (10-1) th transistor configured to be turned on by the gate-on voltage of the scan clock signal or the gate-on voltage of the sensing clock signal to connect the pull-up node with the carry output terminal; a (10-2) th transistor configured to be turned on by the gate-on voltage of the pull-down node to connect the (10-1) th transistor with the carry output terminal; and a (10-3) th transistor configured to be turned on by the gate-on voltage of the another scan clock signal or the gate-on voltage of the sensing clock signal to connect the pull-up node with the (10-2) th transistor.
The invention relates to a scan signal driver circuit for display panels, particularly addressing the need for efficient signal transmission and control in gate driver circuits. The circuit includes a third pull-up node controller that regulates the connection between a pull-up node and a carry output terminal using multiple transistors. A first transistor connects the pull-up node to the carry output terminal when activated by either a scan clock signal or a sensing clock signal. A second transistor, controlled by the gate-on voltage of a pull-down node, connects the first transistor to the carry output terminal. A third transistor, activated by another scan clock signal or the sensing clock signal, connects the pull-up node to the second transistor. This configuration ensures precise timing and signal integrity during display panel operation, improving reliability and performance. The controller enhances the gate driver's ability to handle both display and sensing functions, optimizing signal propagation and reducing power consumption. The transistors are configured to work in tandem, ensuring proper signal routing and minimizing signal distortion. This design is particularly useful in advanced display technologies requiring high-speed and accurate signal control.
31. The scan signal driver of claim 28 , wherein the third pull-up node controller comprises: a (10−1) th transistor configured to be turned on by the gate-on voltage of the pull-down node to connect the pull-up node with a first gate-off terminal to which the first gate-off voltage is applied; and a (10-2) th transistor configured to be turned on by the gate-on voltage of the pull-down node to connect the (10-1) th transistor with the first gate-off terminal.
This invention relates to a scan signal driver circuit for display panels, specifically addressing the need for stable and reliable gate signal control in display driver integrated circuits (DDIs). The circuit includes a pull-up node controller that regulates the voltage at a pull-up node to control the output of scan signals. The third pull-up node controller, a key component, comprises two transistors: a (10-1)th transistor and a (10-2)th transistor. The (10-1)th transistor is configured to connect the pull-up node to a first gate-off terminal, which supplies a first gate-off voltage, when activated by a gate-on voltage from a pull-down node. The (10-2)th transistor is similarly activated by the gate-on voltage of the pull-down node and connects the (10-1)th transistor to the first gate-off terminal. This dual-transistor configuration ensures precise control of the pull-up node voltage, preventing signal distortion and improving the stability of scan signal output. The design enhances the reliability of gate signal generation in display driver circuits, particularly in applications requiring high-resolution or high-frequency operation. The transistors are selectively turned on by the pull-down node's gate-on voltage, ensuring synchronized and accurate voltage regulation at the pull-up node. This configuration minimizes leakage currents and reduces power consumption while maintaining signal integrity.
32. A scan signal driver, comprising: a plurality of stages for outputting scan signals and sensing signals, wherein a first stage among the stages is connected to a first scan signal line and a first sensing signal line, and wherein the first stage comprises: a first output unit configured to output a scan clock signal input to a first scan clock terminal to the first scan signal line as a first scan signal and to output a sensing clock signal input to a first sensing clock terminal to the first sensing signal line as a first sensing signal when a pull-up node has a gate-on voltage; and a sensing controller configured to apply the gate-on voltage to the pull-up node during a vertical blank period of a frame period when a sensing control signal of the gate-on voltage is input to a sensing control terminal during an active period of the frame period.
This invention relates to a scan signal driver for display panels, particularly addressing the need for integrated scan and sensing signal generation in display systems. The driver includes multiple stages, each outputting both scan and sensing signals to respective signal lines. A first stage is connected to a first scan signal line and a first sensing signal line. The stage features an output unit that transmits a scan clock signal to the scan signal line and a sensing clock signal to the sensing signal line when a pull-up node is at a gate-on voltage. A sensing controller applies the gate-on voltage to the pull-up node during a vertical blank period of a frame, triggered by a sensing control signal received during the frame's active period. This design enables simultaneous or sequential scan and sensing operations, improving display panel functionality by integrating signal generation for both display driving and touch or defect detection. The stages are cascaded, with each stage's output influencing subsequent stages, ensuring synchronized signal propagation. The invention optimizes display performance by leveraging existing scan driver circuitry for additional sensing capabilities, reducing hardware complexity and power consumption.
33. A display device, comprising: a display panel comprising data lines, scan signal lines and sensing signal lines, and pixels connected to the data lines, the scan signal lines and the sensing signal lines; a data driver for applying data voltages to the data lines; and a scan signal driver comprising a plurality of stages for applying scan signals to the scan signal lines and applying sensing signals to the sensing signal lines, wherein a first stage among the stages is connected to a first scan signal line and a first sensing signal line, and wherein the first stage comprises: a first output unit configured to output a scan clock signal input to a first scan clock terminal to the first scan signal line as a first scan signal and to output a sensing clock signal input to a first sensing clock terminal to the first sensing signal line as a first sensing signal when a pull-up node has a gate-on voltage; and a second output unit configured to output a carry clock signal input to a first carry clock terminal as a first carry signal to a carry output terminal when the pull-up node has the gate-on voltage, wherein the first stage is connected to a second scan-signal line and a second sensing signal line, and wherein the first output unit is configured to output another scan clock signal input to a second scan clock terminal to the second scan signal line as a second scan signal, and to output another sensing clock signal input to a second sensing clock terminal to the second sensing signal line as a second sensing signal when the pull-up node has the gate-on voltage.
This invention relates to a display device with integrated scan and sensing signal drivers, addressing the need for efficient signal distribution in display panels. The device includes a display panel with data lines, scan signal lines, sensing signal lines, and pixels connected to these lines. A data driver applies data voltages to the data lines, while a scan signal driver, composed of multiple stages, applies scan and sensing signals to the respective lines. A first stage in the scan signal driver is connected to a first scan signal line and a first sensing signal line. This stage includes a first output unit that, when a pull-up node has a gate-on voltage, outputs a scan clock signal from a first scan clock terminal to the first scan signal line as a first scan signal and a sensing clock signal from a first sensing clock terminal to the first sensing signal line as a first sensing signal. The stage also includes a second output unit that outputs a carry clock signal from a first carry clock terminal as a first carry signal to a carry output terminal when the pull-up node has the gate-on voltage. Additionally, the first stage is connected to a second scan signal line and a second sensing signal line, where the first output unit outputs another scan clock signal from a second scan clock terminal to the second scan signal line as a second scan signal and another sensing clock signal from a second sensing clock terminal to the second sensing signal line as a second sensing signal when the pull-up node has the gate-on voltage. This design allows for simultaneous control of multiple scan and sensing signals, improving display panel efficiency and reducing circuit complexity.
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June 15, 2020
February 1, 2022
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