A charge release circuit, a display substrate, a display device and a charge release method thereof are provided. The charge release circuit including: a controller, a charge release sub-circuit and a first conductor, wherein the charge release sub-circuit is respectively connected with the controller, the first conductor and a second conductor in an active area of an array substrate, and the charge release sub-circuit is configured to conduct the first conductor and the second conductor under a control of the controller, so as to allow charges on the second conductor to move to the first conductor. The charge release circuit can solve the problem that the display panel in the black-screen state displays bright spots so as to reduce the number of bright spots on the display panel in the black-screen state.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A charge release circuit, comprising: a controller, a charge release sub-circuit and a first conductor, wherein the charge release sub-circuit is connected with the controller, the first conductor and a second conductor, respectively, the second conductor is located in an active area of an array substrate, and the charge release sub-circuit is configured to be switched on to electrically connect the first conductor and the second conductor under a control of the controller, so as to allow charges on the second conductor to move to the first conductor, wherein the second conductor comprises at least one data line, the controller comprises a second control line, and the charge release sub-circuit comprises a second charge release unit, wherein the second charge release unit is connected with the at least one data line, the second control line and the first conductor, respectively, and the second charge release unit is configured to electrically connect the first conductor and the at least one data line according to a control signal on the second control line, wherein the second conductor further comprises a gate line and at least one pixel electrode, the controller further comprises a third control line, and the charge release sub-circuit further comprises a third charge release unit, wherein the third charge release unit is connected with the gate line and the third control line in the array substrate, respectively, and the third charge release unit is configured to write a control signal on the third control line into the gate line so as to electrically connect each pixel electrode and the data line connected with the pixel electrode, and wherein the second control line is insulated from the third control line.
This invention relates to a charge release circuit designed for array substrates, particularly in display technologies like LCDs or OLEDs, where residual charges on data lines, gate lines, and pixel electrodes can cause display defects. The circuit includes a controller, a charge release sub-circuit, and a first conductor. The charge release sub-circuit connects the first conductor to a second conductor, which includes at least one data line, a gate line, and pixel electrodes within the active area of the array substrate. The sub-circuit selectively connects these components to release accumulated charges. The controller generates control signals via separate control lines to manage charge release. A second control line activates a second charge release unit, which connects the first conductor to the data line, allowing charges to transfer. A third control line activates a third charge release unit, which writes a control signal into the gate line, enabling pixel electrodes to connect with their corresponding data lines. This ensures comprehensive charge dissipation. The second and third control lines are insulated to prevent interference. The system prevents display artifacts by systematically discharging residual charges, improving display uniformity and reliability.
2. The charge release circuit according to claim 1 , wherein the second conductor comprises at least one gate line, the controller comprises a first control line, and the charge release sub-circuit comprises a first charge release unit, and wherein the first charge release unit is connected with the at least one gate line, the first control line and the first conductor, respectively, and the first charge release unit is configured to be switched on to electrically connect the first conductor and the at least one gate line according to a control signal on the first control line.
This invention relates to a charge release circuit for electronic devices, particularly for managing charge distribution in display panels or similar systems. The problem addressed is the need to efficiently release accumulated charge from conductive elements, such as gate lines in display panels, to prevent voltage fluctuations or signal interference that could degrade performance. The charge release circuit includes a first conductor and a second conductor, where the second conductor comprises at least one gate line. A controller with a first control line generates control signals to manage charge release. A charge release sub-circuit, specifically a first charge release unit, connects the first conductor, the at least one gate line, and the first control line. The first charge release unit is configured to switch on in response to a control signal, electrically connecting the first conductor and the gate line to release accumulated charge. This ensures stable operation by preventing charge buildup that could disrupt signal integrity or cause voltage instability in the system. The circuit is designed to be integrated into display panels or other electronic systems requiring precise charge management.
3. The charge release circuit according to claim 2 , wherein the second conductor comprises a plurality of gate lines, the first charge release unit comprises a plurality of first transistors, the first control line is perpendicular to the gate line, and the plurality of first transistors are in a one-to-one correspondence with the plurality of gate lines; wherein a gate electrode of each of the plurality of first transistors is connected with the first control line, a first electrode of each of the plurality of first transistors is connected with one gate line in the plurality of gate lines, and a second electrode of each of the plurality of first transistors is connected with the first conductor.
This invention relates to a charge release circuit used in electronic devices, particularly for managing charge accumulation in gate lines of display panels or similar systems. The problem addressed is uncontrolled charge buildup in gate lines, which can lead to display artifacts, signal interference, or device malfunction. The circuit provides a controlled mechanism to release excess charge from gate lines to a first conductor, preventing such issues. The charge release circuit includes a second conductor comprising multiple gate lines, a first charge release unit with multiple first transistors, and a first control line perpendicular to the gate lines. Each first transistor corresponds to one gate line. The gate electrode of each transistor connects to the first control line, the first electrode connects to a respective gate line, and the second electrode connects to the first conductor. When activated, the transistors discharge charge from the gate lines to the first conductor, ensuring stable operation. The circuit may also include a second charge release unit with second transistors for additional charge management, where the second transistors are controlled by a second control line and connected to a second conductor. This dual-unit design allows for flexible charge release strategies, such as sequential or selective discharge based on operational needs. The invention improves reliability and performance in systems requiring precise charge control in gate lines.
4. The charge release circuit according to claim 1 , wherein the second conductor comprises a plurality of data lines, the second charge release unit comprises a plurality of second transistors, the second control line is perpendicular to the data line, and the plurality of second transistors are in a one-to-one correspondence with the plurality of data lines; and wherein a gate electrode of each of the plurality of second transistors is connected with the second control line, a first electrode of each of the plurality of second transistors is connected with one data line in the plurality of data lines, and a second electrode of each of the plurality of second transistors is connected with the first conductor.
The invention relates to a charge release circuit used in electronic devices, particularly for managing charge distribution in display panels or sensor arrays. The problem addressed is the need for efficient charge release to prevent signal interference or data corruption during operation. The circuit includes a first conductor and a second conductor, where the second conductor comprises multiple data lines. A second charge release unit is connected to these data lines, consisting of multiple transistors that are individually connected to each data line. Each transistor has a gate electrode linked to a second control line, which is oriented perpendicular to the data lines. The first electrode of each transistor connects to a respective data line, while the second electrode connects to the first conductor. This configuration allows selective charge release from the data lines to the first conductor, controlled by the second control line. The circuit ensures proper charge management, reducing noise and improving signal integrity in applications like display panels or sensor arrays. The transistors operate in a one-to-one correspondence with the data lines, enabling precise control over charge release for each line.
5. The charge release circuit according to claim 1 , wherein the second conductor comprises a plurality of data lines, the second charge release unit comprises a plurality of second transistors, the second control line is perpendicular to the data line, and the plurality of second transistors are in a one-to-one correspondence with the plurality of data lines; and wherein a gate electrode of each of the plurality of second transistors is connected with the second control line, a first electrode of each of the plurality of second transistors is connected with one data line in the plurality of data lines, and a second electrode of each of the plurality of second transistors is connected with the first conductor.
This invention relates to a charge release circuit used in electronic devices, particularly for managing charge accumulation in data lines. The problem addressed is the need to efficiently release excess charge from data lines to prevent interference or damage in integrated circuits. The circuit includes a first conductor and a second conductor, where the second conductor comprises multiple data lines. A second charge release unit is connected to these data lines, consisting of multiple transistors that correspond one-to-one with each data line. Each transistor has a gate electrode connected to a second control line, which is perpendicular to the data lines. The first electrode of each transistor connects to a respective data line, while the second electrode connects to the first conductor. This configuration allows selective charge release from individual data lines when activated by the control line, ensuring proper charge management and preventing data corruption or circuit malfunctions. The transistors act as switches, enabling controlled discharge of accumulated charge from the data lines to the first conductor, which may be a ground or another reference line. This design improves reliability and performance in integrated circuits by mitigating charge-related issues.
6. A display device, comprising the charge release circuit according to claim 1 .
A display device includes a charge release circuit designed to manage electrical charge within the device. The charge release circuit is configured to release accumulated charge from a display panel, such as an organic light-emitting diode (OLED) panel, to prevent damage or performance degradation. The circuit operates by detecting charge buildup and selectively discharging it to ground or another safe path, ensuring stable operation and longevity of the display components. This is particularly important in OLED displays, where uncontrolled charge accumulation can lead to pixel degradation or uneven brightness. The charge release circuit may include a switching element, such as a transistor, controlled by a timing signal to release charge at specific intervals or in response to detected conditions. The display device may further incorporate additional circuits, such as a driving circuit for controlling pixel activation and a power supply circuit for providing stable voltage levels. The charge release circuit integrates seamlessly with these components to maintain optimal display performance while minimizing power consumption and heat generation. This solution addresses the problem of charge-related damage in display panels, enhancing reliability and extending the lifespan of electronic devices incorporating such displays.
7. A charge release method of the display device according to claim 6 , comprising: applying a control signal to the controller when the display panel is in a black-screen state, switching on the charge release sub-circuit to electrically connect the first conductor and the second conductor under the control of the controller, and allowing charges on the second conductor to move to the first conductor.
This invention relates to a charge release method for a display device, specifically addressing the issue of residual charges on display panels that can cause image retention or display artifacts when the screen is in a black-screen state. The method involves a display device with a display panel, a controller, and a charge release sub-circuit. The display panel includes a first conductor and a second conductor, where the second conductor accumulates charges during operation. The charge release sub-circuit is connected between the first and second conductors and is controlled by the controller. When the display panel is in a black-screen state, a control signal is applied to the controller, which activates the charge release sub-circuit. This electrically connects the first and second conductors, allowing accumulated charges on the second conductor to transfer to the first conductor, thereby neutralizing the residual charges and preventing display artifacts. The method ensures efficient charge dissipation without requiring additional external components, improving display performance and longevity.
8. A charge release method according to claim 7 , wherein switching on the charge release sub-circuit to electrically connect the first conductor and the second conductor under the control of the controller comprises: inputting a control signal into the second control line, and allowing charges on the data line to move to the first conductor; and inputting a control signal into the third control line, and allowing charges on the pixel electrode to move to the first conductor.
This invention relates to a charge release method for an electronic display device, specifically addressing the problem of residual charges on data lines and pixel electrodes that can cause display artifacts. The method involves a charge release sub-circuit that selectively connects a first conductor to a second conductor, such as a data line or a pixel electrode, to dissipate accumulated charges. The sub-circuit is controlled by a controller that activates specific control lines to enable charge movement. When the sub-circuit is switched on, a control signal is input into a second control line, allowing charges from the data line to transfer to the first conductor. Simultaneously or sequentially, a control signal is input into a third control line, enabling charges from the pixel electrode to also move to the first conductor. This ensures efficient charge dissipation, reducing display irregularities. The method improves display performance by preventing charge buildup that could otherwise lead to visual defects. The first conductor may serve as a common discharge path, while the second and third control lines independently regulate charge flow from the data line and pixel electrode, respectively. The controller coordinates these operations to ensure proper timing and charge release.
9. A charge release circuit, comprising: a controller, a charge release sub-circuit and a first conductor, wherein the charge release sub-circuit is connected with the controller, the first conductor and a second conductor, respectively, the second conductor is located in an active area of an array substrate, and the charge release sub-circuit is configured to be switched on to electrically connect the first conductor and the second conductor under a control of the controller, so as to allow charges on the second conductor to move to the first conductor, wherein the second conductor comprises at least one gate line, the controller comprises a first control line, and the charge release sub-circuit comprises a first charge release unit, and wherein the first charge release unit is respectively connected with the at least one gate line, the first control line and the first conductor, respectively, and the first charge release unit is configured to conduct be switched on to electrically connect the first conductor and the at least one gate line according to a control signal on the first control line, wherein the second conductor comprises at least one data line, the controller comprises a second control line, and the charge release sub-circuit comprises a second charge release unit; and wherein the second charge release unit is respectively connected with the at least one data line, the second control line and the first conductor, respectively, and the second charge release unit is configured to conduct be switched on to electrically connect the first conductor and the at least one data line according to a control signal on the second control line, wherein the second conductor comprises a plurality of data lines, the second charge release unit comprises a plurality of second transistors, the second control line is perpendicular to the data line, and the plurality of second transistors are in a one-to-one correspondence with the plurality of data lines; and wherein a gate electrode of each of the plurality of second transistors is connected with the second control line, a first electrode of each of the plurality of second transistors is connected with one data line in the plurality of data lines, and a second electrode of each of the plurality of second transistors is connected with the first conductor, wherein the second conductor further comprises at least one pixel electrode, the controller further comprises a third control line, and the charge release sub-circuit further comprises a third charge release unit, and wherein the third charge release unit is connected with the gate line and the third control line in the array substrate, respectively, and the third charge release unit is configured to write a control signal on the third control line into the gate line so as to electrically connect each pixel electrode and the data line connected with the pixel electrode.
This invention relates to a charge release circuit for an array substrate, particularly for managing residual charges in display panels. The circuit addresses the problem of charge accumulation on conductive lines (gate lines, data lines, and pixel electrodes) in an array substrate, which can cause display defects or operational issues. The charge release circuit includes a controller, a charge release sub-circuit, and a first conductor. The charge release sub-circuit connects the first conductor to a second conductor (comprising gate lines, data lines, and pixel electrodes) under the control of the controller. When activated, the circuit allows charges on the second conductor to transfer to the first conductor, preventing charge buildup. The controller uses separate control lines to independently manage charge release for gate lines, data lines, and pixel electrodes. For data lines, the sub-circuit includes multiple transistors, each corresponding to a data line, with gates connected to a second control line and electrodes connecting the data lines to the first conductor. Additionally, a third control line enables writing control signals to gate lines, ensuring proper pixel electrode and data line connections. This design ensures efficient charge dissipation and stable display performance.
10. The charge release circuit according to claim 9 , wherein the third charge release unit comprises a plurality of third transistors, the plurality of third transistors are in a one-to-one correspondence with the plurality of gate lines in the array substrate, and the second conductor comprises a plurality of pixel electrodes connected with each gate line, and the third control line is perpendicular to the gate line, and wherein both a gate electrode and a first electrode of each of the plurality of third transistors are connected with the third control line, and a second electrode of each of the plurality of third transistors is connected with one gate line in the plurality of gate lines.
This invention relates to a charge release circuit for an array substrate, particularly for managing residual charges in gate lines during display panel operation. The problem addressed is the accumulation of residual charges in gate lines, which can cause display defects such as flickering or uneven brightness. The circuit includes a third charge release unit with multiple transistors, each corresponding to a gate line in the array substrate. Each transistor has its gate and first electrode connected to a third control line, while its second electrode connects to a specific gate line. The second conductor includes pixel electrodes linked to each gate line, and the third control line is perpendicular to the gate lines. This configuration allows selective discharge of residual charges from the gate lines when the third control line is activated, ensuring stable display performance. The circuit improves charge management by providing a direct path for residual charge dissipation, reducing display artifacts and enhancing panel reliability. The transistors are arranged to ensure precise control over charge release, with each transistor targeting a specific gate line for efficient discharge. This design is particularly useful in high-resolution displays where charge accumulation is more pronounced.
11. The charge release circuit according to claim 9 , wherein a volume of the first conductor is greater than that of the second conductor.
A charge release circuit is designed to manage electrical charge in systems where controlled discharge is necessary, such as in energy storage devices or electronic circuits. The circuit includes a first conductor and a second conductor, each connected to a charge storage element. The first conductor has a larger volume than the second conductor, which influences the circuit's discharge characteristics. The larger volume of the first conductor allows it to handle higher currents or store more charge, while the second conductor, being smaller, may facilitate faster discharge or finer control over the release of charge. The circuit may also include a switching element to selectively connect or disconnect the conductors from the charge storage element, enabling dynamic adjustment of the discharge process. This design ensures efficient charge management, preventing overcharging or uncontrolled discharge, which is critical in applications requiring precise energy regulation. The volume difference between the conductors optimizes the circuit's performance by balancing charge capacity and discharge speed.
12. The charge release circuit according to claim 9 , wherein the first conductor is a common electrode line or a storage electrode line.
A charge release circuit is used in semiconductor devices, particularly in memory cells, to manage charge accumulation and dissipation. The circuit addresses the problem of unintended charge buildup in conductive lines, which can lead to performance degradation, data corruption, or device failure. The circuit includes a first conductor, a second conductor, and a switching element that selectively connects the first conductor to the second conductor to release accumulated charge. The first conductor can be a common electrode line or a storage electrode line, which are critical components in memory cells for storing and transferring charge. The second conductor may be a ground line or another conductive path that provides a discharge route. The switching element, such as a transistor or diode, is controlled by a control signal to enable or disable the charge release path. When activated, the switching element allows charge to flow from the first conductor to the second conductor, preventing excessive charge buildup. This design ensures stable operation of the memory cell by maintaining proper charge levels and avoiding electrical stress on the components. The circuit is particularly useful in dynamic random-access memory (DRAM) and other semiconductor devices where charge management is essential for reliability and performance.
13. A display substrate, comprising the charge release circuit according to claim 9 .
A display substrate includes a charge release circuit designed to mitigate static electricity buildup during manufacturing or operation. The charge release circuit comprises a conductive layer, a charge release electrode, and a charge release line. The conductive layer is formed on the substrate and includes a conductive material such as indium tin oxide (ITO) or metal. The charge release electrode is electrically connected to the conductive layer and is configured to release accumulated static charges. The charge release line is electrically connected to the charge release electrode and provides a conductive path to ground or another discharge point, preventing damage to the display substrate or its components. The circuit ensures efficient charge dissipation, improving manufacturing yield and device reliability. The conductive layer may be part of a thin-film transistor (TFT) structure or other display elements, and the charge release electrode is positioned to minimize interference with display functionality. The charge release line is designed to avoid visual artifacts while maintaining effective charge conduction. This technology addresses static electricity issues in display manufacturing, particularly for large-area substrates or flexible displays where charge accumulation is more pronounced.
14. A display device, comprising a display panel, wherein the display panel comprises the display substrate according to claim 13 .
A display device includes a display panel with a display substrate designed to reduce light leakage and improve display quality. The display substrate features a base substrate, a thin-film transistor (TFT) layer, and a color filter layer. The TFT layer includes a gate electrode, a source electrode, and a drain electrode, with an insulating layer separating the gate electrode from the source and drain electrodes. The color filter layer is positioned above the TFT layer and includes a black matrix and color filters. The black matrix is aligned with the TFT layer to block light from passing through the TFT components, preventing light leakage and enhancing contrast. The color filters are arranged to correspond with pixel regions, allowing precise color display. The display substrate may also include a planarization layer between the TFT and color filter layers to ensure a smooth surface for subsequent layers. This structure improves display uniformity and reduces defects caused by misalignment or light interference. The display device incorporating this substrate is suitable for high-resolution applications, such as smartphones, tablets, and televisions, where image clarity and contrast are critical.
15. A charge release method of the display device according to claim 14 , comprising: applying a control signal to the controller when the display panel is in a black-screen state, switching on the charge release sub-circuit to electrically connect the first conductor and the second conductor under the control of the controller, and allowing charges on the second conductor to move to the first conductor.
This invention relates to a charge release method for a display device, specifically addressing the issue of residual charges on display panels that can cause display abnormalities or damage. The method is designed for use with a display device that includes a display panel, a controller, and a charge release sub-circuit. The display panel has a first conductor and a second conductor, where the second conductor accumulates charges during operation. The charge release sub-circuit is connected to the first and second conductors and can be switched on or off by the controller. The method involves applying a control signal to the controller when the display panel is in a black-screen state, which activates the charge release sub-circuit. This electrically connects the first and second conductors, allowing accumulated charges on the second conductor to transfer to the first conductor, thereby neutralizing the residual charges and preventing display defects. The controller manages the switching of the charge release sub-circuit to ensure proper charge dissipation. This method is particularly useful in display technologies where charge buildup can degrade performance or cause visual artifacts.
16. The method according to claim 15 , wherein the first conductor is a common electrode line or a storage electrode line, and the second conductor is at least one of a gate line, a data line or a pixel electrode.
This invention relates to display panel technologies, specifically addressing signal interference issues in display devices. The method involves reducing interference between conductors in a display panel by adjusting the timing of signal transmission. The first conductor, which can be a common electrode line or a storage electrode line, and the second conductor, which can be a gate line, a data line, or a pixel electrode, are configured to transmit signals with controlled timing to minimize crosstalk. The method ensures that signals on the first conductor are transmitted during a period when the second conductor is inactive, preventing interference. This approach improves display performance by reducing signal distortion and enhancing image quality. The timing adjustment is based on the operational phases of the display panel, ensuring compatibility with existing display driving schemes. The invention is particularly useful in high-resolution displays where signal integrity is critical. By optimizing signal transmission timing, the method effectively mitigates interference without requiring significant hardware modifications, making it a cost-effective solution for enhancing display reliability.
17. The method according to claim 15 , wherein a volume of the first conductor is greater than that of the second conductor.
A method for optimizing electrical conductivity in a multi-conductor system addresses the problem of uneven current distribution and thermal management in electronic devices. The method involves using two conductors with different volumes to improve performance. The first conductor, having a larger volume than the second conductor, is designed to carry a higher current load while minimizing resistive losses. This volume difference ensures that the first conductor can dissipate heat more efficiently, reducing the risk of overheating. The second conductor, with a smaller volume, is optimized for applications requiring lower current flow or where space constraints are critical. By strategically selecting the volume ratio between the two conductors, the method enhances overall system efficiency, reliability, and thermal stability. This approach is particularly useful in high-power electronics, automotive systems, and renewable energy applications where thermal management and current distribution are critical. The method ensures balanced electrical performance while maintaining compact design requirements.
18. The charge release circuit according to claim 9 , wherein a line width of the first conductor is greater than that of the second conductor.
A charge release circuit is designed to manage electrical charge in semiconductor devices, particularly for applications requiring precise charge control, such as memory cells or sensors. The circuit includes a first conductor and a second conductor, each connected to a charge storage node. The first conductor is configured to release charge from the storage node, while the second conductor is used to control or monitor the charge. To optimize performance, the line width of the first conductor is made greater than that of the second conductor. This design ensures efficient charge release while maintaining precise control over the charge storage node. The wider first conductor reduces resistance and improves charge transfer efficiency, while the narrower second conductor allows for finer control or sensing of the charge state. This configuration is particularly useful in integrated circuits where both rapid charge release and accurate charge management are required. The circuit may be part of a larger system, such as a memory array or a sensor interface, where charge handling is critical for proper operation. The design balances speed and precision, making it suitable for high-performance electronic applications.
19. A charge release circuit, comprising: a controller, a charge release sub-circuit and a first conductor, wherein the charge release sub-circuit is connected with the controller, the first conductor and a second conductor, respectively, the second conductor is located in an active area of an array substrate, and the charge release sub-circuit is configured to be switched on to electrically connect the first conductor and the second conductor under a control of the controller, so as to allow charges on the second conductor to move to the first conductor, wherein the second conductor comprises at least one gate line, the controller comprises a first control line, and the charge release sub-circuit comprises a first charge release unit, and wherein the first charge release unit is respectively connected with the at least one gate line, the first control line and the first conductor, respectively, and the first charge release unit is configured to be switched on to electrically connect the first conductor and the at least one gate line according to a control signal on the first control line, wherein the second conductor comprises a plurality of gate lines, the first charge release unit comprises a plurality of first transistors, the first control line is perpendicular to the gate line, and the plurality of first transistors are in a one-to-one correspondence with the plurality of gate lines; wherein a gate electrode of each of the plurality of first transistors is connected with the first control line, a first electrode of each of the plurality of first transistors is connected with one gate line in the plurality of gate lines, and a second electrode of each of the plurality of first transistors is connected with the first conductor, wherein the second conductor comprises at least one data line, the controller comprises a second control line, and the charge release sub-circuit comprises a second charge release unit; and wherein the second charge release unit is respectively connected with the at least one data line, the second control line and the first conductor, respectively, and the second charge release unit is configured to be switched on to electrically connect the first conductor and the at least one data line according to a control signal on the second control line, wherein the second conductor comprises a plurality of data lines, the second charge release unit comprises a plurality of second transistors, the second control line is perpendicular to the data line, and the plurality of second transistors are in a one-to-one correspondence with the plurality of data lines; and wherein a gate electrode of each of the plurality of second transistors is connected with the second control line, a first electrode of each of the plurality of second transistors is connected with one data line in the plurality of data lines, and a second electrode of each of the plurality of second transistors is connected with the first conductor, wherein the second conductor further comprises at least one pixel electrode, the controller further comprises a third control line, and the charge release sub-circuit further comprises a third charge release unit, and wherein the third charge release unit is connected with the gate line and the third control line in the array substrate, and the third charge release unit is configured to write a control signal on the third control line into the gate line so as to electrically connect each pixel electrode and the data line connected with the pixel electrode.
This invention relates to a charge release circuit for an array substrate, addressing the problem of residual charge accumulation on conductive lines and pixel electrodes in display panels, which can cause display defects. The circuit includes a controller, a charge release sub-circuit, and a first conductor. The charge release sub-circuit connects the first conductor to various conductive elements in the active area of the array substrate, allowing controlled discharge of residual charges. The charge release sub-circuit includes multiple units for different conductive elements. For gate lines, a first charge release unit comprises transistors, each with a gate connected to a first control line, a first electrode connected to a gate line, and a second electrode connected to the first conductor. When activated by the control line, these transistors connect the gate lines to the first conductor, discharging residual charges. Similarly, for data lines, a second charge release unit uses transistors connected to a second control line, enabling discharge of data lines to the first conductor. Additionally, a third charge release unit controls pixel electrodes by writing a signal from a third control line into the gate lines, enabling pixel electrodes to connect to their respective data lines for charge release. The control lines are perpendicular to the lines they control, ensuring precise activation. This design ensures efficient charge dissipation, improving display performance and reliability.
20. The charge release circuit according to claim 19 , wherein the third charge release unit comprises a plurality of third transistors, the plurality of third transistors are in a one-to-one correspondence with the plurality of gate lines in the array substrate, and the second conductor comprises a plurality of pixel electrodes connected with each gate line, and the third control line is perpendicular to the gate line, and wherein both a gate electrode and a first electrode of each of the plurality of third transistors are connected with the third control line, and a second electrode of each of the plurality of third transistors is connected with one gate line in the plurality of gate lines.
This invention relates to a charge release circuit for an array substrate, addressing the problem of residual charge accumulation in gate lines during display panel operation, which can cause display defects. The circuit includes a third charge release unit designed to selectively discharge residual charges from gate lines to prevent such issues. The third charge release unit comprises multiple third transistors, each corresponding to a specific gate line in the array substrate. Each transistor's gate and first electrode are connected to a third control line, which is perpendicular to the gate lines, while the second electrode of each transistor is connected to one of the gate lines. The second conductor in the circuit includes multiple pixel electrodes, each connected to a gate line. The third control line activates the transistors to release residual charges from the gate lines, ensuring stable display performance. This design allows for precise control over charge release, improving display quality by mitigating charge-related artifacts. The circuit's structure ensures efficient charge dissipation while maintaining compatibility with existing display panel architectures.
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November 8, 2017
February 1, 2022
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