A method of operating a semiconductor device includes applying a first voltage to a first source select line coupled to first source select transistors of memory strings included in an unselected memory block, among memory blocks, floating the first source select line after the first voltage is applied thereto, applying a second voltage having a lower voltage level than the first voltage to a second source select line coupled to second source select transistors of the memory strings included in the unselected memory block, applying a precharge voltage to a common source line, and applying a program voltage to a word line coupled to selected memory cells of memory strings included in a selected memory block, among the memory blocks.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of operating a semiconductor device including memory blocks sharing a common source line, each of the memory blocks including memory strings each including a first source select line, a second source select line and memory cells, the method comprising: applying a first voltage to a first source select line coupled to first source select transistors of memory strings included in an unselected memory block, among the memory blocks; floating the first source select line after the first voltage is applied thereto; applying a second voltage having a lower voltage level than the first voltage to a second source select line coupled to second source select transistors of the memory strings included in the unselected memory block; applying a precharge voltage to the common source line; and applying a program voltage to a word line coupled to selected memory cells of memory strings included in a selected memory block, among the memory blocks.
2. The method of claim 1 , wherein the memory strings are coupled between the common source line and bit lines, and the first source select transistors are closer to the common source line than the second source select transistors.
3. The method of claim 1 , wherein the second source select transistors are turned off when the second voltage is applied.
4. The method of claim 1 , wherein the second voltage has a lower voltage level than threshold voltages of the second source select transistors.
5. The method of claim 1 , wherein the first voltage is a positive voltage and the second voltage is a ground voltage.
6. The method of claim 1 , wherein the first voltage is a first positive voltage and the second voltage is a second positive voltage.
7. The method of claim 1 , wherein a voltage level of the first voltage is equal to or lower than a voltage level of the precharge voltage.
8. The method of claim 1 , wherein a level of the common source line is increased to a precharge level when the first voltage is applied to the first source select line and the second voltage is applied to the second source select line.
9. The method of claim 1 , wherein the first voltage or the second voltage is applied when the precharge voltage is applied.
10. The method of claim 1 , wherein a level of the common source line is increased to a precharge level using capacitance between the first source select line and the common source line.
11. The method of claim 1 , wherein the second voltage is applied to the second source select line when the first voltage is applied to the first source select line.
12. The method of claim 1 , wherein the second voltage is applied to the second source select line when the first source select line is floated.
13. The method of claim 1 , wherein each of the memory strings further includes a third source select transistor coupled between the first source select transistors and the second source select transistors.
14. The method of claim 13 , further comprising floating a third source select line coupled to the third source select transistor.
15. The method of claim 13 , further comprising floating a third source select line coupled to the third source select transistor when the first voltage is applied to the first source select line and the second voltage is applied to the second source select line.
16. The method of claim 13 , further comprising floating a third source select line coupled to the third source select transistor when the first source select line is floated and the second voltage is applied to the second source select line.
17. The method of claim 1 , wherein a channel region of the memory strings included in the selected memory block is precharged using the precharge voltage.
18. A method of operating a semiconductor device including memory blocks sharing a common source line, each of the memory blocks including memory strings coupled between the common source line and bit lines, each of the memory strings including a first group of source select transistors, a second group of source select transistors, and memory cells, wherein the first group is coupled between the common source line and the second group, the method comprising: applying a positive voltage to a first source select line coupled to a first group of memory strings included in an unselected memory block, among the memory blocks; floating the first source select line after the positive voltage is applied thereto; applying a voltage for turning off the second group to a second source select line coupled to a second group of memory cell strings included in the unselected memory block; applying a precharge voltage to the common source line; and applying a program voltage to a word line coupled to selected memory cells of memory strings included in a selected memory block, among the memory blocks.
19. A semiconductor device, comprising: a common source line; a first memory block including first memory strings coupled between the common source and first bit lines, each of the first memory strings including a first source select transistor, a second source select transistor and memory cells, wherein the first source select transistor is located closer to the common source line than the second source select transistor; a second memory block including second memory strings coupled between the common source and second bit lines, each of the second memory strings including a third source select transistor, a fourth source select transistor and memory cells, wherein the third source select transistor is located closer to the common source line than the fourth source select transistor; a peripheral circuit configured to perform a program operation on the first and second memory strings; and a control logic circuit controlling the peripheral circuit to apply a first voltage to a first source select line coupled to first source select transistors of the first memory strings when the second memory block is selected, float the first source select line after the first voltage is applied thereto, apply a second voltage having a lower voltage level than the first voltage to a second source select line coupled to second source select transistors of the first memory strings, apply a precharge voltage to the common source line, and apply a program voltage to a word line coupled to selected memory cells of the second memory strings.
20. The semiconductor device of claim 19 , wherein the first voltage is a positive voltage, the second voltage has a lower voltage level than threshold voltages of the second source select transistors, and the first source select line is located between the common source line and the second source select line.
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October 14, 2020
February 1, 2022
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