A method of operating a semiconductor device includes applying a first voltage to a first source select line coupled to first source select transistors of memory strings included in an unselected memory block, among memory blocks, floating the first source select line after the first voltage is applied thereto, applying a second voltage having a lower voltage level than the first voltage to a second source select line coupled to second source select transistors of the memory strings included in the unselected memory block, applying a precharge voltage to a common source line, and applying a program voltage to a word line coupled to selected memory cells of memory strings included in a selected memory block, among the memory blocks.
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1. A method of operating a semiconductor device including memory blocks sharing a common source line, each of the memory blocks including memory strings each including a first source select line, a second source select line and memory cells, the method comprising: applying a first voltage to a first source select line coupled to first source select transistors of memory strings included in an unselected memory block, among the memory blocks; floating the first source select line after the first voltage is applied thereto; applying a second voltage having a lower voltage level than the first voltage to a second source select line coupled to second source select transistors of the memory strings included in the unselected memory block; applying a precharge voltage to the common source line; and applying a program voltage to a word line coupled to selected memory cells of memory strings included in a selected memory block, among the memory blocks.
This invention relates to semiconductor memory devices, specifically non-volatile memory such as NAND flash, where multiple memory blocks share a common source line. The problem addressed is minimizing interference and improving reliability during programming operations in such shared-source-line architectures. The method involves selectively controlling voltages applied to source select lines in unselected memory blocks to prevent unintended program disturbances. The technique applies a first voltage to a first source select line connected to first source select transistors in unselected blocks, then floats this line. A second, lower voltage is applied to a second source select line connected to second source select transistors in the same unselected blocks. Meanwhile, a precharge voltage is applied to the common source line shared by all blocks. In the selected block, a program voltage is applied to the word line connected to the target memory cells. This voltage scheme ensures that unselected blocks remain isolated while minimizing parasitic effects, thereby improving programming accuracy and device longevity. The method is particularly useful in high-density memory designs where multiple blocks share infrastructure to conserve space.
2. The method of claim 1 , wherein the memory strings are coupled between the common source line and bit lines, and the first source select transistors are closer to the common source line than the second source select transistors.
This invention relates to memory devices, specifically non-volatile memory arrays such as NAND flash memory. The problem addressed is optimizing the layout and performance of memory strings in such arrays. Memory strings in NAND flash are typically connected between bit lines and a common source line, with select transistors controlling access to the strings. The invention improves this structure by positioning the first source select transistors closer to the common source line than the second source select transistors. This arrangement enhances electrical characteristics, such as reducing resistance and improving data retention, by optimizing the placement of select transistors relative to the source line. The memory strings are formed between the bit lines and the common source line, with the first select transistors acting as source-side select gates and the second select transistors acting as drain-side select gates. The invention ensures efficient charge transfer and minimizes interference between adjacent strings, leading to more reliable memory operations. The layout also facilitates better manufacturing scalability and integration density. The overall design improves the performance, endurance, and reliability of the memory device.
3. The method of claim 1 , wherein the second source select transistors are turned off when the second voltage is applied.
A method for controlling source select transistors in a memory device addresses the challenge of efficiently managing data retention and read operations in non-volatile memory, particularly in flash memory systems. The method involves selectively turning off second source select transistors when a second voltage is applied to a memory cell array. This ensures proper isolation of unselected memory blocks during read or program operations, preventing unintended current leakage and improving data integrity. The second source select transistors are connected to a source line and are controlled to block current flow when the second voltage is applied, typically during a read or program operation. This selective deactivation helps maintain accurate voltage levels across the memory array, reducing interference and enhancing reliability. The method is part of a broader technique for managing source select transistors, which also includes controlling first source select transistors to enable or disable current paths to the memory cells. By coordinating the activation and deactivation of these transistors, the method ensures efficient and reliable memory operations while minimizing power consumption and improving performance. The technique is particularly useful in multi-level cell (MLC) or three-dimensional (3D) NAND flash memory architectures, where precise control of transistor states is critical for maintaining data accuracy.
4. The method of claim 1 , wherein the second voltage has a lower voltage level than threshold voltages of the second source select transistors.
A method for operating a memory device addresses the challenge of efficiently managing data storage and retrieval in non-volatile memory systems, particularly in architectures involving multiple transistors. The method involves applying a first voltage to a first set of transistors, such as word lines or control gates, to enable data access or programming operations. A second voltage, lower than the threshold voltages of a second set of transistors (e.g., source select transistors), is applied to these transistors to prevent unintended current flow or leakage during the operation. This selective voltage application ensures that only the intended transistors are activated, improving data integrity and reducing power consumption. The method may also include applying a third voltage to a third set of transistors, such as drain select transistors, to further control data flow within the memory array. By carefully managing these voltage levels, the method enhances the reliability and efficiency of memory operations, particularly in high-density storage systems where minimizing leakage and ensuring precise transistor control are critical. The technique is applicable to various memory technologies, including NAND flash and other non-volatile memory architectures.
5. The method of claim 1 , wherein the first voltage is a positive voltage and the second voltage is a ground voltage.
This invention relates to a method for operating an electronic device, specifically addressing the need for efficient voltage management in circuits to reduce power consumption and improve performance. The method involves applying a first voltage to a first terminal of a circuit element and a second voltage to a second terminal of the circuit element. The first voltage is a positive voltage, while the second voltage is a ground voltage. This configuration ensures proper biasing of the circuit element, enabling optimal operation while minimizing power dissipation. The method may be applied to various electronic components, such as transistors, diodes, or other semiconductor devices, where precise voltage control is essential. By using a positive voltage and ground voltage, the method ensures stable and efficient circuit operation, particularly in low-power applications where energy efficiency is critical. The technique can be integrated into integrated circuits, power management systems, or other electronic systems requiring precise voltage regulation. The invention improves energy efficiency, reduces heat generation, and enhances the reliability of electronic devices by maintaining proper voltage levels across circuit elements.
6. The method of claim 1 , wherein the first voltage is a first positive voltage and the second voltage is a second positive voltage.
This invention relates to a method for controlling voltages in an electronic system, specifically addressing the need to manage multiple positive voltage levels to optimize performance and efficiency. The method involves applying a first positive voltage and a second positive voltage to different components or stages of the system, where the first and second voltages are distinct positive values. The method ensures proper voltage regulation and distribution, preventing voltage conflicts or inefficiencies that could arise from improper voltage levels. By using separate positive voltages, the system can achieve better power management, reduced energy consumption, and improved operational stability. The method may be applied in various electronic devices, such as processors, memory systems, or power management circuits, where precise voltage control is critical. The invention enhances system reliability and performance by ensuring that each component receives the appropriate voltage level for its intended function.
7. The method of claim 1 , wherein a voltage level of the first voltage is equal to or lower than a voltage level of the precharge voltage.
A method for managing voltage levels in an electronic system addresses the problem of ensuring proper voltage regulation during power transitions. The method involves controlling a first voltage applied to a circuit element, such as a capacitor or a memory cell, to prevent overvoltage conditions that could damage components or disrupt operations. Specifically, the method ensures that the voltage level of the first voltage does not exceed a precharge voltage level, which is a predefined safe operating voltage for the system. This control mechanism is particularly useful in applications where voltage spikes or fluctuations could occur, such as during power-up, power-down, or switching operations. By maintaining the first voltage at or below the precharge voltage, the method safeguards the integrity of the circuit and ensures reliable performance. The method may be implemented in various electronic devices, including memory systems, power management circuits, and signal processing units, where precise voltage control is critical. The approach helps mitigate risks associated with voltage-related failures while optimizing energy efficiency and operational stability.
8. The method of claim 1 , wherein a level of the common source line is increased to a precharge level when the first voltage is applied to the first source select line and the second voltage is applied to the second source select line.
This invention relates to memory devices, specifically non-volatile memory such as NAND flash, and addresses challenges in managing source lines during programming operations. The method involves controlling voltage levels on source select lines to improve data integrity and performance. A common source line is connected to multiple memory cells, and its voltage level is adjusted to a precharge level when specific voltages are applied to first and second source select lines. The first source select line is connected to a first group of memory cells, while the second source select line is connected to a second group. The precharge level is set to reduce interference between adjacent memory cells during programming, ensuring reliable data storage. The method also includes applying a programming voltage to a word line connected to the memory cells, while the source select lines isolate the memory cells from the common source line during programming. This technique helps maintain consistent voltage conditions across the memory array, preventing unintended data disturbances. The invention improves the efficiency and reliability of memory operations by optimizing source line management.
9. The method of claim 1 , wherein the first voltage or the second voltage is applied when the precharge voltage is applied.
A method for controlling a semiconductor device involves applying a first voltage or a second voltage to a first terminal of a transistor while a precharge voltage is applied to a second terminal. The transistor is part of a memory cell, such as a dynamic random-access memory (DRAM) cell, where the first and second voltages are used to adjust the threshold voltage of the transistor during read or write operations. The precharge voltage is applied to a bitline or wordline connected to the memory cell to stabilize the cell's state before data is read or written. By applying the first or second voltage simultaneously with the precharge voltage, the method improves the accuracy and speed of data operations by reducing interference and ensuring proper transistor behavior. The first and second voltages may be selected based on the operating conditions of the memory cell, such as temperature or supply voltage variations, to maintain reliable performance. This technique is particularly useful in high-density memory arrays where precise control of transistor thresholds is critical for minimizing errors and power consumption.
10. The method of claim 1 , wherein a level of the common source line is increased to a precharge level using capacitance between the first source select line and the common source line.
A method for managing voltage levels in a memory device, particularly in a non-volatile memory such as a NAND flash memory, addresses the challenge of efficiently precharging a common source line (CSL) to a desired level. The method involves increasing the voltage level of the CSL by leveraging the capacitive coupling between the first source select line (SSL) and the CSL. This approach reduces the need for additional circuitry or external voltage sources, improving power efficiency and simplifying the design. The SSL is initially charged to a higher voltage, and when its voltage is adjusted, the capacitive coupling between the SSL and CSL transfers charge to the CSL, raising its voltage to a precharge level. This technique is particularly useful in memory operations where precise voltage control is required, such as during read, program, or erase cycles. By utilizing existing capacitive coupling, the method minimizes energy consumption and reduces complexity in the memory device's peripheral circuitry. The method is applicable to various memory architectures where efficient voltage management is critical for performance and reliability.
11. The method of claim 1 , wherein the second voltage is applied to the second source select line when the first voltage is applied to the first source select line.
A method for operating a memory device involves applying voltages to source select lines to control access to memory cells. The method addresses the challenge of efficiently managing data access in memory arrays, particularly in non-volatile memory systems like flash memory, where precise voltage control is critical for reliable read, program, and erase operations. The technique involves applying a first voltage to a first source select line and simultaneously applying a second voltage to a second source select line. This coordinated application of voltages ensures proper selection and deselection of memory cells, preventing unintended data corruption or read errors. The method may be part of a broader process for managing memory operations, including selecting specific memory cells for access while isolating others. The simultaneous application of voltages to the source select lines optimizes performance by reducing latency and improving accuracy in memory operations. This approach is particularly useful in high-density memory arrays where precise control of select lines is essential for maintaining data integrity and operational efficiency. The method may be implemented in various memory architectures, including NAND flash memory, to enhance reliability and performance.
12. The method of claim 1 , wherein the second voltage is applied to the second source select line when the first source select line is floated.
A method for controlling source select lines in a memory device addresses the challenge of efficiently managing voltage application to improve device performance and reliability. The method involves applying a second voltage to a second source select line while the first source select line is in a floated state. This technique is particularly useful in non-volatile memory devices, such as flash memory, where precise control of select lines is critical for accurate data storage and retrieval. By floating the first source select line, the method prevents unintended current paths or voltage disturbances that could degrade performance. The second voltage applied to the second source select line ensures proper selection and deselection of memory cells, enhancing read and write operations. This approach optimizes power consumption and reduces the risk of data corruption, making it suitable for high-density memory architectures. The method may also include applying a first voltage to the first source select line during other operational phases to further refine control over memory cell access. The combination of floating one select line while actively driving another allows for more flexible and efficient memory operations, addressing limitations in conventional select line management techniques.
13. The method of claim 1 , wherein each of the memory strings further includes a third source select transistor coupled between the first source select transistors and the second source select transistors.
The invention relates to memory devices, specifically to the structure and operation of memory strings in non-volatile memory arrays. The problem addressed is improving the performance, reliability, and flexibility of memory strings by incorporating additional select transistors to enhance control over data access and reduce interference between memory cells. The memory strings are organized in a three-dimensional (3D) NAND flash memory architecture, where each string includes multiple memory cells stacked vertically. The memory strings are connected to bit lines and source lines, with select transistors controlling access to the memory cells. The invention introduces a third source select transistor positioned between the first and second source select transistors, which are already present in the memory string. The first source select transistor connects the memory string to the bit line, while the second source select transistor connects the string to the source line. The third source select transistor provides an additional layer of control, allowing for more precise management of current flow and voltage distribution within the string. This configuration reduces leakage current, improves data retention, and enables more efficient programming and read operations. The additional transistor also helps isolate memory cells during operations, minimizing interference and improving overall reliability. The invention is particularly useful in high-density memory arrays where minimizing cell-to-cell interference and optimizing performance are critical.
14. The method of claim 13 , further comprising floating a third source select line coupled to the third source select transistor.
A method for managing source select transistors in a memory device involves controlling multiple source select transistors to improve performance and reliability. The method includes activating a first source select transistor coupled to a first source select line and a second source select transistor coupled to a second source select line. The first and second source select transistors are part of a memory array, where the first source select transistor is connected to a first string of memory cells and the second source select transistor is connected to a second string of memory cells. The method further includes floating a third source select line coupled to a third source select transistor, which is connected to a third string of memory cells. By floating the third source select line, the third source select transistor remains in a non-conductive state, preventing unintended current flow or interference with the first and second strings of memory cells. This selective activation and floating of source select lines allows for precise control over memory cell access, reducing power consumption and improving data integrity in the memory device. The method is particularly useful in non-volatile memory systems, such as NAND flash memory, where efficient and reliable data access is critical.
15. The method of claim 13 , further comprising floating a third source select line coupled to the third source select transistor when the first voltage is applied to the first source select line and the second voltage is applied to the second source select line.
This invention relates to semiconductor memory devices, specifically non-volatile memory such as NAND flash, addressing issues with source select transistors during programming operations. The problem involves ensuring proper isolation and voltage distribution in memory arrays to prevent unintended data disturbances or leakage currents. The method involves controlling multiple source select transistors in a memory array. A first source select line is coupled to a first source select transistor and receives a first voltage, while a second source select line is coupled to a second source select transistor and receives a second voltage. Additionally, a third source select line is floated when the first and second voltages are applied. This floating action helps manage voltage distribution across the array, reducing stress on unselected memory cells and improving reliability. The technique ensures that during programming operations, the third source select transistor remains in a non-conductive state, preventing current leakage and maintaining proper isolation between memory blocks. The method is particularly useful in multi-level cell (MLC) or triple-level cell (TLC) NAND flash memory, where precise voltage control is critical to avoid data corruption. By floating the third source select line under specific conditions, the invention enhances operational stability and extends the lifespan of the memory device.
16. The method of claim 13 , further comprising floating a third source select line coupled to the third source select transistor when the first source select line is floated and the second voltage is applied to the second source select line.
A method for controlling source select transistors in a memory device addresses the challenge of efficiently managing data retention and read operations in non-volatile memory arrays. The method involves selectively applying voltages to source select lines connected to source select transistors to control current flow during memory operations. Specifically, the method includes floating a first source select line while applying a second voltage to a second source select line to isolate or enable specific memory cells. Additionally, the method further includes floating a third source select line when the first source select line is floated and the second voltage is applied to the second source select line. This ensures proper isolation of unselected memory cells during read or program operations, preventing unintended current paths and improving data integrity. The method is particularly useful in multi-level memory architectures where precise control of source select transistors is critical for reliable operation. By dynamically adjusting the voltages and floating conditions of the source select lines, the method enhances performance and reliability in memory devices.
17. The method of claim 1 , wherein a channel region of the memory strings included in the selected memory block is precharged using the precharge voltage.
This invention relates to memory devices, specifically to methods for operating non-volatile memory, such as NAND flash memory. The problem addressed is improving the efficiency and reliability of memory operations, particularly during read or program operations, by controlling the voltage conditions in the memory strings. The method involves precharging a channel region of memory strings within a selected memory block using a precharge voltage. This precharge step ensures that the channel region reaches a desired voltage level before the main operation (e.g., read or program) begins. The precharge voltage is applied to the memory strings to stabilize the channel potential, reducing variability in threshold voltage sensing and improving data integrity. The precharge process may involve applying the voltage to multiple memory strings simultaneously to enhance efficiency. The method may also include adjusting the precharge voltage based on operating conditions, such as temperature or wear level, to optimize performance. By precharging the channel region, the method minimizes disturbances and improves the accuracy of subsequent memory operations. This technique is particularly useful in high-density memory arrays where precise voltage control is critical for reliable data storage and retrieval.
18. A method of operating a semiconductor device including memory blocks sharing a common source line, each of the memory blocks including memory strings coupled between the common source line and bit lines, each of the memory strings including a first group of source select transistors, a second group of source select transistors, and memory cells, wherein the first group is coupled between the common source line and the second group, the method comprising: applying a positive voltage to a first source select line coupled to a first group of memory strings included in an unselected memory block, among the memory blocks; floating the first source select line after the positive voltage is applied thereto; applying a voltage for turning off the second group to a second source select line coupled to a second group of memory cell strings included in the unselected memory block; applying a precharge voltage to the common source line; and applying a program voltage to a word line coupled to selected memory cells of memory strings included in a selected memory block, among the memory blocks.
This invention relates to semiconductor memory devices, specifically NAND flash memory, where multiple memory blocks share a common source line. The problem addressed is minimizing interference between selected and unselected memory blocks during programming operations, which can degrade data integrity. The method involves controlling source select transistors in unselected memory blocks to prevent unintended current paths. Each memory block contains memory strings with two groups of source select transistors connected between a common source line and bit lines. The first group is closer to the source line, while the second group is closer to the memory cells. During programming, a positive voltage is applied to the first source select line of unselected blocks to temporarily turn on the first group of transistors. After this voltage is applied, the line is floated. The second group of source select transistors in unselected blocks is turned off by applying an appropriate voltage to their select line. A precharge voltage is then applied to the common source line, and a program voltage is applied to the word line of the selected memory block to program the target memory cells. This approach isolates unselected blocks, reducing interference and improving programming reliability.
19. A semiconductor device, comprising: a common source line; a first memory block including first memory strings coupled between the common source and first bit lines, each of the first memory strings including a first source select transistor, a second source select transistor and memory cells, wherein the first source select transistor is located closer to the common source line than the second source select transistor; a second memory block including second memory strings coupled between the common source and second bit lines, each of the second memory strings including a third source select transistor, a fourth source select transistor and memory cells, wherein the third source select transistor is located closer to the common source line than the fourth source select transistor; a peripheral circuit configured to perform a program operation on the first and second memory strings; and a control logic circuit controlling the peripheral circuit to apply a first voltage to a first source select line coupled to first source select transistors of the first memory strings when the second memory block is selected, float the first source select line after the first voltage is applied thereto, apply a second voltage having a lower voltage level than the first voltage to a second source select line coupled to second source select transistors of the first memory strings, apply a precharge voltage to the common source line, and apply a program voltage to a word line coupled to selected memory cells of the second memory strings.
A semiconductor device includes a common source line and multiple memory blocks, each containing memory strings with memory cells and source select transistors. Each memory string has two source select transistors, with one positioned closer to the common source line than the other. The device also includes a peripheral circuit for programming operations and a control logic circuit that manages these operations. During programming, the control logic applies a first voltage to the source select line connected to the first source select transistors of a non-selected memory block, then floats that line. A second, lower voltage is applied to the source select line connected to the second source select transistors of the non-selected block. A precharge voltage is applied to the common source line, and a program voltage is applied to the word line of the selected memory cells in the selected memory block. This configuration helps isolate non-selected memory blocks during programming, reducing interference and improving data integrity. The device is designed for use in memory systems where multiple blocks share a common source line, requiring careful voltage management to prevent unintended programming or data corruption.
20. The semiconductor device of claim 19 , wherein the first voltage is a positive voltage, the second voltage has a lower voltage level than threshold voltages of the second source select transistors, and the first source select line is located between the common source line and the second source select line.
A semiconductor device includes a memory cell array with multiple NAND strings, each having a plurality of memory cells connected in series between a bit line and a source line. The device includes a first source select transistor and a second source select transistor connected in series between the memory cells and a common source line. The first source select transistor is controlled by a first source select line, and the second source select transistor is controlled by a second source select line. The first voltage applied to the first source select line is a positive voltage, while the second voltage applied to the second source select line has a lower voltage level than the threshold voltages of the second source select transistors. The first source select line is positioned between the common source line and the second source select line. This configuration ensures proper selection and isolation of the NAND strings during read, program, and erase operations, improving reliability and performance. The device may be used in non-volatile memory systems, such as flash memory, where efficient source line selection is critical for accurate data storage and retrieval. The arrangement of the source select transistors and their respective control voltages helps prevent unintended current paths and enhances the overall stability of the memory device.
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October 14, 2020
February 1, 2022
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