Memory devices including a controller for access of an array of memory cells that is configured to accept a sequence of commands to cause the memory device to read a first set of data from the array of memory cells into a first register, load the first set of data into a first portion of a second register, write a set of test data to a second portion of the second register during a reading of a second set of data from the array of memory cells to the first register, read the set of test data from the second portion of the second register during the reading of the second set of data, and output the set of test data from the memory device during the reading of the second set of data.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A memory device, comprising: an array of memory cells; a first register in communication with the array of memory cells; a second register in communication with the first register; and a controller for access of the array of memory cells; wherein the controller is configured to accept a sequence of commands to cause the memory device to: read a first set of data from the array of memory cells into the first register; load the first set of data into a first portion of the second register; receive a set of test data from an external device; write the set of test data to a second portion of the second register during a reading of a second set of data from the array of memory cells to the first register, wherein the second portion of the second register is different than the first portion of the second register; read the set of test data from the second portion of the second register during the reading of the second set of data from the array of memory cells to the first register; and output the set of test data, read from the second portion of the second register, from the memory device during the reading of the second set of data from the array of memory cells to the first register.
A memory device includes an array of memory cells, a first register, a second register, and a controller. The controller manages access to the memory cells and executes a sequence of commands to perform specific operations. The device reads a first set of data from the memory array into the first register, then loads this data into a first portion of the second register. While reading a second set of data from the memory array into the first register, the device receives test data from an external source and writes it to a second portion of the second register, distinct from the first portion. During this same operation, the device reads the test data from the second portion of the second register and outputs it from the memory device. This allows concurrent data transfer and testing, improving efficiency by overlapping read and test operations. The second register is partitioned to enable simultaneous handling of different data sets, facilitating faster processing and reducing latency in memory access and verification tasks. The controller coordinates these operations to ensure proper sequencing and data integrity.
2. The memory device of claim 1 , wherein the reading of the second set of data from the array of memory cells to the first register comprises performing a read operation on the array of memory cells.
This invention relates to memory devices, specifically addressing the challenge of efficiently reading data from an array of memory cells. The device includes an array of memory cells, a first register, and a second register. The first register is configured to store a first set of data read from the array, while the second register is configured to store a second set of data also read from the array. The reading of the second set of data from the array to the first register involves performing a read operation on the array of memory cells. This allows for the transfer of data between the array and the registers, enabling efficient data management and processing within the memory device. The invention may also include additional features such as a controller to manage the read operations and data transfer processes, ensuring accurate and timely retrieval of data from the memory cells. The overall design aims to improve data access speed and reliability in memory storage systems.
3. The memory device of claim 1 , wherein the controller is configured to accept the sequence of commands in a debug mode of the memory device.
A memory device includes a controller that processes a sequence of commands to perform a specific operation, such as reading, writing, or erasing data. The controller is configured to accept this sequence of commands in a debug mode of the memory device, allowing for testing, verification, or troubleshooting of the device's functionality. The debug mode may provide additional access to internal operations, registers, or status information that are not available in normal operating modes. This enables developers or manufacturers to diagnose issues, validate performance, or optimize the device's behavior under controlled conditions. The debug mode may be activated through a dedicated command, a specific sequence of inputs, or a hardware signal, ensuring that it is only accessible under authorized conditions to prevent unauthorized access or tampering. The memory device may be a non-volatile storage device, such as a flash memory, solid-state drive, or other storage medium, where reliable and secure operation is critical. The debug mode enhances the ability to verify the device's compliance with specifications and identify potential defects or vulnerabilities before deployment.
4. The memory device of claim 1 , wherein the controller is further configured to accept a command to cause the memory device to enter a debug mode of the memory device prior to loading the first set of data to the first portion of the second register.
A memory device includes a controller and a register divided into multiple portions. The controller is configured to load a first set of data into a first portion of the register and a second set of data into a second portion of the register. The controller can also accept a command to enter a debug mode before loading the first set of data into the first portion of the register. In debug mode, the controller may perform additional operations such as verifying data integrity, testing memory access, or enabling diagnostic features. The register may be part of a larger memory array or a dedicated control register. The debug mode allows for troubleshooting and validation of memory operations before normal operation begins. The controller may also manage data transfer between the register and other memory components, ensuring proper synchronization and error handling. The debug mode command can be issued by an external host or an internal diagnostic module, providing flexibility in testing scenarios. This design enhances reliability and simplifies debugging processes in memory devices.
5. The memory device of claim 4 , wherein the controller is configured to accept the sequence of commands only in the debug mode.
This invention relates to memory devices with enhanced security features, specifically addressing the problem of unauthorized access to debug or test modes that could expose sensitive data or system vulnerabilities. The memory device includes a controller that manages access to debug functionality, ensuring that certain operations are restricted to authorized users or specific operational states. The controller is configured to accept a sequence of commands only when the device is in a designated debug mode, preventing unauthorized activation of debug features during normal operation. This restriction helps maintain system integrity by limiting exposure of internal operations and sensitive data to potential attackers. The controller may also include additional security measures, such as authentication or encryption, to further protect against unauthorized access. By enforcing strict control over debug command execution, the invention mitigates risks associated with debug mode exploitation while still allowing legitimate debugging and testing activities when necessary. The overall design ensures that debug functionality remains accessible only under controlled conditions, enhancing the security of the memory device in both development and deployment environments.
6. The memory device of claim 1 , wherein the first register is a page register of the memory device and wherein the second register is a cache register of the memory device.
This invention relates to memory devices, specifically improving data handling efficiency by using distinct registers for different operations. The problem addressed is the inefficiency in conventional memory devices where a single register may be used for multiple purposes, leading to bottlenecks and delays in data processing. The memory device includes a first register, which is a page register, and a second register, which is a cache register. The page register is used to store address and command information for accessing memory pages, while the cache register temporarily holds frequently accessed data to reduce latency. By separating these functions into dedicated registers, the device enhances performance by allowing parallel operations—address decoding and data caching—without contention for a single register resource. This design reduces access time and improves overall system efficiency, particularly in high-speed applications where rapid data retrieval is critical. The use of distinct registers also simplifies control logic, as each register serves a specific role without overlapping responsibilities. This approach is particularly beneficial in memory-intensive systems, such as processors, graphics cards, or storage controllers, where minimizing latency is essential. The invention optimizes memory access by leveraging specialized registers to streamline data flow and reduce operational delays.
7. A memory device, comprising: an array of memory cells; a first register in communication with the array of memory cells; a second resister in communication with the first register; and a controller for access of the array of memory cells; wherein the controller is configured to accept a sequence of commands to cause the memory device to: read a first set of data from the array of memory cells into the first register; load the first set of data into a first portion of the second register; write a set of test data to a second portion of the second register during a reading of a second set of data from the array of memory cells to the first register, wherein the second portion of the second register is different than the first portion of the second register; read the set of test data from the second portion of the second register during the reading of the second set of from the array of memory cells to the first register; and output the set of test data, read from the second portion of the second register, from the memory device during the reading of the second set of data from the array of memory cells to the first register; and wherein the controller is further configured to accept commands to cause the memory device to: enter a debug mode of the memory device prior to loading the first set of data into the first portion of the second register; and exit the debug mode after outputting the set of test data read from the second portion of the second register.
The invention relates to a memory device designed to improve debugging and testing capabilities during memory operations. The device includes an array of memory cells, a first register connected to the array, a second register connected to the first register, and a controller that manages access to the memory cells. The controller executes a sequence of commands to facilitate concurrent data operations and debugging. First, it reads a set of data from the memory array into the first register, then loads this data into a portion of the second register. While reading a second set of data from the array into the first register, the controller writes test data to a different portion of the second register. During this same operation, the controller reads the test data from the second register and outputs it from the device. The controller also supports entering and exiting a debug mode to control these operations. This design allows for parallel execution of normal memory operations and debugging tasks, enhancing efficiency in testing and validation processes. The system ensures that test data can be processed without interrupting the primary data flow, making it useful for real-time debugging scenarios.
8. A memory device, comprising: an array of memory cells; a first register in communication with the array of memory cells; a second register in communication with the first register; and a controller for access of the array of memory cells; wherein the controller is configured to accept a sequence of commands to cause the memory device to: read a first set of data from the array of memory cells into the first register; load the first set of data into a first portion of the second register; write a set of test data to a second portion of the second register during a reading of a second set of data from the array of memory cells to the first register, wherein the second portion of the second register is different than the first portion of the second register; read the set of test data from the second portion of the second register during the reading of the second set of data from the array of memory cells to the first register; and output the set of test data, read from the second portion of the second register, from the memory device during the reading of the second set of data from the array of memory cells to the first register; wherein the controller being configured to cause the memory device to read the set of test data from the second portion of the second register comprises the controller being configured to cause the memory device to read data from the first portion of the second register and from the second portion of the second register.
This invention relates to a memory device designed to improve data access efficiency by using dual registers to handle concurrent operations. The device includes an array of memory cells, a first register connected to the memory array, and a second register connected to the first register. A controller manages access to the memory array and executes a sequence of commands to optimize data handling. The controller reads a first set of data from the memory array into the first register, then loads this data into a first portion of the second register. While the first register is reading a second set of data from the memory array, the controller writes test data into a second portion of the second register, distinct from the first portion. During this operation, the controller reads the test data from the second portion of the second register and outputs it from the memory device, all while the first register continues reading the second set of data. The controller is configured to read data from both portions of the second register simultaneously, enabling parallel processing of different data sets. This design allows the memory device to perform overlapping read and write operations, improving throughput and reducing latency in data access tasks.
9. A memory device, comprising: an array of memory cells; a first register in communication with the array of memory cells; a second register in communication with the first register; and a controller for access of the array of memory cells; wherein the controller is configured to accept a sequence of commands to cause the memory device to: read a first set of data from the array of memory cells into the first register; load the first set of data into a first portion of the second register; write a set of test data to a second portion of the second register during a reading of a second set of data from the array of memory cells to the first register, wherein the second portion of the second register is different than the first portion of the second register; read the set of test data from the second portion of the second register during the reading of the second set of data from the array of memory cells to the first register; and output the set of test data, read from the second portion of the second register, from the memory device during the reading of the second set of data from the array of memory cells to the first register; wherein the controller being configured to cause the memory device to read the set of test data from the second portion of the second register comprises the controller being configured to cause the memory device to read the set of test data from the second portion of the second register without reading data from the first portion of the second register.
The invention relates to a memory device designed to improve data access efficiency by utilizing a dual-register architecture for concurrent operations. The device includes an array of memory cells, a first register connected to the array, and a second register divided into distinct portions. A controller manages access to the memory cells and executes a sequence of commands to perform overlapping read and test operations. The first register receives data from the memory array, while the second register stores this data in a first portion. Simultaneously, a second portion of the second register is used to write and read test data without interfering with the ongoing data transfer. The controller ensures that test data is read from the second portion independently, without accessing the first portion, allowing the memory device to output test results during active data reads. This design enables parallel processing of test and operational data, enhancing performance by reducing latency in memory access operations. The invention addresses inefficiencies in traditional memory systems where test and data operations are sequential, improving throughput and responsiveness in applications requiring real-time data validation.
10. The memory device of claim 9 , wherein the controller is further configured to accept a command to cause the memory device to clear the second register during the reading of the second set of data and prior to writing the set of test data to the second portion of the second register.
This invention relates to memory devices with enhanced data handling capabilities, particularly for testing and validation purposes. The problem addressed is the need to efficiently manage and clear register data during read and write operations to ensure accurate testing without interference from residual data. The memory device includes a controller and at least one register divided into multiple portions. The controller is configured to read a first set of data from a first portion of the register and a second set of data from a second portion of the register. During the reading of the second set of data, the controller can accept a command to clear the second portion of the register before writing a set of test data to it. This ensures that the test data is written to a clean register portion, preventing corruption or interference from previously stored data. The clearing operation is performed dynamically during the read process, optimizing the testing workflow by eliminating the need for separate clearing steps. This feature is particularly useful in scenarios where repeated testing cycles are required, such as during manufacturing or validation phases. The invention improves efficiency and reliability in memory device testing by integrating clearing operations seamlessly into the read process.
11. A memory device, comprising: an array of memory cells; a first register in communication with the array of memory cells; a second register in communication with the first register; and a controller for access of the array of memory cells; wherein the controller is configured to accept a sequence of commands to cause the memory device to: read a first set of data from the array of memory cells into the first register; load the first set of data into a first portion of the second register; clear the second register after loading the first set of data into the second register and during a reading of a second set of data from the array of memory cells to the first register, then write a set of test data to a second portion of the cleared second register during the reading of the second set of data from the array of memory cells to the first register; read the set of test data from the second portion of the cleared second register during the reading of the second set of data from the array of memory cells to the first register; and outputting the set of test data, read from the second portion of the cleared second register, from the memory device.
A memory device includes an array of memory cells, a first register connected to the array, a second register connected to the first register, and a controller for managing access to the array. The controller executes a sequence of commands to perform a data handling operation. First, data is read from the array into the first register. This data is then loaded into a first portion of the second register. While the second register is being loaded, the controller clears the second register and begins reading a second set of data from the array into the first register. During this second read operation, test data is written to a second portion of the cleared second register. The test data is then read from the second portion of the second register while the second set of data continues to be read into the first register. Finally, the test data is output from the memory device. This process allows concurrent data handling and test operations, improving efficiency in memory access and testing. The second register is partially cleared and reused for different operations, enabling parallel processing of data and test patterns.
12. The memory device of claim 11 , wherein the controller being configured to cause the memory device to write the set of test data to the second portion of the cleared second register comprises the controller being configured to cause the memory device to write the set of test data to any portion of the cleared second register.
A memory device includes a controller and a register with at least two portions. The controller is configured to clear a second portion of the register and then write a set of test data to any portion of the cleared second register. The register may be a multi-ported register, allowing simultaneous access to different portions. The controller can also perform operations such as clearing a first portion of the register and writing data to the first portion. The memory device may include additional registers, and the controller can manage data transfer between these registers. The test data writing process ensures that the cleared portion of the register is properly initialized before further operations. This configuration allows for flexible and efficient data handling in memory operations, particularly in systems requiring rapid testing or validation of register states. The ability to write test data to any portion of the cleared register enhances the device's adaptability in various memory management scenarios.
13. The memory device of claim 11 , wherein the controller being configured to cause the memory device to read the set of test data from the second portion of the second register comprises the controller being configured to cause the memory device to read only the set of test data that was written to the second portion of the second register.
This invention relates to memory devices, specifically improving data handling and testing within memory systems. The problem addressed is ensuring accurate and efficient reading of test data from memory registers, particularly when only specific portions of the register are used for testing. Traditional methods may read unnecessary or incorrect data, leading to inefficiencies or errors in testing. The memory device includes a controller and at least one register divided into portions. The controller is configured to write a set of test data to a second portion of a second register. When reading the test data, the controller ensures that only the data written to the second portion is retrieved, avoiding any extraneous or previously stored data. This selective reading prevents contamination of test results by irrelevant data, improving the reliability of memory testing and validation processes. The controller may also manage other operations, such as writing data to a first portion of the second register or reading data from a first register, but the focus is on the precise retrieval of test data from the designated portion. This selective read operation enhances testing accuracy and reduces unnecessary data processing, optimizing memory device performance.
14. A memory device, comprising: an array of memory cells; a page register in communication with the array of memory cells; a cache register in communication with the page register; and a controller for access of the array of memory cells; wherein the controller is configured to accept a sequence of commands to cause the memory device to: read a first set of data from the array of memory cells into the page register; load the first set of data into a first portion of the cache register; receive a set of test data from an external device; write the set of test data to a second portion of the cache register during a reading of a second set of data from the array of memory cells to the page register, wherein the second portion of the cache register is mutually exclusive from the first portion of the cache register; read the set of test data from the second portion of the cache register during the reading of the second set of data from the array of memory cells to the page register; and output the set of test data, read from the second portion of the cache register, from the memory device during the reading of the second set of data from the array of memory cells to the page register.
This invention relates to memory devices, specifically improving data handling efficiency during read operations. The problem addressed is the latency and inefficiency in memory devices when performing concurrent read and write operations, particularly in systems requiring fast data access and testing. The memory device includes an array of memory cells, a page register, a cache register, and a controller. The page register temporarily stores data read from the array, while the cache register further buffers data for faster access. The controller manages data flow between these components and external devices. The device operates by first reading a first set of data from the memory array into the page register, then loading this data into a first portion of the cache register. While a second set of data is being read from the array into the page register, the controller receives test data from an external device and writes it to a second, non-overlapping portion of the cache register. During this same read operation, the controller reads the test data from the second cache portion and outputs it from the device. This allows concurrent data read and test data handling, reducing latency and improving efficiency in memory operations. The invention is particularly useful in systems requiring real-time data processing and testing, such as embedded systems or high-performance computing environments.
15. The memory device of claim 14 , wherein the controller is configured to accept the sequence of commands in a debug mode of the memory device.
A memory device includes a controller that processes a sequence of commands to perform a specific operation, such as reading, writing, or erasing data. The controller is configured to execute these commands in a predefined order, ensuring proper sequencing and timing. In a debug mode, the controller accepts the sequence of commands, allowing for testing, verification, or troubleshooting of the memory device's functionality. The debug mode may include additional features, such as command logging, error detection, or performance monitoring, to assist in diagnosing issues or optimizing performance. The memory device may be a non-volatile storage device, such as a flash memory, solid-state drive, or other storage medium, where reliable command execution is critical. The debug mode enables developers or technicians to validate command sequences, identify errors, and ensure proper operation before deployment in a production environment. This capability is particularly useful in verifying firmware updates, hardware compatibility, or system integration. The controller may also include error correction mechanisms to handle command execution failures during debugging. The overall system ensures robust command processing while providing flexibility for testing and validation.
16. The memory device of claim 14 , wherein the controller is further configured to accept a command to cause the memory device to enter a debug mode of the memory device prior to loading the first set of data to the first portion of the cache register.
This invention relates to memory devices with enhanced debugging capabilities. The problem addressed is the difficulty in diagnosing and resolving issues in memory devices during development and testing phases, particularly when accessing and analyzing internal data states. Traditional memory devices lack efficient mechanisms to inspect or manipulate internal registers during operation, making debugging cumbersome. The invention provides a memory device with a controller configured to enter a debug mode in response to a specific command. In debug mode, the controller allows external access to a cache register, which is divided into multiple portions. Before loading data into a first portion of the cache register, the controller accepts a command to activate debug mode. This enables developers to monitor, modify, or extract data from the cache register during operation, facilitating real-time debugging. The controller may also support additional commands to control data flow, such as loading or unloading data between the cache register and other memory components. The debug mode can be exited upon receiving another command, restoring normal operation. This approach improves debugging efficiency by providing direct access to internal memory states without disrupting normal functionality.
17. The memory device of claim 16 , wherein the controller is configured to accept the sequence of commands only in the debug mode.
A memory device includes a controller that processes a sequence of commands to perform a specific operation, such as erasing or programming memory cells. The controller is configured to accept this sequence of commands only when the device is in a debug mode, a special operational state distinct from normal operation. In debug mode, the controller may execute additional diagnostic or testing functions that are not available during standard operation. The memory device may include non-volatile memory cells, such as flash memory, and the controller may manage data storage, retrieval, and error correction. The debug mode allows for testing and verification of memory operations without interfering with normal device functionality. The controller may also include security features to prevent unauthorized access to debug functions. This approach ensures that sensitive operations are only performed under controlled conditions, reducing the risk of accidental or malicious misuse. The memory device may be part of a larger system, such as a storage drive or embedded memory module, where reliable and secure operation is critical.
18. A memory device, comprising: an array of memory cells; a page register in communication with the array of memory cells; a cache register in communication with the page register; and a controller for access of the array of memory cells; wherein the controller is configured to accept a sequence of commands to cause the memory device to: read a first set of data from the array of memory cells into the page register; load the first set of data into a first portion of the cache register; write a set of test data to a second portion of the cache register during a reading of a second set of data from the array of memory cells to the page register, wherein the second portion of the cache register is mutually exclusive from the first portion of the cache register; read the set of test data from the second portion of the cache register during the reading of the second set of data from the array of memory cells to the page register; and output the set of test data, read from the second portion of the cache register, from the memory device during the reading of the second set of data from the array of memory cells to the page register; and wherein the controller is further configured to accept commands to cause the memory device to: enter a debug mode of the memory device prior to loading the first set of data into the first portion of the cache register; and exit the debug mode after outputting the set of test data read from the second portion of the cache register.
This invention relates to memory devices, specifically a system for debugging memory operations without interrupting normal data access. The problem addressed is the need to test and verify memory functionality while maintaining continuous data flow, avoiding disruptions that could affect system performance. The memory device includes an array of memory cells, a page register for temporary data storage, a cache register divided into distinct portions, and a controller managing access to the memory array. The controller executes a sequence of commands to read data from the memory array into the page register, then loads this data into a first portion of the cache register. Simultaneously, test data is written to a second, mutually exclusive portion of the cache register while a second set of data is being read from the memory array to the page register. The test data is then read from the cache register and output from the device during the ongoing data read operation. The controller also supports entering and exiting a debug mode to enable and disable this testing functionality. This approach allows for real-time debugging without halting normal memory operations, ensuring uninterrupted data access while verifying memory integrity.
19. A memory device, comprising: an array of memory cells; a page register in communication with the array of memory cells; a cache register in communication with the page register; and a controller for access of the array of memory cells; wherein the controller is configured to accept a sequence of commands to cause the memory device to: read a first set of data from the array of memory cells into the page register; load the first set of data into a first portion of the cache register; write a set of test data to a second portion of the cache register during a reading of a second set of data from the array of memory cells to the page register, wherein the second portion of the cache register is mutually exclusive from the first portion of the cache register; read the set of test data from the second portion of the cache register during the reading of the second set of data from the array of memory cells to the page register; and output the set of test data, read from the second portion of the cache register, from the memory device during the reading of the second set of data from the array of memory cells to the page register; wherein the controller being configured to cause the memory device to read the set of test data from the second portion of the cache register comprises the controller being configured to cause the memory device to read the set of test data from the second portion of the cache register and to read the first set of data from the first portion of the cache register.
This invention relates to memory devices, specifically improving data access efficiency by allowing concurrent operations in a cache register. The problem addressed is the latency and inefficiency in traditional memory devices where data transfer between memory arrays and cache registers is sequential, causing delays in accessing multiple data sets. The solution involves a memory device with an array of memory cells, a page register, a cache register, and a controller. The controller executes a sequence of commands to read a first set of data from the memory array into the page register and then load it into a first portion of the cache register. While a second set of data is being read from the memory array to the page register, the controller writes test data to a second, mutually exclusive portion of the cache register. The test data is then read from the second portion of the cache register concurrently with the ongoing read operation of the second set of data. The test data is output from the memory device during this concurrent read operation. The controller ensures that the test data and the first set of data are read from their respective portions of the cache register simultaneously, enabling efficient parallel data access. This design reduces latency by allowing overlapping read and write operations in the cache register, improving overall memory device performance.
20. A memory device, comprising: an array of memory cells; a page register in communication with the array of memory cells; a cache register in communication with the page register; and a controller for access of the array of memory cells; wherein the controller is configured to accept a sequence of commands to cause the memory device to: read a first set of data from the array of memory cells into the page register; load the first set of data into a first portion of the cache register; write a set of test data to a second portion of the cache register during a reading of a second set of data from the array of memory cells to the page register, wherein the second portion of the cache register is mutually exclusive from the first portion of the cache register; read the set of test data from the second portion of the cache register during the reading of the second set of data from the array of memory cells to the page register; and output the set of test data, read from the second portion of the cache register, from the memory device during the reading of the second set of data from the array of memory cells to the page register; wherein the controller being configured to cause the memory device to read the set of test data from the second portion of the cache register comprises the controller being configured to cause the memory device to read the set of test data from the second portion of the cache register without reading data from the first portion of the cache register.
A memory device includes an array of memory cells, a page register, a cache register, and a controller. The page register communicates with the array to transfer data, while the cache register communicates with the page register to store subsets of data. The controller manages access to the array and processes commands to perform specific operations. The device reads a first set of data from the array into the page register and loads it into a first portion of the cache register. Simultaneously, while reading a second set of data from the array into the page register, the controller writes test data to a second portion of the cache register, which is mutually exclusive from the first portion. The controller then reads the test data from the second portion of the cache register during the ongoing read operation of the second set of data and outputs the test data from the device without accessing the first portion of the cache register. This allows concurrent data processing and testing within the memory device, improving efficiency by overlapping operations. The design ensures that test data operations do not interfere with active data transfers, maintaining performance while enabling diagnostic or verification tasks.
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March 24, 2020
February 1, 2022
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