A memory system performs Error Correcting Code (ECC) decoding on data read from a plurality of target memory cells of a memory device, determines whether to update a read bias used in read operations of the memory device according to results of the ECC decoding, and then may update a value of the read bias based on result data produced by the ECC decoding and the number of data bits corrected by the ECC decoding, thereby optimizing the read bias value according to a change in a threshold voltage distribution of the memory cell, and increasing the likelihood of success of the ECC decoding.
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1. A memory system comprising: a memory device; and a memory controller configured to control the memory device, wherein the memory controller: performs Error Correcting Code (ECC) decoding on read data read from a plurality of target memory cells included in the memory device, and in response to the ECC decoding succeeding: determines whether to update one or more read biases used for reading data programmed in the plurality of target memory cells, and in response to determining to update the one or more read biases, updates a read bias of the one or more read biases based on information regarding: i) result data generated by the ECC decoding and ii) a number data bits corrected during the ECC decoding, and wherein the memory controller determines a direction in which the read bias is updated based on a first fail bit rate and a second fail bit rate when updating the read bias.
The memory system addresses the challenge of maintaining data integrity in non-volatile memory devices by dynamically adjusting read biases to compensate for variations in memory cell characteristics over time. The system includes a memory device and a memory controller that performs Error Correcting Code (ECC) decoding on data read from target memory cells. If the ECC decoding succeeds, the controller evaluates whether to update the read biases used for reading the programmed data. When an update is determined necessary, the controller adjusts the read bias based on the ECC decoding results and the number of corrected bits. The direction of the bias adjustment is determined by comparing a first fail bit rate and a second fail bit rate, ensuring optimal read margins. This adaptive approach improves read reliability by dynamically compensating for shifts in memory cell thresholds, reducing errors and extending the lifespan of the memory device. The system avoids static bias settings, which may degrade over time due to wear or environmental factors, by continuously refining read parameters based on real-time ECC performance. This method enhances data accuracy and system longevity in storage applications.
2. The memory system of claim 1 , wherein the memory controller determines the first fail bit rate as a ratio of the number of data bits having a value of 1 among the result data to the number of data bits having a value corrected from 0 to 1 during the ECC decoding, and determines the second fail bit rate as a ratio of the number of data bits having a value of 0 among the result data to the number of data bits having a value corrected from 1 to 0 during the ECC decoding.
The invention relates to memory systems, specifically improving error detection and correction in non-volatile memory devices. The problem addressed is accurately assessing memory cell degradation by distinguishing between different types of bit errors during error correction code (ECC) decoding. Traditional methods may not effectively differentiate between errors caused by cells transitioning from 0 to 1 (program disturb) versus 1 to 0 (retention loss), leading to suboptimal wear leveling and reliability management. The memory system includes a memory controller that analyzes fail bit rates during ECC decoding. The controller calculates a first fail bit rate by comparing the number of data bits with a value of 1 in the corrected result data to the number of bits corrected from 0 to 1. Similarly, it calculates a second fail bit rate by comparing the number of data bits with a value of 0 in the corrected result data to the number of bits corrected from 1 to 0. This differentiation allows the system to track distinct failure mechanisms, enabling more precise memory management. The controller may use these rates to adjust read voltages, trigger refresh operations, or redistribute data to mitigate degradation. The approach enhances reliability by tailoring error handling to specific failure modes, extending the lifespan of non-volatile memory devices.
3. The memory system of claim 2 , wherein the memory controller determines a magnitude by which the read bias is updated based on a first standard deviation and a second standard deviation when updating the read bias, the first standard deviation is an expected standard deviation for a threshold voltage distribution of a memory cell having a value of 1 among the target memory cells, and the second standard deviation is an expected standard deviation for a threshold voltage distribution of a memory cell having a value of zero among the target memory cells.
This invention relates to memory systems, specifically to improving read operations in non-volatile memory by dynamically adjusting read bias voltages based on statistical properties of memory cell threshold voltage distributions. The problem addressed is the degradation of read accuracy over time due to variations in memory cell threshold voltages, which can lead to read errors as the memory cells wear out. The memory system includes a memory controller that updates a read bias voltage used to distinguish between memory cells storing a logical '1' and those storing a logical '0'. The controller determines the magnitude of the read bias update by comparing two standard deviations: one representing the expected spread of threshold voltages for cells storing '1' and another for cells storing '0'. By analyzing these statistical distributions, the controller adjusts the read bias to maintain optimal read accuracy despite variations in cell characteristics over time. This adaptive approach reduces read errors and extends the lifespan of the memory system by compensating for shifts in threshold voltage distributions caused by wear or environmental factors. The system may also include mechanisms to track and predict these distributions, ensuring reliable data retrieval even as memory cells degrade.
4. The memory system of claim 3 , wherein the memory controller determines the first standard deviation and the second standard deviation from among a plurality of standard deviations included in an expected standard deviation group based on a program-erase count of the target memory cells, a retention time of the target memory cells, or both.
The invention relates to a memory system, specifically a method for managing data reliability in non-volatile memory devices such as flash memory. The system addresses the challenge of maintaining data integrity over time, as memory cells degrade due to repeated program-erase cycles and prolonged retention periods. To mitigate this, the memory controller calculates a first standard deviation and a second standard deviation from a predefined group of expected standard deviations. These standard deviations represent variations in threshold voltage distributions of memory cells, which are critical for accurate data read operations. The selection of the first and second standard deviations is based on factors such as the program-erase count of the target memory cells, the retention time of the data stored in those cells, or a combination of both. By dynamically adjusting these parameters, the system improves read accuracy and extends the lifespan of the memory cells. The invention ensures reliable data retrieval even as memory cells age, enhancing overall system performance and durability.
5. The memory system of claim 1 , wherein when the number of read biases is more than one, the memory controller updates each of the read biases based on information obtained by dividing the result data into a plurality of data bit groups corresponding to each read bias when updating that read bias.
This invention relates to memory systems, specifically improving read operations in non-volatile memory by dynamically adjusting read biases. The problem addressed is the degradation of read accuracy over time due to variations in memory cell characteristics, such as threshold voltage shifts in flash memory. Traditional methods apply a single read bias or update biases based on aggregated error data, which may not account for cell-to-cell variations. The system includes a memory controller that manages read operations by applying multiple read biases to retrieve data from memory cells. When multiple read biases are used, the controller updates each bias individually. To do this, the controller divides the retrieved result data into multiple data bit groups, each corresponding to a specific read bias. The information from these groups is then used to refine the respective read bias, improving accuracy. This approach allows the system to adapt to different memory cell behaviors, enhancing reliability in read operations. The method ensures that each bias is optimized based on its specific data group, reducing errors caused by threshold voltage drift or other cell variations. The system may also include error correction mechanisms to further validate and correct data retrieved using the adjusted biases. This technique is particularly useful in high-density memory storage where cell variations are more pronounced.
6. The memory system of claim 1 , wherein the memory controller determines to update the read bias every time the ECC decoding succeeds.
A memory system includes a memory controller that adjusts a read bias voltage applied to a non-volatile memory array to optimize read operations. The system addresses the challenge of maintaining reliable data retrieval in non-volatile memory, where read errors can occur due to variations in memory cell characteristics over time. The memory controller monitors read operations and applies error correction coding (ECC) to detect and correct errors. When ECC decoding successfully corrects errors, the controller updates the read bias voltage to improve future read operations. This adaptive adjustment helps mitigate read disturbances and degradation in memory cells, ensuring consistent data integrity. The system may also include additional features such as dynamic bias adjustment based on environmental conditions or memory usage patterns, further enhancing reliability. The invention provides a self-correcting mechanism that automatically refines read parameters to extend the lifespan and performance of non-volatile memory devices.
7. The memory system of claim 1 , wherein the memory controller determines to update the read bias in response to the number of data bits corrected during the ECC decoding being greater than or equal to a predetermined threshold number of data bits.
A memory system includes a memory controller that adjusts a read bias voltage applied to a non-volatile memory array to improve read reliability. The system monitors the number of data bits corrected by an error correction code (ECC) decoder during read operations. If the number of corrected bits exceeds a predetermined threshold, the memory controller determines that the current read bias is insufficient and updates it to a different value. This adaptive adjustment helps maintain data integrity by compensating for variations in memory cell characteristics over time, such as those caused by wear or environmental factors. The read bias update may involve increasing or decreasing the voltage level based on the error rate, ensuring optimal read performance while minimizing errors. The system may also include additional logic to track error rates across multiple read operations to refine bias adjustments over time. This approach reduces the need for frequent and resource-intensive calibration processes, improving overall system efficiency.
8. The memory system of claim 1 , wherein the memory controller determines to update the read bias in response to a number of iterations of a decoding operation during the ECC decoding being greater than or equal to a predetermined threshold number of iterations.
The invention relates to memory systems, specifically to improving error correction in non-volatile memory devices. The problem addressed is the inefficiency in read operations when error correction decoding fails or requires excessive iterations, leading to degraded performance and reliability. The solution involves dynamically adjusting the read bias voltage applied to memory cells based on the number of decoding iterations required during error correction code (ECC) decoding. If the number of iterations exceeds a predetermined threshold, the memory controller updates the read bias to optimize read operations. This adaptive approach reduces read errors and improves overall system performance by avoiding unnecessary retries or failures. The memory controller monitors the decoding process and adjusts the read bias in real-time, ensuring efficient error correction without manual intervention. This method is particularly useful in flash memory and other non-volatile storage systems where read disturbances and wear can degrade data integrity over time. The invention enhances reliability and extends the lifespan of memory devices by dynamically adapting to changing read conditions.
9. A memory controller comprising: a memory interface configured to communicate with a memory device; and a control circuit configured to control the memory device, wherein the control circuit: performs Error Correcting Code (ECC) decoding on read data read from a plurality of target memory cells included in the memory device, and in response to the ECC decoding succeeding: determines whether to update one or more read biases used for reading data programmed in the plurality of target memory cells, and in response to determining to update the one or more read biases, updates a read bias of the one or more read biases based on information regarding: i) result data generated by the ECC decoding and ii) a number data bits corrected during the ECC decoding, and wherein the control circuit determines a direction in which the read bias is updated based on a first fail bit rate and a second fail bit rate, when updating the read bias.
This invention relates to memory controllers for managing memory devices, particularly focusing on improving read reliability through adaptive read bias adjustment. The problem addressed is the degradation of read accuracy in memory cells over time, which can lead to data errors. The solution involves a memory controller with a memory interface and a control circuit that performs Error Correcting Code (ECC) decoding on read data from target memory cells. If ECC decoding succeeds, the controller evaluates whether to update the read biases used for reading those cells. If an update is deemed necessary, the controller adjusts the read bias based on the ECC decoding results and the number of corrected bits. The direction of the bias adjustment is determined by comparing a first fail bit rate (e.g., before adjustment) with a second fail bit rate (e.g., after adjustment). This adaptive approach ensures optimal read conditions, reducing errors and improving memory reliability. The system dynamically learns from ECC outcomes to refine read operations, enhancing long-term data integrity.
10. The memory controller of claim 9 , wherein the control circuit: determines the first fail bit rate as a ratio of the number of data bits having a value of 1 among the result data to the number of data bits having a value corrected from 0 to 1 during the ECC decoding, and determines the second fail bit rate as a ratio of the number of data bits having a value of 0 among the result data to the number of data bits having a value corrected from 1 to 0 during the ECC decoding.
This invention relates to memory controllers with enhanced error correction capabilities, specifically addressing the challenge of accurately assessing memory cell degradation by distinguishing between different types of bit errors. In memory systems, error correction codes (ECC) are used to detect and correct bit errors in stored data, but conventional methods do not differentiate between errors that occur in cells initially storing a logical 0 versus those storing a logical 1. This limitation can lead to inaccurate assessments of memory wear and reliability. The memory controller includes a control circuit that analyzes error correction results to compute two distinct fail bit rates. The first fail bit rate quantifies the degradation of cells initially storing a logical 1 by comparing the number of 1s in the corrected data to the number of bits corrected from 0 to 1. The second fail bit rate quantifies the degradation of cells initially storing a logical 0 by comparing the number of 0s in the corrected data to the number of bits corrected from 1 to 0. This dual-rate approach provides a more precise measurement of memory cell reliability, enabling better wear-leveling and predictive maintenance strategies. The controller may also use these rates to adjust read and write operations dynamically, improving overall system longevity.
11. The memory controller of claim 10 , wherein the memory controller determines a magnitude by which the read bias is updated based on a first standard deviation and a second standard deviation when updating the read bias, the first standard deviation is an expected standard deviation for a threshold voltage distribution of a memory cell having a value of 1 among the target memory cells, and the second standard deviation is an expected standard deviation for a threshold voltage distribution of a memory cell having a value of zero among the target memory cells.
This invention relates to memory controllers for non-volatile memory, specifically improving read operations by dynamically adjusting read bias based on statistical properties of memory cell threshold voltage distributions. The problem addressed is maintaining accurate data retrieval as memory cells degrade over time, leading to overlapping threshold voltage distributions for stored '0' and '1' values. The memory controller monitors threshold voltage distributions of target memory cells to be read. When updating the read bias (a reference voltage used to distinguish '0' and '1' states), the controller calculates an adjustment magnitude based on two standard deviations: one for cells storing '1' and another for cells storing '0'. These standard deviations represent the expected spread of threshold voltages for each data state. By comparing these values, the controller determines how much to adjust the read bias to maintain optimal separation between the distributions, improving read accuracy. This adaptive approach accounts for variations in memory cell characteristics and wear, allowing the controller to compensate for shifts in threshold voltage distributions that occur during memory cell aging. The technique helps prevent read errors by dynamically adjusting the read reference voltage based on statistical analysis of the current distribution characteristics.
12. The memory controller of claim 11 , wherein the control circuit determines the first standard deviation and the second standard deviation from among a plurality of standard deviations included in an expected standard deviation group based on a program-erase count of the target memory cells, a retention time of the target memory cells, or both.
Solid state memory device, specifically a memory controller, and method of operation. The technology addresses variability in memory cell behavior, which can lead to data retention issues. The problem is to dynamically adjust read operations to compensate for these variations and improve data reliability. This invention pertains to a memory controller that includes a control circuit. The control circuit is configured to manage the reading of data from memory cells. In particular, it determines a first standard deviation and a second standard deviation. These standard deviations are selected from a group of expected standard deviations. The selection is made based on specific characteristics of the target memory cells being accessed. These characteristics include the program-erase count of the memory cells, which indicates wear and tear, and/or the retention time, which reflects how long data is expected to remain reliably stored. By dynamically choosing appropriate standard deviations based on these cell conditions, the memory controller can optimize read parameters to enhance data integrity and mitigate the effects of cell degradation.
13. A method of operating a memory system, the method comprising: successfully performing Error Correcting Code (ECC) decoding on read data read from a plurality of target memory cells included in a memory device; and in response to the ECC decoding succeeding: determining whether to update one or more read biases used for reading data programmed in the plurality of target memory cells, and in response to determining to update the one or more read biases, updating a read bias of the one or more read biases based on information regarding: i) result data generated by the ECC decoding and ii) a number data bits corrected during the ECC decoding, wherein updating of the read bias comprises determining a direction in which the read bias is updated based on a first fail bit rate and a second fail bit rate, when updating the read bias.
This technical summary describes a method for operating a memory system to improve data reliability by dynamically adjusting read biases. The method addresses the problem of read errors in memory devices, particularly in non-volatile memory like flash storage, where data degradation over time can lead to increased error rates. The solution involves performing Error Correcting Code (ECC) decoding on read data from target memory cells. If the ECC decoding succeeds, the method evaluates whether to update the read biases used for reading the data. The decision to update is based on the ECC decoding results, including the corrected data and the number of bits corrected. When updating the read bias, the direction of adjustment is determined by comparing a first fail bit rate (e.g., before adjustment) with a second fail bit rate (e.g., after adjustment). This adaptive approach helps optimize read operations by reducing error rates and improving data integrity over time. The method ensures that read biases are dynamically adjusted to account for variations in memory cell characteristics, enhancing overall system reliability.
14. The method of claim 13 , wherein updating of the read bias comprises: determining the first fail bit rate as a ratio of the number of data bits having a value of 1 among the result data to the number of data bits having a value corrected from 0 to 1 during the ECC decoding, and determining the second fail bit rate as a ratio of the number of data bits having a value of 0 among the result data to the number of data bits having a value corrected from 1 to 0 during the ECC decoding.
In the field of memory storage systems, particularly non-volatile memory such as flash memory, data integrity is critical. Over time, read errors occur due to factors like wear, charge leakage, or noise, requiring error correction techniques. However, traditional error correction codes (ECC) may not account for read bias, which can lead to inefficient error correction and reduced reliability. This invention addresses the problem by dynamically adjusting read bias in memory storage systems based on fail bit rates. The method involves reading data from a memory cell and performing ECC decoding to correct errors. During this process, the system determines two fail bit rates: the first fail bit rate is calculated as the ratio of data bits originally read as 1 to the number of bits corrected from 0 to 1 during ECC decoding. The second fail bit rate is the ratio of data bits originally read as 0 to the number of bits corrected from 1 to 0. These fail bit rates are used to update the read bias, optimizing the read operation for improved accuracy and reliability. The method ensures that the read bias is adjusted based on actual error patterns, enhancing the overall performance and longevity of the memory system.
15. The method of claim 14 , wherein updating of the read bias comprises determining a magnitude by which the read bias is updated based on a first standard deviation and a second standard deviation when updating the read bias, wherein the first standard deviation is an expected standard deviation for a threshold voltage distribution of a memory cell having a value of 1 among the target memory cells, and wherein the second standard deviation is an expected standard deviation for a threshold voltage distribution of a memory cell having a value of zero among the target memory cells.
This invention relates to memory systems, specifically to methods for adjusting read bias in non-volatile memory cells to improve read accuracy. The problem addressed is the variability in threshold voltage distributions of memory cells, which can lead to read errors when the read bias is not properly aligned with the actual distribution of cell voltages. The invention provides a method to dynamically update the read bias based on statistical properties of the memory cells' threshold voltage distributions. The method involves determining a magnitude for updating the read bias by analyzing two standard deviations: the first standard deviation corresponds to the expected spread of threshold voltages for memory cells storing a value of 1, while the second standard deviation corresponds to the expected spread for memory cells storing a value of 0. By comparing these standard deviations, the system calculates an appropriate adjustment to the read bias to minimize read errors. This approach ensures that the read bias is optimized for the current state of the memory cells, accounting for variations in their threshold voltage distributions over time. The method may be applied during read operations to maintain accurate data retrieval as the memory cells degrade or experience environmental changes.
16. The method of claim 15 , wherein updating of the read bias comprises determining the first standard deviation and the second standard deviation from among a plurality of standard deviations included in an expected standard deviation group based on a program-erase count of the target memory cells, a retention time of the target memory cells, or both.
This invention relates to memory storage systems, specifically to methods for adjusting read bias in non-volatile memory devices to improve data accuracy. The problem addressed is the degradation of stored data over time due to factors like program-erase cycles and retention time, which affect the reliability of read operations. The invention provides a method to dynamically update read bias by analyzing statistical variations in memory cell behavior. The method involves determining a first standard deviation and a second standard deviation from a group of expected standard deviations. These standard deviations are selected based on the program-erase count of the target memory cells, the retention time of the target memory cells, or both. The program-erase count refers to the number of times the memory cells have been programmed and erased, which impacts their wear and reliability. The retention time refers to the duration for which data has been stored in the memory cells, which affects data retention integrity. By using these factors, the method adjusts the read bias to compensate for variations in memory cell behavior, thereby improving read accuracy and reducing errors. The expected standard deviation group includes multiple standard deviations that represent different levels of variability in memory cell behavior under varying conditions. The method selects the appropriate standard deviations from this group to fine-tune the read bias, ensuring optimal performance across different memory states. This approach enhances the reliability of data retrieval in non-volatile memory devices, particularly in environments where memory cells are subject to frequent program-erase cycles or long-term data storage.
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May 15, 2020
February 1, 2022
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