Interconnect structures and methods for forming the interconnect structures generally include a subtractive etching process to form a fully aligned top via and metal line interconnect structure. The interconnect structure includes a top via and a metal line formed of an alternative metal other than copper or tungsten. A conductive etch stop layer is intermediate the top via and the metal line. The top via is fully aligned to the metal line.
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1. A method of forming an interconnect structure, the method comprising: forming a metal stack on a substrate, wherein the metal stack comprises an alternative metal other than copper or tungsten; forming a line pattern from a mandrel deposited on the metal stack, the mandrel comprising a height dimension greater than a width dimension; forming a spacer on sidewalls of the mandrel line pattern, wherein gaps remain between adjacent sidewall spacers; filling the gaps between the adjacent sidewall spacers with a non-mandrel material to form a non-mandrel line pattern; forming via openings in the mandrel line pattern and the non-mandrel line pattern; filling the via openings with a fill material; selectively removing the sidewall spacers to expose portions of the metal stack between the mandrel line pattern and the non-mandrel line pattern; selectively etching the exposed portions of the metal stack to a depth corresponding to a desired via height; selectively removing the mandrel and the non-mandrel line patterns; etching the metal stack to the substrate to form the interconnect structure comprising a plurality of metal lines with fully aligned top vias formed of the alternative metal under the fill material; and removing the fill material.
This invention relates to semiconductor interconnect fabrication, specifically addressing challenges in forming high-density, fully aligned metal lines and vias using alternative metals like cobalt or ruthenium instead of traditional copper or tungsten. The method involves depositing a metal stack containing the alternative metal on a substrate. A mandrel line pattern is formed on the metal stack, with the mandrel having a height greater than its width. Sidewall spacers are then deposited on the mandrel, leaving gaps between adjacent spacers. These gaps are filled with a non-mandrel material to create a non-mandrel line pattern. Via openings are formed in both the mandrel and non-mandrel patterns, which are subsequently filled with a fill material. The sidewall spacers are selectively removed, exposing portions of the metal stack. These exposed portions are etched to a depth matching the desired via height. The mandrel and non-mandrel patterns are then removed, followed by etching the metal stack down to the substrate to form the interconnect structure. This results in metal lines with fully aligned top vias made of the alternative metal, which are then covered by the fill material. Finally, the fill material is removed, completing the interconnect structure. The process enables precise alignment and high-density interconnects using alternative metals, addressing limitations in traditional copper or tungsten-based fabrication.
2. The method of claim 1 , wherein the substrate comprises an interlayer dielectric including an underlying interconnect structure, or one or more front end of line devices, or a middle of the line contact structure, wherein the metal lines are electrically coupled thereto.
This invention relates to semiconductor fabrication, specifically methods for forming metal lines on a substrate. The problem addressed is the need for precise and reliable electrical connections between metal lines and underlying structures in integrated circuits. The method involves depositing a metal layer over a substrate, where the substrate includes either an interlayer dielectric with an underlying interconnect structure, front-end-of-line (FEOL) devices, or a middle-of-line (MOL) contact structure. The metal layer is then patterned to form metal lines that are electrically coupled to these underlying structures. The patterning may involve etching or other selective removal techniques to define the metal lines. The invention ensures proper electrical connectivity between the metal lines and the substrate's components, which is critical for device performance and reliability. The method is applicable to various stages of semiconductor manufacturing, including back-end-of-line (BEOL) processing, where interconnects are formed to connect different device layers. The technique helps mitigate issues like poor contact resistance or misalignment, which can degrade circuit functionality. The invention is particularly useful in advanced semiconductor nodes where precise patterning and reliable interconnects are essential for high-performance devices.
3. The method of claim 1 , wherein the alternative metal comprises ruthenium, iridium, rhodium, molybdenum, cobalt, aluminum, combinations thereof, or alloys thereof.
This invention relates to the field of semiconductor manufacturing, specifically to the use of alternative metals in the fabrication of integrated circuits. The problem addressed is the need for improved conductivity and reliability in semiconductor devices, particularly in interconnect structures, where traditional metals like copper may face limitations in performance or compatibility with advanced fabrication processes. The invention describes a method for incorporating alternative metals into semiconductor devices to enhance electrical conductivity and structural integrity. The alternative metals include ruthenium, iridium, rhodium, molybdenum, cobalt, aluminum, or combinations and alloys thereof. These metals are selected for their superior properties, such as high melting points, resistance to electromigration, and compatibility with advanced semiconductor materials. The method involves depositing these metals into interconnect structures, such as vias, trenches, or contact pads, to improve device performance and reliability. The use of these alternative metals addresses challenges in scaling down semiconductor devices, where traditional materials may not provide sufficient conductivity or durability. By integrating these metals, the invention enables the fabrication of high-performance, reliable semiconductor devices suitable for advanced applications. The method ensures proper adhesion, uniformity, and electrical properties, making it compatible with existing semiconductor manufacturing processes.
4. The method of claim 1 , wherein the metal stack comprises a conductive etch stop layer between a first metal layer and a second metal layer, wherein the second metal layer is on the first metal layer, wherein the second metal layer corresponds to the via height and the first metal layer corresponds to a metal line height.
This invention relates to semiconductor manufacturing, specifically to the formation of metal interconnect structures in integrated circuits. The problem addressed is controlling the etching process to ensure precise formation of vias and metal lines while preventing over-etching or under-etching, which can degrade electrical performance and reliability. The invention describes a metal stack structure with a conductive etch stop layer positioned between a first metal layer and a second metal layer. The second metal layer is deposited on top of the first metal layer. The second metal layer is designed to correspond to the height of a via, while the first metal layer corresponds to the height of a metal line. The conductive etch stop layer serves as a barrier during the etching process, allowing selective removal of material while protecting underlying layers. This ensures accurate via formation without damaging the metal line structure. The conductive etch stop layer also maintains electrical conductivity between the via and the metal line, preventing signal degradation. The invention improves manufacturing yield and reliability by providing precise control over the etching process in semiconductor fabrication.
5. The method of claim 4 , wherein the conductive etch stop layer comprises titanium, cobalt, tantalum, rhodium, tungsten, combinations thereof, or alloys thereof.
This invention relates to semiconductor manufacturing, specifically to methods for forming conductive features with improved etch selectivity. The problem addressed is achieving precise etching of conductive materials while preventing damage to underlying layers during the fabrication of integrated circuits. The invention describes a method for forming conductive features where a conductive etch stop layer is used to control the etching process. This etch stop layer is composed of materials that can withstand the etching conditions while allowing selective removal of overlying conductive layers. The conductive etch stop layer includes titanium, cobalt, tantalum, rhodium, tungsten, or combinations and alloys thereof. These materials are chosen for their resistance to etchants used in the process, ensuring that the underlying layers remain intact. The method involves depositing the conductive etch stop layer between conductive layers, such as copper or other metals, and then selectively etching the upper conductive layer without affecting the etch stop layer. This selective etching allows for precise patterning of conductive features, improving the reliability and performance of semiconductor devices. The use of these specific conductive materials as etch stop layers enhances process control and reduces defects in advanced semiconductor manufacturing.
6. The method of claim 4 further comprising anisotropically etching to selectively remove the etch stop layer subsequent to selectively etching the exposed portions of the metal stack.
This invention relates to semiconductor fabrication, specifically to a method for selectively etching layers in a metal stack structure. The problem addressed is the precise removal of an etch stop layer after selectively etching exposed portions of a metal stack, ensuring accurate patterning without damaging underlying layers. The method involves anisotropically etching to selectively remove the etch stop layer after the exposed portions of the metal stack have been etched. The etch stop layer serves as a protective barrier during the initial etching of the metal stack, preventing over-etching into underlying layers. After the metal stack is patterned, the etch stop layer is removed using an anisotropic etch process, which etches vertically without significantly undercutting adjacent structures. This ensures precise control over the etching process, maintaining the integrity of the patterned metal stack and the underlying layers. The anisotropic etch process is highly selective, meaning it preferentially removes the etch stop layer material while minimizing damage to the metal stack or other adjacent materials. This selectivity is achieved through careful control of etch parameters, such as gas composition, pressure, and plasma conditions. The method ensures that the etch stop layer is completely removed from the desired areas, leaving a clean and well-defined metal stack structure. This technique is particularly useful in advanced semiconductor manufacturing, where precise patterning of metal layers is critical for device performance and reliability. By using an etch stop layer and subsequent anisotropic etching, the method enables high-precision fabrication of complex metal interconnect structures.
7. The method of claim 1 , wherein the mandrel and the non-mandrel line patterns are etch selective relative to the fill material, the sidewall spacers, and the metal stack.
The invention relates to semiconductor manufacturing, specifically to a method for fabricating integrated circuits with improved pattern fidelity and etch selectivity. The method addresses challenges in etching complex patterns, particularly when using mandrel-based patterning techniques, where maintaining selectivity between different materials is critical to avoid unintended etching and pattern distortion. The method involves forming a mandrel and non-mandrel line patterns on a substrate, where these patterns are selectively etchable relative to a fill material, sidewall spacers, and a metal stack. The mandrel and non-mandrel patterns are initially formed using a sacrificial mandrel structure, which is later removed to leave behind the desired non-mandrel lines. The fill material temporarily fills gaps between the mandrel and non-mandrel lines, while sidewall spacers are formed adjacent to the mandrel to define the final pattern dimensions. The metal stack, which may include conductive layers, is deposited and patterned to form electrical connections. The key innovation is the etch selectivity between the mandrel and non-mandrel patterns and the other materials (fill material, sidewall spacers, and metal stack). This ensures that during etching steps, only the intended structures are removed, preventing damage to adjacent features. The method enables precise patterning of high-density interconnects and other semiconductor structures with minimal defects, improving yield and performance in advanced integrated circuits.
8. The method of claim 1 further comprising depositing a hardmask on the mandrel prior to forming the mandrel line pattern; and patterning the hardmask to lithographically form the mandrel line pattern.
This invention relates to semiconductor manufacturing, specifically a method for forming fine pitch patterns using a mandrel-based lithography technique. The problem addressed is the difficulty in achieving high-resolution patterns with conventional lithography due to optical limitations, particularly for advanced node semiconductor devices. The method involves forming a mandrel line pattern on a substrate, where the mandrel is a temporary structure used to define the final pattern. The mandrel is formed by depositing a hardmask layer on the mandrel material before patterning. The hardmask is then lithographically patterned to define the mandrel line pattern, which serves as a template for subsequent etching or deposition steps. This approach improves pattern fidelity and resolution by leveraging the hardmask as an intermediate layer, enhancing the precision of the mandrel formation. The mandrel line pattern is used to create spacers or other structures in subsequent steps, which are then transferred into underlying layers. The hardmask ensures accurate pattern transfer, reducing defects and improving uniformity. This technique is particularly useful for self-aligned multiple patterning (SAMP) or spacer-based patterning, where high-resolution features are required beyond the capabilities of single-exposure lithography. The method enables the fabrication of dense, high-precision patterns for advanced semiconductor devices, such as logic or memory chips.
9. The method of claim 1 , wherein selectively etching the exposed portions of the metal stack to the depth corresponding to the desired via height comprises a time-based etching process.
A method for fabricating semiconductor devices involves forming a metal stack on a substrate, where the metal stack includes multiple conductive layers. The method addresses the challenge of precisely controlling via height during etching to ensure reliable electrical connections in integrated circuits. The process begins by depositing a metal stack, which may include layers such as copper, aluminum, or other conductive materials, on a substrate. A patterned mask is then applied to the metal stack to define regions where vias will be formed. The exposed portions of the metal stack are selectively etched to a specific depth, corresponding to the desired via height. This etching is performed using a time-based etching process, where the etching duration is carefully controlled to achieve the precise depth required for the via. The time-based approach ensures that the etching stops at the correct depth, preventing over-etching or under-etching, which could compromise device performance. The method may also include additional steps such as cleaning the etched surface or depositing additional materials to complete the via formation. The resulting structure provides accurate via heights, improving electrical connectivity and reliability in semiconductor devices.
10. The method of claim 1 further comprising depositing a conductive liner layer on the substrate prior to forming the metal stack.
A method for fabricating semiconductor devices addresses the challenge of improving electrical conductivity and adhesion in integrated circuits. The process involves forming a metal stack on a substrate, where the metal stack includes at least one metal layer. To enhance performance, a conductive liner layer is deposited on the substrate before forming the metal stack. This liner layer serves as a barrier to prevent diffusion of metal atoms into the substrate, ensuring reliable device operation. Additionally, it improves adhesion between the metal stack and the substrate, reducing the risk of delamination. The liner layer may be composed of materials such as titanium, tantalum, or their nitrides, which are known for their conductive properties and compatibility with semiconductor manufacturing processes. The metal stack itself may include layers of copper, aluminum, or other conductive metals, depending on the specific application. This method is particularly useful in advanced semiconductor nodes where minimizing resistance and ensuring long-term reliability are critical. By incorporating the conductive liner layer, the method improves both the electrical and mechanical integrity of the fabricated devices.
11. A subtractive etching method to form a fully aligned top via and metal line interconnect structure, the method comprising: providing a metal stack on a substrate, the metal stack comprising a conductive liner layer, a first alternative metal on the conductive liner layer, a conductive etch stop layer on the first alternative metal layer, and a second alternative metal layer on the conductive etch stop layer, wherein the second alternative metal layer has a height equal to a desired top via height and first alternative metal layer has a height equal to a desired metal line height; depositing and patterning a mandrel layer on the metal stack to form a plurality of mandrel lines, the mandrel comprising a height dimension greater than a width dimension; depositing a sidewall spacer onto the mandrel lines, wherein gaps remain between adjacent sidewall spacers; filling the gaps between the adjacent sidewall spacers with a non-mandrel material to form non-mandrel lines; patterning the mandrel lines and non-mandrel lines to form via openings to the second alternative metal layer in the metal stack; filling the via openings with a fill material having etch selectivity relative to the mandrel lines, non-mandrel lines, metal stack, and sidewall spacers; selectively removing the sidewall spacers to expose portions of the second alternative metal layer of the metal stack; etching the exposed portions of the second alternative metal layer to the conductive etch stop layer; selectively removing the mandrel lines, the non-mandrel lines, and exposed portions of the etch stop layer; etching exposed portions of the first alternative metal layer and the liner layer to the substrate; selectively removing the fill material to form the interconnect structure comprising the fully aligned top via of the second alternative metal and the metal line of the first alternative metal.
This invention relates to a subtractive etching method for forming a fully aligned top via and metal line interconnect structure in semiconductor manufacturing. The method addresses challenges in achieving precise alignment between vias and metal lines, which is critical for high-performance integrated circuits. The process begins with a metal stack on a substrate, comprising a conductive liner layer, a first alternative metal layer for the metal line, a conductive etch stop layer, and a second alternative metal layer for the via. The heights of these layers are precisely controlled to match the desired via and metal line dimensions. A mandrel layer is deposited and patterned into mandrel lines with a height greater than their width. Sidewall spacers are formed around these mandrel lines, leaving gaps between adjacent spacers. The gaps are filled with a non-mandrel material to create non-mandrel lines. Via openings are then patterned through the mandrel and non-mandrel lines to expose the second alternative metal layer. These openings are filled with a material that has etch selectivity relative to the surrounding layers. The sidewall spacers are selectively removed, exposing portions of the second alternative metal layer, which are then etched down to the conductive etch stop layer. The mandrel lines, non-mandrel lines, and exposed etch stop layer are removed, followed by etching the first alternative metal layer and liner layer to the substrate. Finally, the fill material is removed, resulting in a fully aligned interconnect structure with a top via formed from the second alternative metal and a metal line from the first alternative metal. This method ensures precise alignment and reduces misalignment issues in advanced semiconductor fabrication.
12. The method of claim 11 , wherein the first and second alternative metal layers are free from copper and tungsten and comprise ruthenium, iridium, rhodium, molybdenum, cobalt, aluminum, combinations thereof, or alloys thereof.
This invention relates to semiconductor manufacturing, specifically to the formation of metal interconnect structures in integrated circuits. The problem addressed is the need for alternative metal layers that avoid the use of copper and tungsten, which can suffer from issues such as electromigration, high resistivity, or compatibility challenges with advanced fabrication processes. The solution involves using first and second alternative metal layers composed of materials like ruthenium, iridium, rhodium, molybdenum, cobalt, aluminum, or their combinations and alloys. These layers are deposited in a manner that ensures reliable electrical connectivity while mitigating the drawbacks of traditional metals. The method includes forming a conductive via or trench in a dielectric layer, depositing a barrier layer, and then sequentially depositing the first and second alternative metal layers. The first layer may be deposited using a conformal deposition technique, while the second layer is deposited to fill the remaining volume. The alternative metals provide improved adhesion, lower resistivity, and better compatibility with advanced semiconductor processes compared to copper and tungsten. This approach is particularly useful for high-density interconnects in advanced nodes where traditional metals may not meet performance or reliability requirements.
13. The method of claim 11 , wherein the conductive etch stop layer comprises titanium, cobalt, tantalum, rhodium, tungsten, combinations thereof, or alloys thereof.
This invention relates to semiconductor manufacturing, specifically to the formation of conductive etch stop layers in integrated circuits. The problem addressed is the need for reliable etch stop materials that prevent over-etching during semiconductor fabrication while maintaining electrical conductivity. Traditional etch stop layers often use insulating materials, which disrupt electrical pathways, or conductive materials that lack sufficient etch selectivity. The invention describes a method for fabricating a semiconductor device that includes depositing a conductive etch stop layer composed of titanium, cobalt, tantalum, rhodium, tungsten, or combinations and alloys thereof. This layer serves as a barrier during etching processes, allowing precise control over material removal while preserving electrical connectivity. The conductive etch stop layer is integrated into the device structure, typically between conductive layers or adjacent to active regions, to prevent unintended etching of underlying materials. The use of these specific metals ensures high etch selectivity, thermal stability, and compatibility with standard semiconductor processing techniques. The method may also involve patterning the conductive etch stop layer and subsequent deposition of additional conductive or insulating layers to complete the device. This approach improves manufacturing yield and device performance by minimizing defects caused by over-etching while maintaining electrical functionality.
14. The method of claim 11 , wherein the substrate comprises an interlayer dielectric including an underlying interconnect structure, or one or more devices, or a middle of the line contact or plug structure, wherein the metal lines are electrically coupled thereto.
This invention relates to semiconductor manufacturing, specifically methods for forming metal interconnect structures in integrated circuits. The problem addressed is the need for improved electrical connectivity and structural integrity in advanced semiconductor devices, particularly in the middle-of-line (MOL) and back-end-of-line (BEOL) stages. The method involves depositing a metal layer over a substrate, where the substrate includes an interlayer dielectric (ILD) with an underlying interconnect structure, one or more semiconductor devices, or a middle-of-line contact or plug structure. The metal layer is patterned to form metal lines that are electrically coupled to these underlying features. The process ensures reliable electrical connections while maintaining structural stability in the semiconductor device. The metal lines are formed by depositing a metal layer, such as copper or aluminum, over the substrate. The metal layer is then patterned using lithography and etching techniques to define the desired interconnect lines. The patterned metal lines are electrically connected to the underlying interconnect structure, devices, or MOL contacts, enabling signal transmission and power distribution within the integrated circuit. The method ensures proper alignment and adhesion between the metal lines and the substrate, reducing defects and improving device performance. This approach is particularly useful in advanced semiconductor nodes where precise interconnect formation is critical for high-performance and high-density integrated circuits. The method enhances electrical connectivity while maintaining mechanical stability, addressing challenges in modern semiconductor fabrication.
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April 6, 2020
February 8, 2022
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