Patentable/Patents/US-11249512
US-11249512

Frequency execution monitoring in a real-time embedded system

PublishedFebruary 15, 2022
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method includes reading first and second timer count values from a timer. The first timer count value is associated with a first time point, and the second timer count value is associated with a second time point. Also, the method includes calculating a difference between the first and the second timer count values, and determining whether the difference is within a range. The range is based on a desired executing frequency to perform a computing task, a variation of the desired executing frequency, and a timer frequency. Further, based on the difference not being within the range, the method includes setting an error flag value to be true and incrementing an error count value.

Patent Claims
6 claims

Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.

Claim 1

Original Legal Text

1. A system comprising: a storage device containing executable instructions to monitor a frequency at which a task of a real time operating system is performed; and a processing resource coupled to the storage device to execute the executable instructions to: determine a first time associated with a first execution of the task and determine a second time associated with a second execution of the task; calculate a time difference between the first time and the second time; determine whether the time difference is in a fixed range; set an error flag to be true when the time difference is not within the fixed range or set the error flag to be false when the time difference is within the fixed range; and a timer coupled to the processing resource, wherein the timer is configured to count pulses of a clock signal and to generate output count values from which the first and second times are determined.

Plain English Translation

This invention relates to monitoring task execution timing in real-time operating systems (RTOS) to ensure deterministic behavior. Real-time systems require precise timing to meet strict deadlines, and deviations can lead to system failures. The system monitors the frequency of task execution by tracking the time between consecutive executions of a task. A storage device contains instructions for a processing resource to determine the first and second execution times of a task, calculate the time difference between them, and check if this difference falls within a predefined fixed range. If the difference is outside the range, an error flag is set to indicate a timing violation. A timer coupled to the processing resource counts clock pulses to generate precise time measurements. The system ensures that tasks execute within expected intervals, detecting anomalies that could disrupt real-time performance. This approach helps maintain system reliability by identifying timing inconsistencies early, allowing for corrective actions. The invention is particularly useful in safety-critical applications where predictable task execution is essential.

Claim 2

Original Legal Text

2. The system of claim 1 , wherein the processing resource is at least one of: (a) a single core central processing unit (CPU), (b) a multi-core CPU, or (c) a computer cluster.

Plain English Translation

This invention relates to a system for processing data using a configurable processing resource. The system addresses the challenge of efficiently handling diverse computational workloads by providing flexibility in the type of processing resource employed. The processing resource can be a single-core central processing unit (CPU), a multi-core CPU, or a computer cluster, allowing the system to adapt to different performance and scalability requirements. The system dynamically selects or configures the appropriate processing resource based on the workload characteristics, optimizing resource utilization and performance. This adaptability ensures that the system can efficiently manage tasks ranging from lightweight computations to high-performance parallel processing. The invention enhances computational efficiency by leveraging the most suitable processing architecture for the given workload, reducing latency and improving throughput. The system's modular design allows seamless integration with various processing resources, making it versatile for different applications. By supporting multiple processing configurations, the system ensures compatibility with existing and future hardware advancements, providing long-term scalability and adaptability.

Claim 3

Original Legal Text

3. The system of claim 1 , wherein the timer is a decrementing timer that counts down from a maximum count value to a minimum count value, and when the timer reaches the minimum count value, the timer transitions to the maximum count value.

Plain English Translation

A system for managing a decrementing timer in a computing environment is disclosed. The system addresses the need for precise timing control in applications where a timer must repeatedly cycle between a maximum and minimum count value without manual reset. The timer counts down from a predefined maximum count value to a minimum count value. Once the minimum count value is reached, the timer automatically resets to the maximum count value, allowing continuous operation without external intervention. This design ensures consistent timing behavior in applications such as scheduling, synchronization, or periodic task execution. The system may include additional components, such as a processor to monitor the timer's state and a memory to store the count values. The timer's cyclic behavior eliminates the need for manual resets, improving reliability and reducing computational overhead. The system is particularly useful in embedded systems, real-time applications, or any scenario requiring automated, repetitive timing cycles. The timer's operation is deterministic, ensuring predictable performance in time-sensitive processes.

Claim 4

Original Legal Text

4. A system comprising: a timer configured to count transitions of a clock signal; a storage device containing executable instructions; a processing resource coupled to the timer and to the storage device to execute the executable instructions to: determine a value representing one of (i) a ratio of a time to execute a task of a real time operating system to a count interval of the timer, or (ii) a product of a time to execute the task and the frequency of the timer; determine whether the value is within a fixed range determined based on a frequency of the timer, an execution frequency of the task, and an allowable execution frequency; and set an error flag to be true when the ratio is not within the fixed range or set the error flag to be false when the ratio is within the fixed range.

Plain English Translation

This invention relates to real-time operating systems (RTOS) and addresses the challenge of ensuring tasks execute within predictable time constraints. The system monitors task execution times to detect deviations that could disrupt system timing. A timer counts clock signal transitions, providing a reference for measuring task execution duration. A processing resource executes instructions to calculate a value representing either the ratio of task execution time to timer count interval or the product of task execution time and timer frequency. This value is compared against a predefined range, which is derived from the timer frequency, task execution frequency, and allowable execution frequency. If the value falls outside this range, an error flag is set to indicate a timing violation, signaling potential issues in task scheduling or system performance. The system ensures tasks meet real-time constraints, preventing timing-related failures in critical applications. The error flag can trigger corrective actions, such as rescheduling tasks or adjusting system parameters, to maintain system reliability. This approach enhances timing predictability in RTOS environments, particularly in embedded systems where precise timing is essential.

Claim 5

Original Legal Text

5. The system of claim 4 , wherein the processing resource is at least one of: (a) a single core central processing unit (CPU), (b) a multi-core CPU, or (c) a computer cluster.

Plain English Translation

The invention relates to a processing system designed to enhance computational efficiency and scalability. The system addresses the challenge of optimizing resource allocation in computing environments where varying workload demands require flexible processing capabilities. The core system includes a processing resource configured to execute tasks, where the resource can be dynamically adjusted based on workload requirements. This adaptability ensures efficient utilization of computational power, reducing idle time and improving overall performance. The processing resource in the system can be implemented in multiple configurations to suit different operational needs. It may be a single-core central processing unit (CPU), which provides a straightforward and cost-effective solution for tasks with moderate processing demands. Alternatively, the system can employ a multi-core CPU, enabling parallel processing to handle more complex or concurrent workloads efficiently. For large-scale or high-performance applications, the processing resource can be a computer cluster, distributing tasks across multiple interconnected nodes to achieve higher throughput and scalability. By offering these configurable options, the system ensures compatibility with a wide range of applications, from small-scale tasks to large-scale distributed computing. The flexibility in processing resource selection allows users to tailor the system to their specific needs, optimizing performance and resource usage. This adaptability is particularly valuable in environments where workloads vary significantly over time, ensuring consistent and efficient operation.

Claim 6

Original Legal Text

6. A method comprising: determining, by a processing resource, a first time associated with a first execution of a task of a real time operating system and a second time associated with a second execution of the task; calculating a time difference between the first time and the second time; determining whether the time difference is in a fixed range; setting an error flag to be true when the time difference is not within the fixed range or setting the error flag to be false when the time difference is within the fixed range; and counting pulses of a clock signal and to generate output count values from which the first and second times are determined.

Plain English Translation

This invention relates to real-time operating systems (RTOS) and addresses the challenge of ensuring predictable task execution timing. In RTOS environments, tasks must execute within strict temporal constraints to maintain system reliability. The invention provides a method to monitor and verify task execution timing by comparing the execution times of consecutive instances of a task. A processing resource measures the first and second execution times of a task and calculates the time difference between them. The system then checks whether this difference falls within a predefined fixed range. If the difference exceeds the range, an error flag is set to true, indicating a timing violation; otherwise, the flag remains false. The method also involves counting pulses from a clock signal to generate precise time measurements for the execution times. This approach enables real-time systems to detect deviations from expected task timing, ensuring system stability and reliability. The invention is particularly useful in safety-critical applications where timing consistency is essential.

Classification Codes (CPC)

Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.

Patent Metadata

Filing Date

July 29, 2019

Publication Date

February 15, 2022

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Frequency execution monitoring in a real-time embedded system