A data transfer circuit includes: a one-time PROM storing first to m-th register addresses and first to m-th register data; first to n-th registers holding first to n-th data corresponding to first to n-th parameters controlling an operation of a functional element; and a data transfer control circuit acquiring the i-th register address and the i-th register data from the one-time PROM, transferring the i-th register data to the k-th register designated by the i-th register address, k being an integer equal to or greater than 1 and equal to or smaller than n, and updating the k-th data with the i-th register data.
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1. A data transfer circuit comprising: a one-time programmable read-only memory (PROM) storing first to m-th register addresses and first to m-th register data, m being an integer equal to or greater than 1; first to n-th registers holding first to n-th data corresponding to first to n-th parameters controlling an operation of a functional element, n being an integer equal to or greater than 2; and a data transfer control circuit acquiring, with respect to each integer i equal to or greater than 1 and equal to or smaller than m, the i-th register address and the i-th register data from the one-time PROM, transferring the i-th register data to the k-th register designated by the i-th register address, k being an integer equal to or greater than 1 and equal to or smaller than n, and updating the k-th data with the i-th register data.
This invention relates to data transfer circuits for controlling functional elements. The problem addressed is efficiently configuring the parameters of a functional element. The circuit includes a one-time programmable read-only memory (PROM). This PROM stores a set of register addresses and corresponding register data. The number of address-data pairs stored is denoted by 'm', where 'm' is at least one. The circuit also comprises multiple registers, from the first to the n-th register. These registers hold data that corresponds to parameters controlling the operation of a functional element. The number of these registers is denoted by 'n', where 'n' is at least two. A data transfer control circuit is responsible for managing the data flow. For each stored address-data pair in the PROM (from the first to the m-th pair), the control circuit retrieves the i-th register address and the i-th register data. It then transfers the i-th register data to a specific register. The target register is identified by the i-th register address, which points to a register 'k' within the range of 1 to 'n'. Finally, the data stored in the k-th register is updated with the transferred i-th register data. This allows for the programmable configuration of functional element parameters stored in the registers using data from the PROM.
2. The data transfer circuit according to claim 1 , wherein the one-time PROM stores first to n-th initial data which are initial values of the first to n-th parameters, and the data transfer control circuit transfers the i-th register data to the k-th register after acquiring the first to n-th initial data from the one-time PROM and transferring the first to n-th initial data to the first to n-th registers.
This invention relates to a data transfer circuit for initializing and managing parameter values in a system. The circuit addresses the need for reliable and secure initialization of system parameters, particularly in applications where parameter values must be set once and cannot be altered afterward. The circuit includes a one-time programmable read-only memory (OTP PROM) that stores initial values for multiple parameters, ensuring these values are fixed after programming. The OTP PROM contains first to n-th initial data, which are the initial values for first to n-th parameters. A data transfer control circuit retrieves these initial values from the OTP PROM and transfers them to corresponding first to n-th registers. After initialization, the circuit transfers data from an i-th register to a k-th register, enabling dynamic parameter adjustments while maintaining the integrity of the initial values stored in the OTP PROM. This design ensures secure and tamper-proof parameter initialization, which is critical for applications requiring high reliability, such as embedded systems, security modules, or configuration management in electronic devices. The circuit's ability to transfer data between registers after initialization allows for flexible parameter management while preserving the original initial values.
3. The data transfer circuit according to claim 1 , wherein the data transfer control circuit transfers the i-th register data to the k-th register after first to n-th initial data which are initial values of the first to n-th parameters are loaded in parallel to the first to n-th registers.
This invention relates to a data transfer circuit designed for efficient parameter initialization and data transfer in digital systems. The circuit addresses the challenge of initializing multiple registers with initial parameter values and subsequently transferring data between registers in a controlled manner. The circuit includes a data transfer control circuit that manages the loading of initial values into a set of registers and the subsequent transfer of data between them. Specifically, the control circuit first loads initial values for n parameters in parallel into n registers. After initialization, the control circuit transfers the data stored in the i-th register to the k-th register, enabling flexible and efficient data movement within the system. This approach ensures rapid initialization and precise data transfer, improving performance in applications requiring frequent parameter updates or dynamic data routing. The circuit is particularly useful in digital signal processing, control systems, and other domains where parameter management and data transfer efficiency are critical.
4. The data transfer circuit according to claim 1 , wherein the one-time PROM stores predetermined data, the data transfer control circuit determines that transfer of the first to m-th register data is finished, on acquiring the predetermined data from the one-time PROM.
This invention relates to a data transfer circuit designed for secure and efficient data handling, particularly in systems requiring one-time programmable (OTP) memory. The circuit addresses the challenge of ensuring reliable data transfer while minimizing power consumption and circuit complexity. The core functionality involves a data transfer control circuit that manages the movement of data between registers and a one-time programmable read-only memory (PROM). The one-time PROM stores predetermined data, which serves as a trigger for the control circuit. When the control circuit detects that the predetermined data has been acquired from the one-time PROM, it concludes that the transfer of data from the first to the m-th register is complete. This mechanism ensures that data transfer operations are accurately tracked and terminated upon reaching a predefined state, enhancing system reliability. The circuit is particularly useful in applications where data integrity and controlled transfer are critical, such as in embedded systems, secure storage devices, or firmware updates. The use of a one-time PROM ensures that the predetermined data is immutable, preventing unauthorized modifications and ensuring the integrity of the transfer process. The overall design optimizes power efficiency by avoiding unnecessary data transfers once the predetermined condition is met.
5. The data transfer circuit according to claim 1 , wherein an address of an area where the i-th register address is stored and an address of an area where the i-th register data is stored, in the one-time PROM, are different from each other.
This invention relates to a data transfer circuit designed for use with a one-time programmable read-only memory (OTP PROM). The circuit addresses the challenge of efficiently managing register addresses and data storage in OTP PROMs, where data can only be written once. The invention ensures that the address of the storage area for a register address and the address of the storage area for the corresponding register data are distinct within the OTP PROM. This separation prevents conflicts and ensures reliable data retrieval. The circuit includes a register address storage area and a register data storage area, each with unique addresses, allowing for independent access and modification. The design supports multiple registers, where each register's address and data are stored in separate locations. This approach enhances data integrity and simplifies memory management in systems using OTP PROMs, particularly in applications where write-once memory is required. The invention is useful in embedded systems, microcontrollers, and other devices where secure and efficient data storage is critical.
6. The data transfer circuit according to claim 1 , wherein an address of an area where the i-th register address is stored and an address of an area where the i-th register data is stored in the one-time PROM are the same.
A data transfer circuit is designed to improve efficiency in systems using one-time programmable read-only memory (OTP PROM) by optimizing address management. The circuit addresses the challenge of storing both register addresses and corresponding register data in OTP PROM, which traditionally requires separate memory locations for each, increasing storage overhead and complexity. The invention ensures that the address of the storage area for the i-th register address and the address of the storage area for the i-th register data in the OTP PROM are identical. This means a single memory location is used to store both the address and the data for each register, reducing memory usage and simplifying access operations. The circuit likely includes logic to distinguish between address and data storage within the same memory location, enabling efficient retrieval and transfer of register information. This approach minimizes the physical space required in the OTP PROM and streamlines data handling, particularly in embedded systems or applications where memory resources are constrained. The invention enhances performance by reducing the number of memory accesses needed to retrieve both address and data, improving overall system efficiency.
7. The data transfer circuit according to claim 1 , wherein the functional element is a resonator element, the data transfer circuit has an oscillation circuit oscillating the resonator element, and one of the first to n-th parameters is a temperature compensation parameter for the oscillation circuit, and another one of the first to n-th parameters is a frequency adjustment parameter for the oscillation circuit.
This invention relates to a data transfer circuit incorporating a resonator element, such as a crystal oscillator, used in electronic systems requiring precise timing or frequency control. The circuit includes an oscillation circuit that drives the resonator element to generate a stable output frequency. A key challenge in such systems is maintaining accuracy under varying environmental conditions, particularly temperature fluctuations, which can drift the oscillator's frequency. Additionally, fine-tuning the output frequency to match specific system requirements is often necessary. The data transfer circuit addresses these issues by incorporating multiple adjustable parameters, including a temperature compensation parameter and a frequency adjustment parameter. The temperature compensation parameter dynamically adjusts the oscillation circuit to counteract thermal drift, ensuring stable frequency output across temperature variations. The frequency adjustment parameter allows for precise calibration of the oscillator's output frequency to meet exact system specifications. These parameters are part of a broader set of configurable parameters (first to n-th) that enable flexible tuning of the circuit's performance. The resonator element, typically a crystal or MEMS device, is driven by the oscillation circuit, which may include feedback loops or phase-locked loops to enhance stability. The circuit's design ensures reliable data transfer by maintaining accurate timing signals, critical for applications like telecommunications, computing, and instrumentation.
8. An electronic component comprising: the data transfer circuit according to claim 1 ; and the functional element.
This invention relates to electronic components designed for efficient data transfer and processing. The component includes a data transfer circuit and a functional element. The data transfer circuit is configured to receive input data, process it through a series of operations, and output the processed data. These operations may include filtering, amplification, or modulation, depending on the application. The functional element is connected to the data transfer circuit and performs specific tasks such as signal processing, data storage, or control functions. The component is structured to ensure seamless interaction between the data transfer circuit and the functional element, optimizing performance and reducing latency. This design is particularly useful in high-speed communication systems, digital signal processing, and embedded systems where efficient data handling is critical. The invention addresses the need for integrated circuits that can handle complex data operations while maintaining low power consumption and high reliability. The component's modular architecture allows for customization based on specific application requirements, making it adaptable to various electronic devices and systems.
9. An electronic apparatus comprising: the electronic component according to claim 8 ; and a processing circuit operating based on an output signal from the electronic component.
The invention relates to an electronic apparatus incorporating an electronic component designed to detect or process signals, along with a processing circuit that operates based on the output signal from this component. The electronic component itself includes a sensor or detector configured to generate an output signal in response to an input stimulus, such as environmental changes, physical interactions, or electrical inputs. The processing circuit receives this output signal and performs computations, analysis, or control functions based on the received data. The apparatus is intended to improve signal processing efficiency, accuracy, or reliability in applications where real-time or precise detection and response are critical. The electronic component may include additional features such as signal conditioning, amplification, or filtering to enhance the quality of the output signal before it reaches the processing circuit. The overall system is designed to integrate seamlessly into electronic devices requiring responsive and accurate signal interpretation, such as sensors, measurement systems, or control units. The invention aims to address challenges in signal fidelity, processing speed, and system integration in electronic apparatuses.
10. A vehicle comprising: the electronic component according to claim 8 ; and a processing circuit operating based on an output signal from the electronic component.
This invention relates to a vehicle incorporating an electronic component designed to monitor and analyze vehicle conditions, along with a processing circuit that operates based on the output signal from this component. The electronic component includes a sensor configured to detect a physical parameter of the vehicle, such as temperature, pressure, or vibration, and a signal processing unit that converts the raw sensor data into a standardized output signal. The processing circuit receives this output signal and performs further analysis, such as diagnosing faults, optimizing performance, or triggering safety measures. The system ensures real-time monitoring and responsive adjustments, improving vehicle reliability and efficiency. The electronic component may also include a communication interface to transmit data to external systems for remote diagnostics or fleet management. This invention addresses the need for accurate, real-time vehicle condition monitoring to enhance safety, maintenance, and operational efficiency.
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May 21, 2020
February 22, 2022
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