A data transfer circuit includes: a one-time PROM storing first to m-th register addresses and first to m-th register data; first to n-th registers holding first to n-th data corresponding to first to n-th parameters controlling an operation of a functional element; and a data transfer control circuit acquiring the i-th register address and the i-th register data from the one-time PROM, transferring the i-th register data to the k-th register designated by the i-th register address, k being an integer equal to or greater than 1 and equal to or smaller than n, and updating the k-th data with the i-th register data.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A data transfer circuit comprising: a one-time programmable read-only memory (PROM) storing first to m-th register addresses and first to m-th register data, m being an integer equal to or greater than 1; first to n-th registers holding first to n-th data corresponding to first to n-th parameters controlling an operation of a functional element, n being an integer equal to or greater than 2; and a data transfer control circuit acquiring, with respect to each integer i equal to or greater than 1 and equal to or smaller than m, the i-th register address and the i-th register data from the one-time PROM, transferring the i-th register data to the k-th register designated by the i-th register address, k being an integer equal to or greater than 1 and equal to or smaller than n, and updating the k-th data with the i-th register data.
2. The data transfer circuit according to claim 1 , wherein the one-time PROM stores first to n-th initial data which are initial values of the first to n-th parameters, and the data transfer control circuit transfers the i-th register data to the k-th register after acquiring the first to n-th initial data from the one-time PROM and transferring the first to n-th initial data to the first to n-th registers.
3. The data transfer circuit according to claim 1 , wherein the data transfer control circuit transfers the i-th register data to the k-th register after first to n-th initial data which are initial values of the first to n-th parameters are loaded in parallel to the first to n-th registers.
4. The data transfer circuit according to claim 1 , wherein the one-time PROM stores predetermined data, the data transfer control circuit determines that transfer of the first to m-th register data is finished, on acquiring the predetermined data from the one-time PROM.
5. The data transfer circuit according to claim 1 , wherein an address of an area where the i-th register address is stored and an address of an area where the i-th register data is stored, in the one-time PROM, are different from each other.
6. The data transfer circuit according to claim 1 , wherein an address of an area where the i-th register address is stored and an address of an area where the i-th register data is stored in the one-time PROM are the same.
7. The data transfer circuit according to claim 1 , wherein the functional element is a resonator element, the data transfer circuit has an oscillation circuit oscillating the resonator element, and one of the first to n-th parameters is a temperature compensation parameter for the oscillation circuit, and another one of the first to n-th parameters is a frequency adjustment parameter for the oscillation circuit.
8. An electronic component comprising: the data transfer circuit according to claim 1 ; and the functional element.
9. An electronic apparatus comprising: the electronic component according to claim 8 ; and a processing circuit operating based on an output signal from the electronic component.
10. A vehicle comprising: the electronic component according to claim 8 ; and a processing circuit operating based on an output signal from the electronic component.
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May 21, 2020
February 22, 2022
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