Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor device, comprising: a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure; a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature; a contact etch stop layer (CESL) over the gate SAC dielectric feature; a dielectric layer over the CESL; a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure; and a liner disposed between the first spacer feature and the gate contact feature.
This invention relates to semiconductor devices, specifically addressing challenges in forming reliable gate contacts in advanced integrated circuits. The device includes a gate structure flanked by two spacer features, with the top surfaces of these spacers extending above the gate structure. A gate self-aligned contact (SAC) dielectric feature is deposited over the spacers, followed by a contact etch stop layer (CESL) and a dielectric layer. A gate contact feature is formed by etching through these layers and the spacers to reach the gate structure. A liner is positioned between the spacers and the gate contact to improve adhesion and prevent material diffusion. The design ensures precise alignment of the gate contact while minimizing leakage and improving electrical performance. The spacer features and liner enhance process control during etching, reducing defects and improving yield. This configuration is particularly useful in high-density semiconductor devices where precise contact formation is critical for performance and reliability.
2. The semiconductor device of claim 1 , wherein a composition of the liner is different a composition of the gate SAC dielectric feature.
A semiconductor device includes a gate structure with a self-aligned contact (SAC) dielectric feature and a liner surrounding the gate structure. The liner is positioned between the gate structure and the SAC dielectric feature. The liner has a composition that is different from the composition of the SAC dielectric feature. This design helps prevent unwanted interactions between the gate structure and the SAC dielectric feature, improving device reliability and performance. The liner may be made of a material that provides better adhesion, etch selectivity, or barrier properties compared to the SAC dielectric feature. The SAC dielectric feature is typically used to isolate the gate structure from subsequent interconnect layers, ensuring proper electrical insulation. The liner's distinct composition allows for optimized processing conditions during fabrication, such as selective etching or deposition, while maintaining structural integrity. This configuration is particularly useful in advanced semiconductor nodes where precise material interactions are critical for device functionality. The different compositions of the liner and SAC dielectric feature enable better control over electrical properties and manufacturing yield.
3. The semiconductor device of claim 1 , wherein the liner includes a first portion adjacent the first spacer feature and a second portion adjacent the second spacer feature, wherein the first portion is disposed between the first spacer feature and the gate contact feature and the second portion is spaced apart from the gate contact feature by a portion of the gate SAC dielectric feature.
This invention relates to semiconductor devices, specifically addressing challenges in gate contact formation and isolation in advanced semiconductor manufacturing. The device includes a gate structure with a self-aligned contact (SAC) dielectric feature surrounding it, which prevents short circuits between the gate and adjacent source/drain contacts. A liner is deposited over the SAC dielectric, with a first portion adjacent a first spacer feature and a second portion adjacent a second spacer feature. The first portion of the liner is positioned between the first spacer feature and a gate contact feature, while the second portion is spaced apart from the gate contact feature by a portion of the SAC dielectric. This configuration ensures proper electrical isolation and structural integrity during subsequent processing steps, such as etching or deposition, while maintaining reliable gate contact formation. The liner's segmented design helps prevent misalignment or over-etching issues that could compromise device performance. The invention is particularly relevant to finFET or gate-all-around transistor architectures where precise gate contact isolation is critical for yield and reliability.
4. The semiconductor device of claim 1 , wherein the liner includes a first portion adjacent the first spacer feature and a second portion adjacent the second spacer feature, wherein a height of the first portion from the gate structure is different from a height of the second portion from the gate structure.
This invention relates to semiconductor devices, specifically addressing challenges in forming liner structures adjacent to gate structures and spacer features. The device includes a gate structure with first and second spacer features on opposing sides, and a liner material deposited over the gate structure and spacers. The liner has a first portion adjacent the first spacer and a second portion adjacent the second spacer, where the height of the first portion from the gate structure differs from the height of the second portion. This asymmetric liner design enables precise control over material deposition and etching processes, improving device performance and reliability. The varying heights may be achieved through selective deposition, etching, or patterning techniques, allowing for tailored electrical and mechanical properties in different regions of the device. The invention is particularly useful in advanced semiconductor manufacturing, where precise control over liner dimensions is critical for optimizing transistor performance, reducing leakage currents, and enhancing overall device efficiency. The asymmetric liner structure can be applied to various semiconductor technologies, including FinFETs, nanowire transistors, and other advanced transistor architectures.
5. The semiconductor device of claim 1 , wherein the liner comprises silicon oxide, hafnium silicide, silicon oxycarbide, aluminum oxide, zirconium silicide, aluminum oxynitride, zirconium oxide, hafnium oxide, hafnium zirconium oxide, titanium oxide, zirconium aluminum oxide, zinc oxide, tantalum oxide, lanthanum oxide, yittrium oxide, tantalum carbonitride, silicon nitride, silicon oxycarbonitride, silicon, zirconium nitride, or silicon carbonitride.
This invention relates to semiconductor devices, specifically to the materials used in liner layers within such devices. The problem addressed is the need for improved liner materials that enhance device performance, reliability, and manufacturing efficiency. The liner layer is a thin film deposited between a substrate and other functional layers in semiconductor structures, such as transistors or memory cells, to improve adhesion, barrier properties, or electrical characteristics. The invention discloses a semiconductor device with a liner layer composed of specific materials, including silicon oxide, hafnium silicide, silicon oxycarbide, aluminum oxide, zirconium silicide, aluminum oxynitride, zirconium oxide, hafnium oxide, hafnium zirconium oxide, titanium oxide, zirconium aluminum oxide, zinc oxide, tantalum oxide, lanthanum oxide, yttrium oxide, tantalum carbonitride, silicon nitride, silicon oxycarbonitride, silicon, zirconium nitride, or silicon carbonitride. These materials are selected for their thermal stability, dielectric properties, and compatibility with semiconductor manufacturing processes. The liner may serve as a diffusion barrier, adhesion promoter, or stress control layer, depending on the application. The choice of material can optimize electrical performance, reduce leakage currents, and improve device longevity. This invention is particularly relevant in advanced semiconductor nodes where precise material selection is critical for maintaining device functionality and yield.
6. The semiconductor device of claim 1 , further comprising: a source/drain (S/D) contact adjacent the second spacer feature; and a S/D self-aligned contact (SAC) dielectric feature disposed on the S/D contact, wherein a portion of the liner is disposed between the gate SAC dielectric feature and the S/D SAC dielectric feature.
This invention relates to semiconductor devices, specifically addressing challenges in integrating self-aligned contact (SAC) structures in advanced transistor designs. The device includes a gate structure with a gate SAC dielectric feature and a surrounding liner, which extends to cover adjacent regions. A source/drain (S/D) contact is positioned adjacent to a second spacer feature, which isolates the S/D region from the gate. A S/D SAC dielectric feature is formed on top of the S/D contact. The liner is configured to separate the gate SAC dielectric feature from the S/D SAC dielectric feature, preventing electrical shorts and ensuring proper isolation between these components. This design improves reliability and performance in densely packed semiconductor devices by maintaining precise alignment and minimizing parasitic capacitance. The liner acts as a barrier, ensuring that the SAC dielectric features do not merge, which is critical for maintaining device functionality in scaled-down transistor architectures. The invention is particularly relevant to finFET or gate-all-around (GAA) transistor technologies where precise contact alignment is essential for high-performance operation.
7. The semiconductor device of claim 1 , wherein a portion of the liner is disposed over at least one of a top surface of the first spacer feature and a top surface of the second spacer feature.
The semiconductor device relates to integrated circuit fabrication, specifically addressing challenges in forming reliable and precise conductive contacts in advanced semiconductor structures. The device includes a first spacer feature and a second spacer feature adjacent to a gate structure, with a liner material deposited over these features. A key aspect is that a portion of the liner is positioned over at least one of the top surfaces of the first or second spacer features. This configuration improves the structural integrity and electrical performance of the device by ensuring proper isolation and reducing parasitic capacitance. The liner material, typically an insulating or barrier layer, prevents unwanted interactions between conductive materials and adjacent components, enhancing reliability. The spacer features, often used to define critical dimensions in transistor structures, benefit from the liner coverage to maintain precise dimensions and alignment during subsequent processing steps. This design is particularly relevant in advanced nodes where feature sizes are extremely small, and precise control of material deposition is crucial to avoid defects and performance degradation. The liner's placement over the spacer top surfaces ensures consistent electrical properties and mechanical stability, addressing issues like short circuits or leakage currents that can arise from improper material deposition. The overall structure supports high-performance semiconductor devices with improved yield and reliability.
8. A semiconductor structure, comprising: a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature; a gate self-aligned contact (SAC) dielectric feature over the first spacer feature, the gate structure and the second spacer feature; a contact etch stop layer (CESL) over the gate SAC dielectric feature; a dielectric layer over the CESL; a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure; and a liner disposed between the first spacer feature and the gate contact feature and between the first spacer feature and the gate SAC dielectric feature, wherein a portion of the gate SAC dielectric feature is disposed directly between the first spacer feature and the second spacer feature.
This invention relates to semiconductor structures, specifically addressing challenges in gate contact formation and integration in advanced semiconductor devices. The structure includes a gate structure flanked by a first and second spacer feature, with a gate self-aligned contact (SAC) dielectric feature covering the gate structure and extending between the spacers. A contact etch stop layer (CESL) is deposited over the gate SAC dielectric, followed by a dielectric layer. A gate contact feature penetrates through these layers, reaching the gate structure, and is lined with a liner material that interfaces with the first spacer and the gate SAC dielectric. The gate SAC dielectric partially extends between the spacers, ensuring proper alignment and isolation. The liner prevents direct contact between the gate contact and the spacer, improving reliability and reducing leakage. This design enhances gate contact formation in densely packed semiconductor devices, addressing issues related to misalignment, short circuits, and performance degradation in advanced node technologies. The structure ensures precise gate contact placement while maintaining electrical isolation and structural integrity.
9. The semiconductor structure of claim 8 , wherein a composition of the liner is different a composition of the gate SAC dielectric feature.
The semiconductor structure relates to advanced transistor fabrication, specifically addressing challenges in gate contact formation. The structure includes a gate self-aligned contact (SAC) dielectric feature surrounding a gate electrode, with a liner material deposited between the SAC dielectric and the gate electrode. The liner serves as a barrier to prevent diffusion of materials between the gate electrode and the SAC dielectric, ensuring reliable electrical isolation and performance. The key innovation is that the liner's composition differs from the SAC dielectric's composition, optimizing adhesion, etch selectivity, and material compatibility. This distinction allows precise control over the liner's properties, such as thermal stability and chemical resistance, while maintaining the SAC dielectric's insulating characteristics. The structure is particularly useful in finFET or gate-all-around transistor architectures, where precise material selection is critical for minimizing parasitic capacitance and leakage currents. The differing compositions enable independent optimization of the liner and SAC dielectric, improving manufacturing yield and device reliability. This approach addresses issues like gate contact resistance and dielectric breakdown, which are critical for scaling advanced semiconductor nodes.
10. The semiconductor structure of claim 8 , wherein a portion of the gate contact feature is in contact with the first spacer feature and the second spacer feature, wherein the liner does not extend between the gate contact feature and the second spacer feature.
The semiconductor structure relates to an improved gate contact design in advanced semiconductor devices, addressing challenges in electrical connectivity and manufacturing complexity. The structure includes a gate contact feature that interfaces with both a first and a second spacer feature, which are typically insulating structures adjacent to the gate electrode. A critical aspect is that the gate contact feature directly contacts both spacer features, ensuring reliable electrical connection while avoiding short circuits. Additionally, a liner material is present but does not extend between the gate contact feature and the second spacer feature, preventing unwanted insulation that could degrade performance. This design enhances conductivity and reduces resistance in the gate contact region, which is crucial for high-performance transistors in modern integrated circuits. The structure is particularly relevant for finFETs and other multi-gate devices where precise control of gate contact interfaces is essential. By optimizing the liner placement and ensuring direct contact between the gate contact and spacers, the invention improves manufacturing yield and device reliability. The solution is applicable in semiconductor fabrication processes where minimizing parasitic resistance and ensuring robust electrical connections are priorities.
11. The semiconductor structure of claim 8 , wherein the gate contact feature is asymmetric with respect to a center line of the gate contact feature.
A semiconductor structure includes a gate contact feature that is asymmetrically positioned relative to a center line of the gate contact feature. The gate contact feature is electrically coupled to a gate electrode, which is part of a transistor structure. The transistor structure includes a source region and a drain region, with the gate electrode positioned between them. The gate electrode may be formed over a channel region of a semiconductor substrate, and the gate contact feature is aligned with the gate electrode to provide electrical connectivity. The asymmetric positioning of the gate contact feature allows for optimized electrical performance, reduced parasitic capacitance, or improved layout efficiency in integrated circuit designs. The asymmetry may be achieved by offsetting the gate contact feature along a direction perpendicular to the gate electrode or by varying the dimensions of the gate contact feature on either side of the center line. This design is particularly useful in advanced semiconductor devices where precise control of electrical characteristics and layout density is critical. The structure may be part of a finFET, a planar transistor, or another transistor architecture, depending on the specific application.
12. The semiconductor structure of claim 8 , wherein the liner is in contact with the CESL.
This claim describes a part of a microchip where a protective layer called the "liner" directly touches another protective layer called the "CESL".
13. The semiconductor structure of claim 8 , wherein the liner comprises hafnium zirconium oxide.
A semiconductor structure includes a substrate with a first region and a second region, where the first region has a first conductivity type and the second region has a second conductivity type. A gate structure is positioned over the substrate, and a liner is formed over the gate structure. The liner is composed of hafnium zirconium oxide, which provides improved dielectric properties and thermal stability. The gate structure may include a high-k dielectric layer and a metal gate electrode, enhancing the structure's performance in advanced semiconductor devices. The liner's composition helps reduce leakage current and improves reliability in integrated circuits. The structure is particularly useful in transistors, such as FinFETs or gate-all-around (GAA) devices, where precise control of material properties is critical for optimal device operation. The hafnium zirconium oxide liner ensures better interface quality and compatibility with surrounding materials, contributing to overall device efficiency and longevity. This design addresses challenges in scaling semiconductor devices while maintaining electrical performance and reliability.
14. The semiconductor structure of claim 8 , wherein the gate SAC dielectric feature comprises zirconium oxide.
A semiconductor structure includes a gate structure with a self-aligned contact (SAC) dielectric feature that surrounds the gate structure to prevent electrical shorts between the gate and adjacent conductive features. The SAC dielectric feature is composed of zirconium oxide, which provides high dielectric strength and thermal stability, ensuring reliable insulation during semiconductor device operation. The gate structure is formed over a substrate and includes a gate dielectric layer, a gate electrode, and sidewall spacers. The zirconium oxide SAC dielectric feature is deposited conformally around the gate structure, filling gaps between the gate and adjacent conductive features. This configuration enhances device performance by reducing leakage currents and improving electrical isolation. The structure is particularly useful in advanced semiconductor nodes where miniaturization increases the risk of shorts between closely spaced conductive features. The zirconium oxide material is selected for its superior dielectric properties compared to traditional materials like silicon oxide or silicon nitride, offering better resistance to etching and thermal degradation during subsequent processing steps. The overall design ensures robust electrical isolation while maintaining compatibility with existing semiconductor fabrication processes.
15. The semiconductor structure of claim 8 , wherein the first spacer feature and the second spacer feature comprise silicon oxycarbonitride.
A semiconductor structure includes a first spacer feature and a second spacer feature, both composed of silicon oxycarbonitride. These spacer features are positioned adjacent to a gate structure, which is formed over a substrate and includes a gate dielectric layer, a work function metal layer, and a conductive fill material. The gate structure is flanked by source and drain regions, which may be epitaxially grown and doped to form a transistor. The silicon oxycarbonitride material in the spacer features provides improved electrical and thermal properties, enhancing device performance and reliability. The structure may also include a contact etch stop layer and an interlayer dielectric layer, which are patterned to form openings for electrical contacts. The silicon oxycarbonitride spacers help control critical dimensions, reduce leakage, and improve gate-to-source/drain isolation, making the structure suitable for advanced semiconductor devices.
16. A semiconductor structure, comprising: a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature; a source/drain contact spaced apart from the gate structure from the second spacer feature; a gate self-aligned contact (SAC) dielectric feature over the first spacer feature, the gate structure and the second spacer feature; a source/drain SAC dielectric feature over the source/drain contact; a contact etch stop layer (CESL) over the gate SAC dielectric feature and the source/drain SAC dielectric feature; a dielectric layer over the CESL; a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure; and a liner disposed between the first spacer feature and the gate contact feature and between the first spacer feature and the gate SAC dielectric feature, wherein a portion of the gate SAC dielectric feature is disposed directly between the first spacer feature and the second spacer feature.
The semiconductor structure relates to advanced transistor designs, particularly addressing challenges in contact formation and isolation in densely packed semiconductor devices. The structure includes a gate structure flanked by first and second spacer features, which define the gate's boundaries and protect adjacent regions during processing. A source/drain contact is positioned adjacent to the gate structure, separated by the second spacer feature. To ensure proper electrical isolation and prevent short circuits, a gate self-aligned contact (SAC) dielectric feature is formed over the first spacer, the gate structure, and the second spacer. Similarly, a source/drain SAC dielectric feature is deposited over the source/drain contact. A contact etch stop layer (CESL) is applied over both SAC dielectric features, followed by a dielectric layer. A gate contact feature is then formed, extending through the dielectric layer, CESL, and gate SAC dielectric feature, making direct contact with the gate structure. A liner is positioned between the first spacer and both the gate contact feature and the gate SAC dielectric feature to enhance adhesion and prevent material diffusion. The gate SAC dielectric feature partially extends between the first and second spacer features, ensuring precise alignment and minimizing parasitic capacitance. This design improves reliability and performance in high-density semiconductor devices by optimizing contact formation and isolation.
17. The semiconductor structure of claim 16 , wherein a composition of the gate SAC dielectric feature is different from a composition of the source/drain SAC dielectric feature.
A semiconductor structure includes a gate structure and source/drain contacts, each with self-aligned contact (SAC) dielectric features. The gate SAC dielectric feature and the source/drain SAC dielectric feature have distinct compositions. The gate SAC dielectric feature is positioned adjacent to the gate structure, while the source/drain SAC dielectric feature is positioned adjacent to the source/drain regions. The different compositions allow for selective etching or deposition processes during fabrication, enabling precise control over contact formation. This differentiation helps prevent misalignment or shorting between the gate and source/drain contacts, improving device reliability and performance. The structure may also include a fin or nanowire channel, with the SAC dielectric features ensuring proper isolation between the gate and source/drain contacts. The distinct compositions may be achieved through material selection, such as using different dielectric materials or doping levels, to optimize electrical properties and manufacturing efficiency. This approach is particularly useful in advanced semiconductor nodes where feature sizes are extremely small, requiring precise control over contact formation to maintain functionality.
18. The semiconductor structure of claim 16 , wherein a composition of the liner is different a composition of the gate SAC dielectric feature.
A semiconductor structure includes a gate structure with a self-aligned contact (SAC) dielectric feature surrounding the gate. The SAC dielectric feature is formed over a substrate and includes a liner layer adjacent to the gate structure. The liner layer has a composition that is different from the composition of the SAC dielectric feature. The gate structure may include a gate electrode and a gate dielectric layer, and the SAC dielectric feature may be formed using a self-aligned process to ensure precise alignment with the gate structure. The liner layer may serve as a barrier or adhesion layer to improve the interface between the gate structure and the SAC dielectric feature. The different compositions of the liner and SAC dielectric feature may be selected to optimize electrical insulation, thermal stability, or etch selectivity during fabrication. This structure is useful in advanced semiconductor devices where precise control of gate-to-contact spacing is critical to device performance and reliability. The liner layer may be composed of a material such as silicon nitride, silicon carbide, or a high-k dielectric, while the SAC dielectric feature may be composed of a different dielectric material to enhance isolation properties. The structure may be part of a finFET, gate-all-around FET, or other advanced transistor architecture.
19. The semiconductor structure of claim 16 , wherein a thickness of the liner is between about 1 nm and about 10 nm.
The semiconductor structure relates to the field of integrated circuit manufacturing, specifically addressing challenges in forming reliable and high-performance semiconductor devices. The structure includes a liner layer deposited on a substrate, where the liner serves as a barrier or interface layer to improve device performance, reliability, or manufacturability. The liner is designed to prevent diffusion of materials, reduce defects, or enhance adhesion between layers. A critical aspect of this structure is the precise control of the liner's thickness, which is specified to be between approximately 1 nm and 10 nm. This thickness range ensures optimal functionality while avoiding issues such as excessive resistance or poor step coverage. The liner may be composed of materials such as silicon nitride, silicon oxide, or other dielectric or conductive materials, depending on the application. The structure may be part of a transistor, memory device, or other semiconductor component, where the liner plays a role in electrical isolation, passivation, or structural support. The thickness control is achieved through deposition techniques like atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD), ensuring uniformity and precision. This innovation addresses the need for thin, conformal layers in advanced semiconductor manufacturing to meet performance and reliability requirements.
20. The semiconductor structure of claim 16 , wherein the gate self-aligned contact (SAC) dielectric feature is in direct contact with the first spacer feature and the second spacer feature.
A semiconductor structure includes a gate self-aligned contact (SAC) dielectric feature that is in direct contact with both a first spacer feature and a second spacer feature. The structure is designed to improve electrical isolation and reduce parasitic capacitance in advanced semiconductor devices, particularly in finFET or gate-all-around (GAA) transistor architectures. The SAC dielectric feature is positioned adjacent to the gate structure, ensuring precise alignment and minimizing misalignment-related defects. The first and second spacer features, typically formed from dielectric materials such as silicon nitride or silicon oxide, are positioned on opposing sides of the gate structure to define the source/drain regions. By ensuring direct contact between the SAC dielectric feature and both spacer features, the structure enhances process control during subsequent etching and contact formation steps, reducing the risk of short circuits or leakage paths. This configuration is particularly useful in high-density semiconductor devices where precise feature alignment is critical for performance and reliability. The invention addresses challenges in scaling down transistor dimensions while maintaining electrical isolation and structural integrity.
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June 8, 2020
February 22, 2022
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