A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An electronic device comprising: a first transistor layer on a second transistor layer; a first interconnect layer coupled to a first source/drain region on the first transistor layer; a first gate on the first transistor layer, the first gate having a first composition, wherein the first gate is an N-type gate; a second interconnect layer coupled to a second source/drain region on the second transistor layer, the second interconnect layer having an uppermost surface; and a second gate on the second transistor layer, the second gate having a second composition different than the first composition, wherein the second gate is a P-type gate, and wherein the second gate is directly on the first gate, and wherein the second gate has a bottommost surface above the uppermost surface of the second interconnect layer.
This invention relates to semiconductor device structures, specifically a stacked transistor configuration for integrated circuits. The problem addressed is the efficient integration of complementary metal-oxide-semiconductor (CMOS) transistors in a compact, vertically stacked arrangement to improve performance and reduce footprint. The device includes a first transistor layer stacked on a second transistor layer. The first transistor layer contains an N-type gate with a specific composition, while the second transistor layer contains a P-type gate with a different composition. The N-type gate is positioned above the P-type gate, with the bottom surface of the P-type gate located higher than the uppermost surface of an interconnect layer connected to the second transistor layer's source/drain region. This vertical stacking allows for direct placement of the P-type gate on the N-type gate, optimizing space and electrical connectivity. The interconnect layers provide electrical connections to the respective source/drain regions of each transistor layer, ensuring proper signal routing. This configuration enables high-density integration of complementary transistors while maintaining distinct gate materials and electrical isolation between layers. The invention is particularly useful in advanced semiconductor manufacturing for applications requiring compact, high-performance CMOS circuits.
2. The electronic device of claim 1 , wherein a portion of the first interconnect layer is extended through the first source/drain region coupled to the second source/drain region.
This invention relates to semiconductor device structures, specifically addressing challenges in interconnect design for improved electrical connectivity and performance. The device includes a semiconductor substrate with a first source/drain region and a second source/drain region, where the first source/drain region is coupled to a first interconnect layer. A portion of this interconnect layer is extended through the first source/drain region to directly connect with the second source/drain region. This extension creates a direct conductive path between the two source/drain regions, enhancing electrical connectivity and potentially reducing resistance in the device. The interconnect layer may be formed from conductive materials such as metals or doped semiconductors, and the extension may be achieved through techniques like etching, deposition, or selective growth. The structure is particularly useful in advanced semiconductor devices where efficient charge transport between source/drain regions is critical for performance. The invention may also include additional interconnect layers or insulating layers to isolate conductive paths and prevent short circuits. The extended interconnect portion ensures reliable electrical coupling while maintaining structural integrity in densely packed semiconductor layouts.
3. The electronic device of claim 1 , wherein a portion of the first interconnect layer wraps around the first source/drain region coupled to the second source/drain region.
This invention relates to semiconductor device structures, specifically addressing challenges in integrating advanced interconnect layers with source/drain regions in transistors. The problem being solved involves improving electrical connectivity and performance in nanoscale transistors by optimizing the arrangement of interconnect layers relative to source/drain regions. The invention describes an electronic device with a transistor structure that includes a first source/drain region and a second source/drain region. A first interconnect layer is positioned to electrically couple these regions. A key feature is that a portion of this interconnect layer wraps around the first source/drain region, creating a direct and efficient electrical connection to the second source/drain region. This wrapping configuration enhances current flow and reduces resistance, improving overall device performance. The interconnect layer may be formed using conductive materials such as metals or silicides, and the wrapping portion ensures minimal contact resistance while maintaining structural integrity. The design is particularly useful in advanced semiconductor nodes where traditional interconnect schemes may suffer from increased resistance or reliability issues. By wrapping the interconnect around the source/drain region, the invention provides a more robust and efficient electrical pathway, addressing limitations in conventional transistor architectures.
4. The electronic device of claim 1 , further comprising an insulating layer underneath the first gate.
The invention relates to electronic devices, specifically semiconductor structures with improved insulation properties. The problem addressed is preventing unwanted electrical interference or leakage between conductive elements in integrated circuits, particularly in devices with multiple gate structures. The electronic device includes a substrate with a first gate structure formed on its surface. An insulating layer is positioned directly beneath the first gate to electrically isolate it from underlying conductive or semiconductor regions. This insulating layer prevents current leakage or capacitive coupling between the gate and the substrate, improving device performance and reliability. The first gate may be part of a transistor or other active component, where precise electrical isolation is critical for proper operation. The insulating layer is typically made of a dielectric material such as silicon dioxide or a high-k dielectric, chosen for its insulating properties and compatibility with semiconductor fabrication processes. The layer's thickness and composition are optimized to balance electrical isolation with manufacturing feasibility. This design is particularly useful in advanced semiconductor nodes where device densities are high, and unintended interactions between components can degrade performance. The insulating layer may also serve as a barrier against diffusion of dopants or other contaminants from the substrate into the gate structure, further enhancing device stability. The overall structure ensures that the first gate operates independently of underlying regions, reducing noise and improving signal integrity in integrated circuits.
5. A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a first transistor layer on a second transistor layer; a first interconnect layer coupled to a first source/drain region on the first transistor layer; a first gate on the first transistor layer, the first gate having a first composition, wherein the first gate is an N-type gate; a second interconnect layer coupled to a second source/drain region on the second transistor layer, the second interconnect layer having an uppermost surface; and a second gate on the second transistor layer, the second gate having a second composition different than the first composition, wherein the second gate is a P-type gate, and wherein the second gate is directly on the first gate, and wherein the second gate has a bottommost surface above the uppermost surface of the second interconnect layer.
This invention relates to semiconductor device structures, specifically a computing device with a novel integrated circuit architecture. The problem addressed is the need for efficient, high-performance transistor integration in advanced semiconductor designs, particularly for complementary metal-oxide-semiconductor (CMOS) technology where N-type and P-type transistors must be closely integrated while minimizing parasitic effects and manufacturing complexity. The computing device includes a board with a component featuring a stacked transistor structure. The component has an integrated circuit with two transistor layers: a first transistor layer and a second transistor layer positioned above it. The first transistor layer includes an N-type gate with a specific composition, connected to a first source/drain region via a first interconnect layer. The second transistor layer, positioned above the first, includes a P-type gate with a different composition from the N-type gate. The P-type gate is directly stacked on top of the N-type gate, forming a vertical arrangement. The second transistor layer also includes a second source/drain region connected to a second interconnect layer, with the P-type gate's bottom surface positioned above the uppermost surface of this interconnect layer. This design enables compact, vertically integrated CMOS transistors while maintaining electrical isolation and performance. The invention aims to improve transistor density and efficiency in semiconductor devices.
6. The computing device of claim 5 , further comprising: a memory coupled to the board.
The computing device also has a memory (like RAM or storage) that's connected to the main board.
7. The computing device of claim 5 , further comprising: a communication chip coupled to the board.
A computing device includes a board with a processor and a memory storing instructions executable by the processor to perform operations. The operations include receiving a request for a service, determining whether the request is valid, and providing the service if the request is valid. If the request is invalid, the device may log the request or take other actions. The device may also include a communication chip coupled to the board, enabling data transmission and reception. The communication chip may support wired or wireless communication protocols, facilitating connectivity with external networks or devices. The processor may further analyze the request to detect anomalies or security threats, enhancing system security. The memory may store additional instructions for managing system resources, optimizing performance, or handling errors. The device may also include input/output interfaces for interacting with peripheral devices. The communication chip ensures seamless data exchange, supporting various applications such as cloud computing, IoT, or enterprise systems. The overall system improves efficiency, security, and reliability in processing service requests.
8. The computing device of claim 5 , further comprising: a camera coupled to the board.
A computing device includes a board with a processor, memory, and a communication interface for wirelessly transmitting data. The device is designed to operate in a low-power mode, where the processor periodically wakes to perform tasks such as sensing environmental conditions, processing data, and transmitting results. The device may also include a sensor coupled to the board to gather data, such as temperature or motion, and a power source like a battery to sustain operation. Additionally, the device features a camera coupled to the board, enabling image capture for further processing or transmission. The system is optimized for energy efficiency, ensuring prolonged operation in remote or resource-constrained environments. The camera may be used for monitoring, surveillance, or environmental analysis, with the processor handling image processing tasks before transmission. The communication interface supports wireless data transfer, allowing the device to relay captured data to a remote server or network. The overall design focuses on balancing performance with power consumption, making it suitable for applications requiring intermittent data collection and transmission.
9. The computing device of claim 5 , further comprising: a battery coupled to the board.
A computing device includes a board with a processor and a memory storing instructions executable by the processor to perform operations. The operations include receiving a request to execute a task, determining whether the task is eligible for execution based on a set of criteria, and executing the task if eligible. The criteria may include factors such as task priority, resource availability, or security permissions. The device also includes a battery coupled to the board, providing power for operation. The battery may be rechargeable and integrated into the device's housing. The system ensures efficient task execution by evaluating eligibility before processing, optimizing resource usage and performance. The battery integration allows for portable operation, enabling the device to function independently of external power sources. This design is suitable for mobile or embedded computing applications where power management and task prioritization are critical.
10. The computing device of claim 5 , further comprising: an antenna coupled to the board.
A computing device includes a board with a housing and a plurality of components mounted on the board. The housing has a first side and a second side, with the first side having a first surface area and the second side having a second surface area. The first surface area is larger than the second surface area. The board is positioned within the housing such that the first side of the housing is adjacent to a first side of the board and the second side of the housing is adjacent to a second side of the board. The computing device also includes an antenna coupled to the board. The antenna is positioned on the first side of the board, and the housing includes a cutout on the first side to accommodate the antenna. The antenna is configured to transmit and receive wireless signals. The computing device may also include a display coupled to the board, where the display is positioned on the first side of the board and aligned with the cutout in the housing. The housing may further include a second cutout on the second side, where the second cutout is smaller than the first cutout. The computing device may also include a camera module coupled to the board, where the camera module is positioned on the second side of the board and aligned with the second cutout in the housing. The computing device may further include a battery coupled to the board, where the battery is positioned on the second side of the board. The computing device may also include a speaker coupled to the board, where the speaker is positioned on the second side of the board. The computing device may further include a microphone coupled to the board, where the microphone is positioned on the second side of the board. The computing device may also include a plurality of input devices coupled to the board, where
11. The computing device of claim 5 , wherein the component is a packaged integrated circuit die.
A computing device includes a substrate with a cavity and a component mounted within the cavity. The cavity is formed by etching a recess into the substrate, and the component is secured using an adhesive. The substrate has a first surface and a second surface, with the cavity extending from the first surface toward the second surface. The component is electrically connected to the substrate via conductive traces, and the cavity is sealed with a sealing material to protect the component. The substrate may be a semiconductor wafer or a printed circuit board, and the component can be a packaged integrated circuit die. The adhesive used to secure the component may be a conductive or non-conductive material, depending on the application. The conductive traces provide electrical connectivity between the component and external circuits, while the sealing material ensures environmental protection. This design allows for compact integration of components within the substrate, reducing overall device size and improving performance by minimizing signal path lengths. The etching process ensures precise cavity dimensions, and the sealing material prevents contamination or damage to the component. This approach is particularly useful in high-density electronic applications where space efficiency and reliability are critical.
12. The computing device of claim 5 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
A computing device includes a component that is selected from a processor, a communications chip, or a digital signal processor. The component is configured to receive a request for a service from a user device, where the request includes a user identifier and a service identifier. The computing device determines whether the user is authorized to access the requested service by comparing the user identifier and service identifier to a set of access rules stored in a database. If the user is authorized, the computing device retrieves the requested service from a service database and transmits it to the user device. If the user is not authorized, the computing device transmits a denial message to the user device. The computing device may also log the request, including the user identifier, service identifier, and authorization result, in a log database. The system ensures secure and controlled access to services based on predefined access rules, improving security and access management in computing environments.
13. The computing device of claim 5 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.
This invention relates to computing devices configured to process and analyze data, particularly in applications requiring efficient data handling and computational tasks. The computing device includes a processor and memory storing instructions that, when executed, enable the device to perform specific operations. These operations include receiving input data, processing the data according to predefined algorithms, and generating output results. The device may also include additional components such as input/output interfaces, communication modules, and storage systems to support these functions. The computing device is designed to address challenges in data processing efficiency, scalability, and reliability. By optimizing computational tasks, the device ensures faster processing times and reduced resource consumption. The invention is applicable across various computing environments, including mobile phones, laptops, desktop computers, servers, and set-top boxes. Each of these devices may be configured to execute the same core processing functions while adapting to their specific hardware and software constraints. The invention further enhances data security by implementing encryption and authentication protocols during data transmission and storage. This ensures that sensitive information remains protected throughout the processing pipeline. The device's modular design allows for easy integration with existing systems, making it suitable for both standalone and networked applications. Overall, the invention provides a versatile solution for improving data processing capabilities in diverse computing environments.
14. The computing device of claim 5 , wherein a portion of the first interconnect layer is extended through the first source/drain region coupled to the second source/drain region.
This invention relates to semiconductor device structures, specifically addressing challenges in interconnect routing and integration within advanced integrated circuits. The technology focuses on optimizing the layout and connectivity of interconnect layers in a semiconductor device to improve performance, reduce resistance, and enhance manufacturing efficiency. The device includes a first interconnect layer that is extended through a first source/drain region, which is coupled to a second source/drain region. This extension allows for direct electrical connection between the interconnect layer and the source/drain regions, bypassing traditional routing constraints. The interconnect layer may be formed using conductive materials such as metal or doped polysilicon, ensuring low-resistance pathways. The first and second source/drain regions are part of a transistor structure, where the first source/drain region is adjacent to a gate structure, and the second source/drain region is positioned to facilitate the extended interconnect connection. The extended interconnect design reduces the need for additional vias or intermediate routing layers, simplifying the overall device architecture. This approach is particularly useful in high-density semiconductor designs where space optimization is critical. The invention may be applied in various semiconductor technologies, including FinFETs, planar transistors, or other advanced transistor architectures. The extended interconnect layer ensures efficient signal transmission while minimizing parasitic effects, improving overall circuit performance.
15. The computing device of claim 5 , wherein a portion of the first interconnect layer wraps around the first source/drain region coupled to the second source/drain region.
This invention relates to semiconductor device structures, specifically addressing challenges in integrating advanced interconnect layers with source/drain regions in transistors. The problem being solved involves optimizing electrical connectivity and performance in nanoscale semiconductor devices by improving the arrangement of interconnect layers relative to source/drain regions. The invention describes a computing device with a transistor structure that includes a first interconnect layer and a second interconnect layer. The first interconnect layer is positioned adjacent to a first source/drain region of the transistor, while the second interconnect layer is positioned adjacent to a second source/drain region. A key feature is that a portion of the first interconnect layer wraps around the first source/drain region, making direct contact with the second source/drain region. This wrapping configuration enhances electrical connectivity between the interconnect layers and the source/drain regions, improving signal transmission and reducing resistance in the device. The structure may also include additional components such as a gate structure and a channel region, which facilitate transistor operation. The wrapping interconnect design is particularly useful in advanced semiconductor nodes where traditional interconnect layouts may face limitations in performance and scalability.
16. The computing device of claim 5 , further comprising an insulating layer underneath the first gate.
A computing device includes a semiconductor substrate with a first gate structure formed on a first region of the substrate. The first gate structure includes a first gate dielectric layer, a first gate electrode, and a first gate spacer. An insulating layer is positioned underneath the first gate structure, separating it from the substrate. The device also includes a second gate structure formed on a second region of the substrate, with a second gate dielectric layer, a second gate electrode, and a second gate spacer. The second gate structure is electrically connected to the first gate structure, forming a single gate structure. The device further includes a source region and a drain region adjacent to the first and second gate structures, and a channel region beneath the first and second gate structures. The insulating layer under the first gate structure electrically isolates it from the substrate, while the second gate structure is in direct contact with the substrate. This configuration allows for improved control over the electrical characteristics of the device, such as threshold voltage adjustment and reduced leakage current. The device may be part of a semiconductor integrated circuit, such as a field-effect transistor (FET) or a finFET, used in high-performance computing applications. The insulating layer ensures proper electrical isolation, enhancing device performance and reliability.
17. An electronic device comprising: a first transistor layer on a second transistor layer; a first interconnect layer coupled to a first source/drain region on the first transistor layer; a first gate on the first transistor layer; a second interconnect layer coupled to a second source/drain region on the second transistor layer, the second interconnect layer having an uppermost surface; and a second gate on the second transistor layer, the second gate having a material layer not included in the first gate, wherein the second gate is directly on the first gate, and wherein the second gate has a bottommost surface above the uppermost surface of the second interconnect layer.
This invention relates to semiconductor device structures, specifically a multi-layered transistor configuration designed to improve performance and integration density. The device addresses challenges in conventional semiconductor designs where stacking transistors and interconnects can lead to increased parasitic capacitance, signal delay, and manufacturing complexity. The electronic device includes a first transistor layer stacked on a second transistor layer. The first transistor layer has a first interconnect layer connected to its source/drain region and a first gate. The second transistor layer has a second interconnect layer connected to its source/drain region, with the second interconnect layer having an uppermost surface. A second gate is positioned directly on the first gate, meaning it is vertically aligned with the first gate but does not extend below the uppermost surface of the second interconnect layer. The second gate includes a material not present in the first gate, allowing for optimized electrical properties or functionality. This stacked configuration enables efficient vertical integration of transistors while minimizing interference between layers. The second gate's placement ensures proper electrical isolation and reduces parasitic effects, improving overall device performance. The use of distinct materials in the gates allows for tailored electrical characteristics in each layer, enhancing flexibility in circuit design. The invention is particularly useful in advanced semiconductor applications requiring high-density, high-performance transistor structures.
18. An electronic device comprising: a first transistor layer on a second transistor layer; a first interconnect layer coupled to a first source/drain region on the first transistor layer; a first gate on the first transistor layer, the first gate having a first composition; a second interconnect layer coupled to a second source/drain region on the second transistor layer, the second interconnect layer having an uppermost surface; and a second gate on the second transistor layer, the second gate having a second composition, an entirety of the second composition different than an entirety of the first composition, wherein the second gate is directly on the first gate, and wherein the second gate has a bottommost surface above the uppermost surface of the second interconnect layer.
This invention relates to semiconductor device structures, specifically a multi-layer transistor configuration addressing challenges in integrating different transistor technologies on a single chip. The device includes two transistor layers stacked vertically, where a first transistor layer is positioned above a second transistor layer. The first transistor layer has a first gate with a specific material composition, while the second transistor layer has a second gate with a distinct material composition, ensuring the entire composition of the second gate differs from the first gate. The second gate is directly placed on top of the first gate, and its bottom surface is positioned higher than the uppermost surface of an interconnect layer connected to the second transistor layer's source/drain region. The first transistor layer is connected to an interconnect layer that interfaces with its source/drain region. This stacked arrangement allows for the integration of transistors with different material properties, enabling optimized performance for diverse applications while maintaining efficient interlayer connectivity. The design ensures proper electrical isolation and functional separation between the layers, facilitating advanced semiconductor manufacturing processes.
19. An electronic device comprising: a first transistor layer on a second transistor layer; a first interconnect layer coupled to a first source/drain region on the first transistor layer; a first gate on the first transistor layer; a second interconnect layer coupled to a second source/drain region on the second transistor layer, the second interconnect layer having an uppermost surface; and a second gate on the second transistor layer, wherein the second gate is directly on the first gate, and wherein the second gate meets the first gate at a physical interface, and wherein the second gate has a bottommost surface above the uppermost surface of the second interconnect layer.
This invention relates to semiconductor device structures, specifically a multi-layered transistor configuration designed to improve performance and integration density. The device addresses challenges in conventional semiconductor designs where interconnect layers and gate structures can interfere with each other, leading to performance degradation or increased fabrication complexity. The electronic device includes a first transistor layer stacked on a second transistor layer. The first transistor layer has a first gate and a first source/drain region connected to a first interconnect layer. The second transistor layer has a second gate and a second source/drain region connected to a second interconnect layer. The second gate is directly stacked on the first gate, forming a physical interface between them. The bottommost surface of the second gate is positioned above the uppermost surface of the second interconnect layer, ensuring proper electrical isolation and reducing interference. This stacked gate configuration allows for vertical integration of transistors, enabling higher density and improved performance in semiconductor devices. The direct stacking of gates minimizes lateral space requirements while maintaining electrical separation between interconnect layers and gate structures. The design is particularly useful in advanced semiconductor manufacturing, where space efficiency and performance optimization are critical.
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December 18, 2015
February 22, 2022
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