A solid-state imaging device includes: a latch circuit that holds a digital signal of pixel data, the digital signal having 1 bit; a driver circuit that outputs the digital signal held in the latch circuit to a read bit line pair; a sense amplifier connected to the read bit line pair; and a selector circuit that selects whether the digital signal output from the sense amplifier is to be output in normal form or in inverted form.
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1. A solid-state imaging device, comprising: a latch circuit that holds a digital signal constituting pixel data, the digital signal having 1 bit; a driver circuit that outputs the digital signal held in the latch circuit to a read bit line pair; a sense amplifier connected to the read bit line pair; and a selector circuit that selects whether the digital signal to be output from the sense amplifier is to be output in normal form or in inverted form.
A solid-state imaging device captures and processes digital pixel data. The device includes a latch circuit that stores a 1-bit digital signal representing pixel data. A driver circuit transfers this digital signal from the latch circuit to a read bit line pair. A sense amplifier connected to the read bit line pair amplifies the signal. A selector circuit determines whether the amplified signal is output in its original (normal) form or an inverted form. This allows flexible signal processing, enabling the device to adapt to different output requirements or error correction schemes. The system ensures efficient data handling by maintaining a 1-bit signal throughout the process, reducing complexity while supporting configurable output formats. The selector circuit provides versatility, allowing the device to interface with various downstream components or algorithms that may require either normal or inverted data. This design is particularly useful in high-speed imaging applications where signal integrity and processing flexibility are critical.
2. The solid-state imaging device according to claim 1 , further comprising: a comparing circuit that compares a first digital signal with a second digital signal, the first digital signal and the second digital signal being ones of the digital signal output from the sense amplifier in successive cycles, and the second digital signal being output in a next cycle after a cycle in which the first digital signal is output, wherein the selector circuit selects whether to output the digital signal in normal form or in inverted form in accordance with a comparison result from the comparing circuit.
This invention relates to solid-state imaging devices, specifically addressing the challenge of accurately converting analog signals from pixels into digital signals while minimizing errors due to noise or signal variations. The device includes an array of pixels, each configured to generate an analog signal representing incident light intensity. A sense amplifier converts these analog signals into digital signals, which are then processed by a selector circuit. The selector circuit determines whether to output the digital signal in its original (normal) form or an inverted form based on a comparison between successive digital signals. A comparing circuit evaluates a first digital signal from one cycle and a second digital signal from the next cycle, ensuring consistency in the output. If the signals differ, the selector circuit may invert the second signal to correct for noise or distortion, improving signal integrity. This adaptive inversion mechanism enhances the reliability of the digital output, particularly in high-noise environments or when dealing with weak signals. The system dynamically adjusts the output format to maintain accuracy, making it suitable for applications requiring precise image capture, such as medical imaging or scientific instrumentation.
3. The solid-state imaging device according to claim 1 , comprising: a pixel array in which a plurality of pixel units that carry out photoelectric conversion are arranged in rows and columns; an AD converter that converts analog signals from the plurality of pixel units into digital signals on a column-by-column basis; a plurality of latch circuits provided on a column-by-column basis and holding the digital signals, the plurality of latch circuits each being the latch circuit; a plurality of driver circuits that sequentially output the digital signals held in the plurality of latch circuits on a column-by-column basis, the plurality of driver circuits each being the driver circuit; a plurality of read bit line pairs respectively connected to the plurality of driver circuits, the plurality of read bit line pairs each being the read bit line pair; a plurality of sense amplifiers respectively connected to the plurality of read bit line pairs, the plurality of sense amplifiers each being the sense amplifier; and a plurality of selector circuits that select whether the digital signals output sequentially from the plurality of sense amplifiers are to be output in normal form or in inverted form, on a column-by-column basis, the plurality of selector circuits each being the selector circuit.
A solid-state imaging device includes a pixel array with multiple pixel units arranged in rows and columns, each unit performing photoelectric conversion. An analog-to-digital (AD) converter converts analog signals from the pixel units into digital signals on a column-by-column basis. Multiple latch circuits, each associated with a column, hold these digital signals. Driver circuits sequentially output the latched digital signals column by column. Each driver circuit connects to a read bit line pair, which in turn connects to a sense amplifier. The sense amplifiers amplify the digital signals from the read bit lines. Selector circuits, one per column, determine whether the amplified digital signals are output in their original form or inverted form. This configuration allows for flexible signal processing, enabling column-specific adjustments to the output signal polarity. The device is designed to enhance signal integrity and processing efficiency in imaging applications by providing precise control over digital signal output.
4. The solid-state imaging device according to claim 3 , further comprising: a plurality of comparing circuits that compare, on a bit-by-bit basis, first pixel data with second pixel data, the first pixel data and the second pixel data being ones of the digital signals output from the plurality of sense amplifiers in successive cycles; and a majority detecting circuit that detects a majority decision result based on a total number of mismatches in comparison results from the plurality of comparing circuits, wherein the plurality of selector circuits select whether to output in normal form or in inverted form in accordance with the majority decision result.
A solid-state imaging device includes a plurality of sense amplifiers that convert analog signals from pixels into digital signals. The device further includes a plurality of comparing circuits that compare first pixel data with second pixel data, where the first and second pixel data are digital signals output from the sense amplifiers in successive cycles. Each comparing circuit performs a bit-by-bit comparison between the two sets of pixel data. The device also includes a majority detecting circuit that analyzes the comparison results from all comparing circuits to determine a majority decision result based on the total number of mismatches detected. The majority decision result indicates whether the digital signals should be output in their normal form or in an inverted form. The device further includes a plurality of selector circuits that use the majority decision result to select between the normal and inverted forms of the digital signals for output. This approach helps correct errors in the digital signals by ensuring consistency across multiple comparisons, improving the reliability of the imaging device.
5. The solid-state imaging device according to claim 4 , wherein when the majority decision result is true, the plurality of selector circuits output the digital signals in inverted form.
A solid-state imaging device includes an array of pixels that generate analog signals in response to incident light. These analog signals are converted into digital signals by analog-to-digital converters (ADCs). The device further includes a plurality of selector circuits that receive the digital signals from the ADCs. Each selector circuit is configured to perform a majority decision operation on the digital signals from multiple ADCs to determine whether the majority of the signals indicate a true or false state. When the majority decision result is true, the selector circuits output the digital signals in an inverted form. This inversion ensures that the final output accurately reflects the true state of the pixel data, compensating for potential errors or noise in the conversion process. The device may also include additional circuitry to process the inverted signals further, such as error correction or signal conditioning, to enhance image quality. The majority decision and inversion mechanism improve the reliability of the digital output by mitigating the effects of individual ADC errors or noise, resulting in more accurate image data.
6. The solid-state imaging device according to claim 4 , wherein when the majority decision result is false, the plurality of selector circuits output the digital signals in normal form.
A solid-state imaging device includes a plurality of pixel circuits, each generating an analog signal, and a plurality of analog-to-digital converter (ADC) circuits that convert these analog signals into digital signals. The device also includes a majority decision circuit that compares the digital signals from the ADC circuits and determines a majority decision result. When the majority decision result is false, a plurality of selector circuits output the digital signals in their original, unmodified form. This ensures that the digital signals retain their integrity when the majority decision process does not yield a consistent result. The selector circuits may also output corrected digital signals when the majority decision result is true, improving signal accuracy. The device is designed to enhance the reliability of digital signal output in solid-state imaging applications by dynamically selecting between original and corrected signals based on the majority decision outcome. This approach helps mitigate errors in signal conversion and processing, particularly in environments where noise or interference may affect signal consistency.
7. The solid-state imaging device according to claim 4 , wherein the majority detecting circuit outputs a signal indicating the majority decision result, as a signal indicating whether the digital signal is inverted or normal, at the same time as the digital signal.
8. The solid-state imaging device according to claim 3 , wherein the AD converter converts the analog signals into digital signals each having n bits, n being an integer of 2 or greater, a number of the plurality of latch circuits provided in each of the columns is n, a number of the plurality of driver circuits provided in each of the columns is n, a number of the plurality of read bit line pairs that are provided is n, the plurality of read bit line pairs are respectively connected to the driver circuits that are arranged in a row direction, a number of the plurality of sense amplifiers that are provided is n, and a number of the plurality of selector circuits that are provided is n.
This invention relates to a solid-state imaging device, specifically addressing the challenge of efficiently converting analog signals from image sensors into digital signals while minimizing circuit complexity and power consumption. The device includes an array of pixels that generate analog signals in response to incident light. These signals are processed by an analog-to-digital (AD) converter that converts them into digital signals, each having n bits, where n is an integer of 2 or greater. The conversion process involves multiple latch circuits, driver circuits, read bit line pairs, sense amplifiers, and selector circuits, all arranged in a columnar structure. Each column of the imaging device contains n latch circuits, n driver circuits, and n read bit line pairs, ensuring parallel processing of the digital signals. The driver circuits are connected to the read bit line pairs in a row direction, allowing for synchronized data transfer. Additionally, n sense amplifiers and n selector circuits are provided to further process and route the digital signals. This configuration enables high-speed, low-power digital signal conversion while maintaining a compact circuit layout, improving the overall efficiency of the imaging device.
9. The solid-state imaging device according to claim 3 , wherein the plurality of selector circuits are input with a clock signal having a cycle k times a cycle of an operating clock signal as a selection control signal, k being an integer of 2 or greater.
A solid-state imaging device includes an array of pixels and a plurality of selector circuits that control the readout of pixel signals. The selector circuits are configured to receive a clock signal with a cycle that is an integer multiple (k) of the cycle of an operating clock signal, where k is 2 or greater. This allows the selector circuits to time-multiplex the readout of pixel signals, improving data throughput and reducing power consumption by synchronizing signal processing with the operating clock. The device may include additional circuits, such as analog-to-digital converters (ADCs) or signal processing units, that operate in coordination with the selector circuits to enhance imaging performance. The use of a clock signal with a longer cycle (k times the operating clock) enables efficient signal selection and transfer, particularly in high-resolution or high-speed imaging applications. The selector circuits may be integrated into the pixel array or positioned externally to optimize signal routing and minimize noise. The invention addresses challenges in managing high data rates and power efficiency in modern imaging systems.
10. The solid-state imaging device according to claim 3 , comprising: a plurality of output buffers that output the digital signals output from the plurality of selector circuits; and a signal processor that digitally processes the digital signals from the plurality of output buffers.
A solid-state imaging device captures and processes image data using an array of pixels, each generating an analog signal. The device includes a plurality of selector circuits that receive analog signals from the pixels and convert them into digital signals. These digital signals are then output to a plurality of output buffers, which temporarily store the data before transmission. A signal processor digitally processes the buffered signals to enhance image quality, reduce noise, or perform other image processing tasks. The device may also include an analog-to-digital converter (ADC) that converts the analog pixel signals into digital form before they reach the selector circuits. The selector circuits may further include a plurality of memory circuits that store the digital signals temporarily, allowing for efficient data handling and processing. The overall system ensures high-speed, low-noise image capture and processing, suitable for applications requiring real-time imaging, such as digital cameras, medical imaging, and surveillance systems. The digital processing stage enables advanced features like noise reduction, color correction, and image compression, improving the final output quality.
11. The solid-state imaging device according to claim 4 , wherein the majority detecting circuit includes: a plurality of match detection driver circuits corresponding to the plurality of comparing circuits; a first line that is pulled up to a predetermined potential via a first resistance element; a second line that is pulled up to the predetermined potential via a second resistance element; and a detection circuit connected to the first line and the second line, wherein each of the plurality of match detection driver circuits lowers a potential of the first line when the comparison result from the corresponding comparing circuit indicates a mismatch, and lowers a potential of the second line when the comparison result from the corresponding comparing circuit indicates a match, and when the potential of the first line is lower than the potential of the second line, the detection circuit detects that the majority decision result is true, and when the potential of the first line is higher than the potential of the second line, the detection circuit detects that the majority decision result is false.
A solid-state imaging device includes a majority detecting circuit designed to determine whether a majority of comparison results from multiple comparing circuits indicate a match or a mismatch. The circuit comprises multiple match detection driver circuits, each corresponding to one of the comparing circuits. A first line is pulled up to a predetermined potential through a first resistance element, and a second line is pulled up to the same potential through a second resistance element. A detection circuit is connected to both lines. When a comparing circuit outputs a mismatch, the corresponding match detection driver circuit lowers the potential of the first line. Conversely, when a comparing circuit outputs a match, the corresponding driver circuit lowers the potential of the second line. The detection circuit evaluates the potentials of the two lines: if the first line's potential is lower than the second line's, the majority decision result is true (indicating a majority of matches). If the first line's potential is higher, the majority decision result is false (indicating a majority of mismatches). This design enables efficient majority voting in solid-state imaging devices by leveraging resistive pull-up lines and a simple detection mechanism to determine the dominant comparison outcome.
12. The solid-state imaging device according to claim 11 , wherein each of the plurality of match detection driver circuits includes: a first transistor pair cascode-connected between the first line and a ground; and a second transistor pair cascode-connected between the second line and a ground, wherein a signal indicating the comparison result from a corresponding comparing circuit is input to a gate of one of transistors constituting the first transistor pair, and a signal indicating an inverted form of the comparison result from a corresponding comparing circuit is input to a gate of one of transistors constituting the second transistor pair.
A solid-state imaging device includes a plurality of match detection driver circuits, each connected to a first line and a second line. Each driver circuit contains a first transistor pair and a second transistor pair, both configured in a cascode arrangement between their respective lines and ground. The first transistor pair is connected between the first line and ground, while the second transistor pair is connected between the second line and ground. A comparison result signal from a corresponding comparing circuit is input to the gate of one transistor in the first pair, and an inverted version of the same comparison result is input to the gate of one transistor in the second pair. This configuration allows the driver circuits to control current flow based on the comparison result, enabling efficient signal processing in imaging applications. The comparing circuits generate the comparison result by evaluating input signals, which are then used to drive the transistor pairs in the match detection driver circuits. The cascode arrangement improves performance by reducing voltage fluctuations and enhancing linearity. This design is particularly useful in solid-state imaging devices where precise and stable signal processing is required.
13. The solid-state imaging device according to claim 4 , wherein the majority detecting circuit further includes a weighting circuit that weights a total number of mismatches or a total number of matches.
A solid-state imaging device includes a pixel array and a majority detecting circuit that evaluates pixel data to determine a majority state. The device is used in imaging applications where pixel data may contain noise or errors, and the goal is to accurately determine the majority state of a group of pixels. The majority detecting circuit compares pixel data from multiple pixels and counts the number of matches and mismatches between them. The circuit then determines whether the majority of pixels are in a first state or a second state based on these counts. To improve accuracy, the majority detecting circuit includes a weighting circuit that applies weights to the total number of mismatches or matches. This weighting allows the circuit to adjust the decision threshold, making it more robust against noise or systematic errors in the pixel data. The weighting can be fixed or dynamically adjusted based on operating conditions or calibration data. The device may be used in digital cameras, medical imaging, or other applications where reliable pixel state detection is critical. The weighting circuit enhances the reliability of the majority detection process by accounting for variations in pixel behavior or environmental factors.
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May 12, 2020
March 1, 2022
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