Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.
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1. An apparatus, comprising: a memory array comprising a plurality of access lines; and a controller coupled to the memory array, the controller to: select a first access line or a second access line for performance of a memory operation; cause performance of the memory operation; and cause the first access line and the second access line of the memory array to be equalized to a potential that is in between potentials corresponding to a logic high state and potentials corresponding to a logic low state subsequent to performance of the memory operation.
This invention relates to memory systems, specifically addressing the issue of voltage imbalance in memory arrays during read or write operations. The apparatus includes a memory array with multiple access lines (e.g., word lines or bit lines) and a controller. The controller selects either a first or a second access line to perform a memory operation (such as reading or writing data). After the operation, the controller equalizes both the first and second access lines to an intermediate voltage level. This intermediate level is between the voltage potentials representing a logic high state and a logic low state. The equalization process helps mitigate voltage imbalances that can occur during memory operations, improving reliability and performance. The controller's functionality ensures that the access lines return to a balanced state, reducing the risk of data corruption or operational errors. This approach is particularly useful in high-density memory arrays where voltage fluctuations can impact accuracy and efficiency. The invention focuses on maintaining stable voltage conditions in the memory array to enhance overall system reliability.
2. The apparatus of claim 1 , wherein, when the memory operation comprises a program operation, the controller is to cause the first access line to be selected and the second access line to be deselected.
This invention relates to memory systems, specifically apparatuses for managing access lines in memory operations. The problem addressed is optimizing memory operations, particularly during programming, to improve efficiency and reliability. The apparatus includes a memory array with multiple access lines and a controller that manages their selection. During a program operation, the controller selects a first access line while deselecting a second access line. This selective activation ensures that only the intended access line is active, preventing unintended interference or data corruption. The apparatus may also include additional components like a voltage generator to supply appropriate voltages to the access lines during operations. The selective deselection of the second access line during programming helps maintain data integrity and reduces power consumption by avoiding unnecessary activation of multiple lines. This approach is particularly useful in high-density memory arrays where precise control of access lines is critical for reliable operation. The invention improves memory performance by ensuring that only the necessary access lines are active during programming, minimizing errors and energy use.
3. The apparatus of claim 1 , wherein, when the memory operation comprises a read operation, the controller is to cause the first access line to be deselected and the second access line to be selected.
This invention relates to memory systems, specifically addressing challenges in managing access lines during memory operations to improve efficiency and reliability. The apparatus includes a memory array with multiple access lines, a controller, and a selection circuit. The controller is configured to manage memory operations such as read and write operations, while the selection circuit selectively activates or deactivates access lines based on the operation type. During a read operation, the controller ensures that a first access line is deselected while a second access line is selected, allowing precise control over data retrieval. This selective activation helps prevent interference between access lines, reducing errors and improving read performance. The apparatus may also include additional features such as error detection and correction mechanisms to further enhance data integrity. The invention aims to optimize memory access by dynamically adjusting access line selection, particularly during read operations, to ensure accurate and efficient data retrieval.
4. The apparatus of claim 1 , wherein the first access line and the second access line of the memory array are equalized to a potential that is different than a ground reference potential.
This invention relates to memory arrays, specifically addressing the issue of signal integrity and performance during access line equalization. In conventional memory arrays, access lines such as word lines or bit lines are often equalized to a ground reference potential to reduce power consumption and noise. However, this approach can lead to slower access times and increased power dissipation due to the need to charge or discharge the lines during subsequent operations. The invention improves upon prior art by equalizing the first and second access lines of the memory array to a potential that is different from the ground reference potential. This intermediate equalization potential reduces the voltage swing required during subsequent read or write operations, thereby improving speed and efficiency. The apparatus includes a memory array with multiple access lines, where at least two of these lines are selectively equalized to a non-ground potential. This intermediate potential is maintained by a control circuit that adjusts the equalization voltage based on operational requirements, ensuring optimal performance without compromising signal integrity. The invention is particularly useful in high-density memory arrays where minimizing voltage swings and reducing power consumption are critical. By avoiding full ground-level equalization, the apparatus achieves faster access times and lower energy consumption compared to conventional designs.
5. The apparatus of claim 1 , wherein the controller is, subsequent to causing the first access line and the second access line of the memory array to be equalized, to cause the first access line or the second access line, or both, to be discharged to a ground reference potential.
This invention relates to memory array access line equalization and discharge in semiconductor memory devices. The problem addressed is ensuring proper voltage equalization and controlled discharge of access lines, such as word lines or bit lines, to prevent voltage imbalances that could degrade memory performance or cause data corruption. The apparatus includes a memory array with multiple access lines, a controller, and circuitry for equalizing and discharging these lines. The controller first causes the first and second access lines to be equalized, bringing them to a common voltage level. After equalization, the controller then discharges one or both access lines to a ground reference potential. This controlled discharge prevents voltage spikes or residual charges that could interfere with subsequent memory operations. The equalization process ensures that both access lines reach a stable voltage before discharge, minimizing transient effects. The discharge to ground reference potential ensures complete removal of residual charge, improving reliability and reducing power consumption. This technique is particularly useful in high-density memory arrays where precise voltage control is critical for maintaining data integrity and operational efficiency. The invention enhances memory performance by preventing voltage-related errors and optimizing power usage during access line operations.
6. The apparatus of claim 5 , wherein the controller is, subsequent to causing the first access line or the second access line, or both, to be discharged to the ground reference potential, to bias the first access line or the second access line, or both, to a potential different than the ground reference potential.
This invention relates to memory access control in semiconductor devices, specifically addressing the challenge of efficiently managing access lines in memory arrays to improve performance and reduce power consumption. The apparatus includes a controller that regulates the discharge and biasing of access lines, such as word lines or bit lines, to optimize memory operations. The controller is configured to discharge one or both of the first and second access lines to a ground reference potential, effectively resetting their voltage levels. After this discharge, the controller biases the same access lines to a potential different from the ground reference, enabling precise control over the voltage levels during subsequent memory operations. This dynamic adjustment of access line potentials helps minimize power dissipation and enhances operational efficiency by ensuring proper voltage conditions for read, write, or refresh cycles. The invention improves upon conventional memory access techniques by actively managing access line voltages, reducing unnecessary power consumption, and mitigating signal interference. The controlled discharge and subsequent biasing of access lines ensure reliable memory access while optimizing energy usage, making it particularly useful in high-density memory arrays where power efficiency is critical. The apparatus may be integrated into various memory technologies, including DRAM, SRAM, or emerging non-volatile memory systems.
7. The apparatus of claim 1 , wherein the memory array comprises a three-dimensional memory array having a stair step structure at at least a portion of the memory array.
A three-dimensional memory array with a stair step structure is disclosed. The invention addresses challenges in high-density memory storage, particularly in scaling memory devices vertically to increase storage capacity while maintaining efficient access and manufacturing feasibility. The stair step structure allows for precise electrical connections to multiple memory layers, enabling compact and scalable memory architectures. The memory array includes multiple layers of memory cells arranged in a three-dimensional configuration, with the stair step structure formed at least at a portion of the array to facilitate electrical interconnections. This structure supports high-density storage by enabling vertical stacking of memory layers while ensuring reliable access to each layer. The stair step design optimizes the layout for manufacturing processes, reducing complexity and improving yield. The invention is applicable to non-volatile memory technologies, such as flash memory, where vertical scaling is critical for achieving higher storage densities. The apparatus leverages the stair step structure to maintain efficient electrical pathways, ensuring reliable data access and retention in a compact form factor. This approach enhances memory performance, scalability, and cost-effectiveness in advanced semiconductor devices.
8. An apparatus, comprising: a memory array comprising a stack of materials including a plurality of pairs of materials, pairs of materials including a conductive line formed over an insulation material, the stack of materials having a stair step structure formed at at least one edge of the memory array; and a controller coupled to the memory array, the controller to cause: performance of a memory operation; and a selected one of the conductive lines and a non-selected one of the conductive lines to have a substantially equal voltage after performance of the memory operation, wherein the substantially equal voltage comprises a voltage that is between voltages corresponding to a logic high state and voltages corresponding to a logic low state for the selected one of the conductive lines and the non-selected one of the conductive lines.
This invention relates to memory devices, specifically addressing voltage management in memory arrays with stair-step structures. The problem solved is the unintended voltage differences between selected and non-selected conductive lines during memory operations, which can lead to performance issues or data corruption. The apparatus includes a memory array with a stack of materials forming a stair-step structure at its edge. The stack consists of multiple pairs of materials, where each pair includes a conductive line over an insulation material. A controller is coupled to the memory array to perform memory operations while ensuring that a selected conductive line and a non-selected conductive line have substantially equal voltages afterward. This equal voltage is maintained between the logic high and logic low voltage levels for both lines, preventing voltage imbalances that could disrupt memory operations. The stair-step structure at the array edge facilitates precise electrical connections and reduces parasitic effects, improving reliability. The invention enhances memory device performance by mitigating voltage-related disturbances during read or write operations.
9. The apparatus of claim 8 , wherein the controller is to, prior to causing the selected one of the conductive lines and the non-selected one of the conductive lines to have a substantially equal voltage after performance of a memory operation, cause: a first voltage to be applied to a selected one of the conductive lines; and a second voltage to be applied to a non-selected one of the conductive lines.
This invention relates to memory devices, specifically addressing voltage management during memory operations to improve performance and reliability. The problem being solved involves ensuring that after a memory operation, selected and non-selected conductive lines (such as word lines or bit lines) reach a substantially equal voltage to prevent unintended data disturbances or leakage. The invention describes an apparatus with a controller that applies distinct voltages to selected and non-selected conductive lines before equalizing them post-operation. The apparatus includes a memory array with conductive lines and a controller that manages voltage levels during read, write, or erase operations. Initially, the controller applies a first voltage to a selected conductive line (e.g., a word line connected to a target memory cell) and a second voltage to non-selected conductive lines (e.g., adjacent word lines). This voltage differential facilitates the memory operation while minimizing interference. After the operation, the controller adjusts the voltages so that both selected and non-selected lines reach a substantially equal voltage, reducing stress on unselected cells and improving long-term reliability. The invention ensures efficient memory operations while mitigating voltage-related disturbances in non-target cells.
10. The apparatus of claim 8 , further comprising a first interconnection coupled to the conductive line of a stair step and extending substantially perpendicular to a first surface of the stair step; and a second interconnection coupled to the first interconnection extending substantially parallel to a bit line of the memory array.
This invention relates to semiconductor memory devices, specifically addressing challenges in interconnecting conductive lines in three-dimensional memory arrays. The problem involves efficiently routing electrical connections in stacked memory structures, particularly in stair-step configurations where multiple conductive lines must be connected to underlying circuitry. The invention provides a solution by incorporating a first interconnection that couples to a conductive line of a stair step and extends perpendicular to the stair step's surface. A second interconnection is then coupled to the first interconnection and extends parallel to a bit line of the memory array. This arrangement allows for precise routing of signals between the stair-step structure and the bit lines, improving electrical connectivity and reducing signal interference in densely packed memory arrays. The stair-step configuration is commonly used in three-dimensional memory devices, such as NAND flash memory, where multiple layers of memory cells are stacked vertically. The interconnections ensure reliable signal transmission while maintaining compact device dimensions. The invention enhances manufacturing efficiency and performance by optimizing the layout of conductive pathways in advanced memory architectures.
11. The apparatus of claim 8 , wherein a stair step of the stair step structure includes one of the pairs of materials.
A stair step structure is used in semiconductor devices to create a stepped profile, often for alignment or etching purposes. The problem addressed is achieving precise and reliable step formation with controlled material properties. The invention involves a stair step structure where each stair step includes a pair of materials with distinct properties, such as different etch rates, thermal conductivities, or electrical characteristics. These material pairs are selected to optimize the step formation process, ensuring accurate alignment and consistent performance. The stair step structure is part of a larger semiconductor device, where the steps may be used for alignment marks, etching templates, or other functional layers. The pairs of materials are chosen based on their compatibility with the manufacturing process and the desired performance of the final device. This approach improves the precision and reliability of the stair step formation, addressing challenges in semiconductor fabrication where material uniformity and step accuracy are critical. The invention is particularly useful in advanced semiconductor manufacturing, where precise step profiles are required for high-performance devices.
12. The apparatus of claim 8 , wherein the stack of materials has a first width in a first direction, and the stair step structure has a second width in a direction perpendicular to the first direction, the second width being less than the first width.
This invention relates to semiconductor manufacturing, specifically to the formation of stair step structures in a stack of materials. The problem addressed is the need to create precise, high-density stair step structures in material stacks, which are critical for advanced memory devices like 3D NAND. Traditional methods often struggle with maintaining structural integrity and dimensional accuracy at smaller scales. The apparatus includes a stack of materials, such as alternating layers of conductive and insulating materials, arranged in a vertical configuration. The stack has a first width in a first direction. A stair step structure is formed along an edge of the stack, where the steps are created by selectively etching or removing portions of the layers. The stair step structure has a second width in a direction perpendicular to the first direction, and this second width is smaller than the first width of the stack. This design allows for tighter spacing between steps, improving device density and performance. The apparatus may also include additional components, such as support structures or alignment features, to ensure precise formation of the stair step pattern. The invention enables the fabrication of highly compact and reliable semiconductor devices by optimizing the geometry of the stair step structure.
13. The apparatus of claim 8 , wherein the substantially equal voltage is different than a ground reference potential.
This invention relates to electrical apparatuses designed to maintain a substantially equal voltage across components or nodes, where this voltage is intentionally different from a ground reference potential. The apparatus includes a voltage regulation system that ensures consistent voltage distribution across targeted elements, preventing voltage imbalances that could lead to performance degradation or failure. The system may incorporate feedback mechanisms, such as sensors or comparators, to monitor and adjust the voltage dynamically. Additionally, the apparatus may include isolation components to prevent unintended grounding or short-circuiting, ensuring the regulated voltage remains distinct from the ground reference. The invention is particularly useful in applications where precise voltage control is critical, such as in analog circuits, power distribution systems, or sensitive electronic devices. By maintaining a stable, non-ground voltage, the apparatus enhances reliability and performance while mitigating risks associated with voltage fluctuations or grounding issues. The design may also include protective measures, such as overvoltage or undervoltage protection, to further safeguard the system.
14. A system, comprising: a first memory array comprising a first plurality of vertical strings of series-coupled memory cells controlled by a first plurality of access lines; a second memory array comprising a second plurality of vertical strings of series-coupled memory cells controlled by a second plurality of access lines; and a plurality of equalizing transistors switchably coupled to the first memory array and the second memory array, wherein: the plurality of equalizing transistors are operable to equalize a potential between one or more access lines of the first plurality of access lines or the second plurality of access lines, or both, to a potential that is between potentials corresponding to a logic high state and potentials corresponding to a logic low state for the one or more access lines of the first plurality of access lines or the second plurality of access lines, or both, subsequent to performance of a memory operation involving the first memory array or the second memory array, or both, and the first memory array and the second memory array are selectively coupled to a plurality of global control lines via selection transistors located beneath the first memory array or the second memory array, or both.
This invention relates to a memory system with multiple vertically stacked memory arrays and a mechanism for equalizing access line potentials to mitigate interference between operations. The system includes a first and second memory array, each comprising vertical strings of series-coupled memory cells controlled by respective access lines. The memory arrays are selectively coupled to global control lines via selection transistors positioned beneath the arrays. A plurality of equalizing transistors are switchably connected to both memory arrays. These transistors equalize the potential of one or more access lines in either array to an intermediate voltage level between logic high and low states after performing a memory operation. This intermediate state reduces voltage disturbances that could affect adjacent memory cells or operations. The equalization process helps maintain data integrity and performance in densely packed, vertically stacked memory architectures by minimizing interference between concurrent or sequential operations in different memory arrays. The selection transistors beneath the arrays enable independent access to each memory array while maintaining efficient control line routing. This design is particularly useful in high-density memory systems where vertical integration and operational efficiency are critical.
15. The system of claim 14 , wherein: the first plurality of vertical strings of series-coupled memory cells are located between a bit line of the first memory array and a source line of the first memory array, and the second plurality of vertical strings of series-coupled memory cells are located between a bit line of the second memory array and a source line of the second memory array.
This invention relates to a memory system architecture involving multiple memory arrays with vertically arranged memory cells. The system addresses challenges in memory density and efficiency by organizing memory cells into vertical strings, where each string consists of multiple memory cells connected in series. The system includes at least two memory arrays, each containing a plurality of these vertical strings. In each array, the vertical strings are positioned between a bit line and a source line, facilitating data read and write operations. The bit lines and source lines serve as electrical pathways for accessing the memory cells within the strings. The vertical arrangement of memory cells allows for higher memory density compared to traditional planar memory designs, while the series-coupled configuration within each string enables efficient data storage and retrieval. The system may also include additional components such as peripheral circuits for controlling memory operations, ensuring reliable and fast access to stored data. This architecture is particularly useful in advanced memory technologies like 3D NAND flash, where vertical stacking of memory cells is essential for achieving high storage capacity in a compact form factor.
16. The system of claim 14 , further comprising control circuitry coupled to the first memory array and the second memory array, the control circuitry to control performance of a memory operation using the first memory array or the second memory array, or both.
This invention relates to a memory system with multiple memory arrays and control circuitry for managing memory operations. The system includes a first memory array and a second memory array, where each array may be a different type of memory, such as DRAM and NAND flash. The control circuitry is coupled to both memory arrays and is responsible for directing memory operations, such as read, write, or erase operations, across the arrays. The control circuitry can selectively use either the first memory array, the second memory array, or both, depending on the operation requirements. This allows for flexible memory management, potentially improving performance, efficiency, or reliability by leveraging the strengths of different memory types. The system may also include additional components, such as a memory controller or interface, to facilitate communication between the memory arrays and external devices. The invention aims to optimize memory operations by dynamically utilizing multiple memory arrays under the direction of the control circuitry.
17. The system of claim 14 , wherein the first memory array or the second memory array, or both, comprise a stack of materials including a plurality of pairs of materials, pairs of materials including a conductive line formed over an insulation material, the stack of materials having a stair step structure formed at at least one edge of the first memory array or the second memory array, or both.
This invention relates to memory systems, specifically to the structure of memory arrays in semiconductor devices. The problem addressed is the efficient and reliable formation of memory arrays with complex multi-layered structures, particularly in three-dimensional memory architectures. The invention describes a memory system with at least two memory arrays, each comprising a stack of materials. The stack includes multiple pairs of materials, where each pair consists of a conductive line formed over an insulation material. The stack is arranged in a stair-step structure at the edges of the memory arrays. This stair-step configuration allows for precise electrical connections to different layers within the stack, facilitating the integration of the memory arrays into larger semiconductor devices. The conductive lines enable data storage or transfer, while the insulation materials electrically isolate the lines. The stair-step structure simplifies the manufacturing process by providing accessible contact points for interconnecting the memory arrays with other components. This design is particularly useful in high-density memory devices, such as flash memory or other non-volatile storage systems, where efficient use of space and reliable electrical connections are critical. The invention improves manufacturing yield and performance by ensuring proper alignment and connectivity within the memory arrays.
18. The system of claim 14 , further comprising control circuitry coupled to the first memory array, the second memory array, and the plurality of access lines, wherein the control circuitry is to cause the one or more access lines of the plurality of access lines to be discharged to a ground reference potential subsequent to the one or more access lines being equalized.
The system relates to memory storage technology, specifically addressing the challenge of efficiently managing access lines in memory arrays to improve performance and reliability. The system includes a first memory array and a second memory array, each containing memory cells organized in rows and columns. A plurality of access lines, such as word lines or bit lines, are connected to the memory cells to facilitate read and write operations. The system further includes control circuitry that manages the operation of these access lines. After an equalization process, where the access lines are brought to a balanced voltage level, the control circuitry ensures that the access lines are discharged to a ground reference potential. This discharge step helps reduce residual voltage, minimizing interference and improving the accuracy of subsequent memory operations. The control circuitry may also coordinate timing and voltage levels to optimize power efficiency and data integrity. This approach is particularly useful in high-density memory systems where precise control of access lines is critical for reliable data access and retention.
19. The system of claim 14 , further comprising control circuitry coupled to the first memory array, the second memory array, and the plurality of access lines, wherein the control circuitry is to: cause a first access line of the one or more access lines to be biased to a first potential subsequent to the one or more access lines being equalized; and cause a second access line of the one or more access lines to be biased to a second potential subsequent to the one or more access lines being equalized.
The invention relates to memory systems, specifically addressing the challenge of efficiently managing access lines in memory arrays to improve performance and reliability. The system includes a first memory array and a second memory array, each connected to a plurality of access lines. These access lines are initially equalized to a common potential to ensure uniform conditions before any access operations. The system further includes control circuitry that selectively biases individual access lines to different potentials after equalization. Specifically, the control circuitry biases a first access line to a first potential and a second access line to a second potential, allowing for precise control over memory access operations. This selective biasing helps optimize read and write operations, reduce power consumption, and minimize interference between adjacent memory cells. The system ensures that access lines are properly conditioned before being used, enhancing the overall efficiency and reliability of the memory system. The control circuitry's ability to independently adjust the potentials of different access lines enables fine-tuned control, which is particularly useful in high-density memory arrays where precise voltage management is critical.
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July 6, 2020
March 15, 2022
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