Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a semiconductor well, a source area and a drain area next to the semiconductor well, a gate electrode, and a base terminal. The gate electrode may be coupled to the base terminal, hence forming a floating body MOSFET. A junction may exist between the drain area and the semiconductor well. A first resistance may exist between the source area and the drain area through the semiconductor well. A programming operation may be performed when the gate electrode is coupled to a high impedance, a programming voltage is applied at the source area, and the drain area is coupled to a ground voltage to break the junction between the drain area and the semiconductor well to generate a current between the source area, the semiconductor well, and the drain area. Other embodiments may be described and/or claimed.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An integrated circuit (IC), comprising: a source area adjacent to a semiconductor well and above a substrate; a drain area adjacent to the semiconductor well and above the substrate, wherein a junction exists between the drain area and the semiconductor well; a base terminal coupled to the semiconductor well; and a gate electrode above the semiconductor well, the gate electrode coupled to the base terminal; wherein the source area, the semiconductor well, the gate electrode, and the drain area form a metal-oxide-semiconductor field-effect-transistor (MOSFET), the MOSFET configurable to have a first resistance between the source area and the drain area through the semiconductor well, and the MOSFET configurable to have a second resistance between the source area, the drain area, and the semiconductor well, after a programming operation is performed when the gate electrode is coupled to a high impedance, a programming voltage is applied at the source area, and the drain area is coupled to a ground voltage to break the junction between the drain area and the semiconductor well to generate a current between the source area, the semiconductor well, and the drain area.
2. The integrated circuit of claim 1 , wherein the substrate is a bulk substrate, a silicon-on-insulator (SOI) substrate, or a partial-depleted SOI substrate.
This invention relates to integrated circuits (ICs) with improved semiconductor substrates designed to enhance performance and reliability. The IC includes a substrate that can be a bulk substrate, a silicon-on-insulator (SOI) substrate, or a partial-depleted SOI substrate. Bulk substrates are traditional semiconductor wafers, while SOI substrates feature a thin silicon layer insulated from the underlying bulk material, reducing parasitic capacitance and improving speed. Partial-depleted SOI substrates have a partially depleted silicon layer, balancing performance and manufacturing complexity. The choice of substrate type allows optimization for different applications, such as high-speed digital circuits, power management, or analog/RF designs. The invention addresses challenges in semiconductor fabrication, including leakage current, thermal management, and process variability, by providing flexibility in substrate selection. This adaptability ensures better control over electrical characteristics, enabling higher efficiency and reliability in integrated circuits. The substrate configuration also supports advanced manufacturing techniques, such as finFET or gate-all-around transistor structures, for next-generation semiconductor devices.
3. The integrated circuit of claim 1 , wherein the MOSFET is a FinFET, or a planar MOSFET.
The invention relates to integrated circuits incorporating MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices, specifically FinFETs or planar MOSFETs, to address challenges in semiconductor manufacturing and performance optimization. FinFETs are three-dimensional transistors with fin-shaped channels, offering improved electrostatic control and reduced leakage current compared to traditional planar MOSFETs. Planar MOSFETs are two-dimensional transistors with a flat channel structure, widely used in conventional integrated circuits. The integrated circuit includes a MOSFET device, which can be either a FinFET or a planar MOSFET, depending on the application requirements. FinFETs are particularly advantageous for advanced nodes due to their superior scalability and performance at smaller technology nodes, while planar MOSFETs may be preferred for cost-effective solutions in less demanding applications. The choice between FinFET and planar MOSFET allows for flexibility in design, enabling optimization for different performance, power, and cost trade-offs. The invention aims to provide a versatile integrated circuit architecture that can leverage the benefits of either FinFET or planar MOSFET technology, depending on the specific needs of the application. This flexibility enhances manufacturing efficiency and performance across various semiconductor devices, addressing the need for scalable and adaptable transistor designs in modern integrated circuits.
4. The integrated circuit of claim 1 , wherein the semiconductor well is a n-type well or a p-type well.
This invention relates to integrated circuits with semiconductor wells used for electronic device fabrication. The problem addressed is optimizing the conductivity and performance of semiconductor wells in integrated circuits by selecting appropriate doping types. The invention describes an integrated circuit containing a semiconductor well, which can be either an n-type well or a p-type well, depending on the specific application requirements. The well is formed within a semiconductor substrate and is used to house active devices such as transistors or diodes. The doping type of the well determines its electrical properties, with n-type wells providing electron conductivity and p-type wells providing hole conductivity. The selection of well type allows for the integration of complementary devices, enabling the fabrication of CMOS (complementary metal-oxide-semiconductor) circuits. The invention ensures proper isolation and functionality of devices within the well by controlling the doping concentration and distribution. This approach enhances device performance, reduces leakage currents, and improves overall circuit reliability. The semiconductor well can be fabricated using standard semiconductor processing techniques, including ion implantation and diffusion processes, to achieve the desired doping profile. The invention is applicable in various integrated circuit designs, including memory devices, logic circuits, and power electronics, where precise control of semiconductor well properties is critical.
5. The integrated circuit of claim 1 , wherein the programming voltage is less than or equal to about 2.5 V.
The invention relates to an integrated circuit with a non-volatile memory cell that can be programmed at a low voltage. The memory cell includes a floating gate transistor with a control gate, a source, and a drain. The control gate is coupled to a word line, and the source and drain are coupled to bit lines. The memory cell is programmed by applying a programming voltage to the control gate while grounding the source, with the programming voltage being less than or equal to about 2.5 V. This low-voltage programming allows the memory cell to be integrated into systems with power constraints, such as portable electronics, while maintaining reliable data storage. The reduced programming voltage minimizes power consumption and heat generation, improving efficiency and longevity. The memory cell may also include additional features, such as a tunneling oxide layer for charge retention and a select transistor for isolating the memory cell during read operations. The low-voltage operation ensures compatibility with modern semiconductor processes and low-power applications.
6. The integrated circuit of claim 1 , wherein the first resistance is about 10 4 to 10 6 times larger than the second resistance.
This invention relates to integrated circuits, specifically those incorporating resistive elements with a defined resistance ratio. The problem addressed is the need for precise control of resistance values in integrated circuits to ensure proper functionality, particularly in applications requiring high resistance ratios for accurate signal processing or power management. The integrated circuit includes at least two resistive elements, where the first resistance is significantly larger than the second resistance, specifically in a ratio of approximately 10,000 to 1,000,000 times. This large resistance ratio is critical for applications such as voltage division, current limiting, or signal conditioning, where precise resistance values are necessary to maintain circuit performance. The resistive elements may be implemented using various technologies, including polysilicon resistors, diffusion resistors, or other semiconductor-based resistive structures. The high resistance ratio ensures that the first resistive element can effectively limit current or divide voltage while the second resistive element provides a stable reference or low-impedance path. This design is particularly useful in analog circuits, sensor interfaces, or power management systems where accurate resistance values are essential for reliable operation. The invention may also include additional circuitry to compensate for environmental factors like temperature or process variations, ensuring consistent performance across different operating conditions.
7. The integrated circuit of claim 1 , wherein the gate electrode includes germanium (Ge), cobalt (Co), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, W, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, or InAlO.
The invention relates to an integrated circuit with an improved gate electrode structure designed to enhance electrical performance and reliability. The gate electrode includes at least one of germanium (Ge), cobalt (Co), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, W, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, or InAlO. These materials are selected for their favorable electrical conductivity, thermal stability, and compatibility with semiconductor manufacturing processes. The gate electrode may be part of a transistor structure, where it controls the flow of current between source and drain regions. The use of these specific metals and alloys helps reduce resistance, improve charge carrier mobility, and enhance overall device performance. The invention addresses challenges in semiconductor scaling, such as increased resistance and reliability issues in advanced nodes, by providing a gate electrode with optimized material properties. The materials chosen also resist oxidation and diffusion, ensuring long-term stability under operating conditions. This innovation is particularly relevant for high-performance and low-power integrated circuits in modern electronic devices.
8. The integrated circuit of claim 1 , wherein the programming operation is performed when the MOSFET is in an off state.
This invention relates to integrated circuits incorporating metal-oxide-semiconductor field-effect transistors (MOSFETs) and methods for programming such circuits. The technology addresses the challenge of performing programming operations in integrated circuits without disrupting the normal operation of MOSFETs, particularly when the transistor is in an off state. The invention enables programming of the integrated circuit while maintaining the MOSFET in a non-conductive state, ensuring that the programming process does not interfere with the transistor's functionality or the overall circuit performance. This is achieved through a specialized programming mechanism that operates independently of the MOSFET's conductive state, allowing for reliable and efficient programming without requiring the transistor to be in an active state. The solution is particularly useful in applications where continuous operation is critical, such as in memory devices or logic circuits, where programming must occur without disrupting the circuit's normal operation. The invention ensures that the programming process is isolated from the MOSFET's operational state, preventing any potential interference or degradation of performance during the programming phase. This approach enhances the reliability and efficiency of integrated circuit programming while maintaining the integrity of the MOSFET's functionality.
9. The integrated circuit of claim 1 , further comprising: a sense amplifier to perform a sense operation to detect the MOSFET has been programmed when the gate electrode is to control the MOSFET in an off-state, and a current is detected between the source area and the drain area.
This invention relates to integrated circuits incorporating metal-oxide-semiconductor field-effect transistors (MOSFETs) with enhanced programming detection. The technology addresses the challenge of reliably verifying the programmed state of a MOSFET, particularly when the device is intended to be in an off-state but may still conduct unintended current due to manufacturing variations or operational conditions. The integrated circuit includes a MOSFET with a gate electrode, a source area, and a drain area. A sense amplifier is integrated to perform a sense operation that detects whether the MOSFET has been successfully programmed. The sense operation specifically checks for the presence of current between the source and drain areas when the gate electrode is configured to maintain the MOSFET in an off-state. If current is detected, it indicates a programming failure or unintended conduction, allowing for corrective measures or further diagnostic steps. The sense amplifier provides a precise and automated method to verify the MOSFET's programmed state, improving reliability in applications where accurate state detection is critical, such as memory devices or logic circuits. This solution enhances fault detection and ensures proper device operation under varying conditions.
10. The integrated circuit of claim 1 , further comprising: a first selector coupled to the drain electrode; a second selector coupled to the source electrode; and a gate controller to couple the gate electrode to a high impedance.
The invention relates to an integrated circuit with improved memory cell architecture, addressing challenges in data retention and access efficiency in semiconductor memory devices. The circuit includes a memory cell with a drain electrode, a source electrode, and a gate electrode, where the gate electrode is coupled to a high-impedance state via a gate controller to minimize leakage current and enhance data retention. The circuit further includes a first selector connected to the drain electrode and a second selector connected to the source electrode. These selectors enable precise control over data read and write operations, reducing interference between adjacent memory cells and improving overall circuit performance. The high-impedance coupling of the gate electrode ensures stable voltage levels during standby modes, preventing unintended data corruption. The selectors allow independent activation of the drain and source electrodes, facilitating efficient data transfer while maintaining low power consumption. This design is particularly useful in non-volatile memory applications where reliability and energy efficiency are critical. The integration of selectors and gate control mechanisms provides a robust solution for modern semiconductor memory systems, addressing issues related to signal integrity and power management.
11. The integrated circuit of claim 10 , wherein the first selector or the second selector is a NMOS transistor or a PMOS transistor.
This invention relates to integrated circuits, specifically those incorporating selector devices for memory or logic applications. The problem addressed is the need for efficient, compact, and reliable selector components that can control current flow in integrated circuits, particularly in memory arrays or logic circuits. The integrated circuit includes a first selector and a second selector, each configured to control current flow between a first terminal and a second terminal. The selectors are designed to operate in response to a control signal, allowing or blocking current flow based on the signal's state. The selectors may be implemented using either NMOS (n-channel metal-oxide-semiconductor) transistors or PMOS (p-channel metal-oxide-semiconductor) transistors, depending on the circuit requirements. These transistors act as switches, enabling or disabling current paths in response to voltage or current inputs. The use of NMOS or PMOS transistors as selectors provides advantages such as low power consumption, fast switching speeds, and compatibility with standard semiconductor fabrication processes. The selectors can be integrated into memory cells, such as in resistive RAM (ReRAM) or phase-change RAM (PCRAM), where they help isolate memory elements during read and write operations. Alternatively, they can be used in logic circuits to control signal routing or power distribution. The invention focuses on optimizing the selector design to improve performance, reduce leakage current, and enhance scalability in advanced semiconductor technologies. By leveraging NMOS or PMOS transistors, the circuit achieves reliable switching behavior while maintaining compatibility with existing fabrication techniques.
12. The integrated circuit of claim 1 , wherein the source area, the drain area, the base terminal, the semiconductor well, the gate electrode, and the MOSFET is a first source area, a first drain area, a first base terminal, a first semiconductor well, a first gate electrode, and a first MOSFET, respectively, and the integrated circuit further includes: a second semiconductor well isolated from the first semiconductor well by an isolation area; a second source area adjacent to the second semiconductor well and above the substrate; a second drain area adjacent to the second semiconductor well and above the substrate, wherein a second junction exists between the second drain area and the second semiconductor well; a second base terminal coupled to the second semiconductor well; a second gate electrode above the second semiconductor well, the second gate electrode coupled to the second base terminal; wherein the second source area, the second semiconductor well, the second gate electrode, and the second drain area form a second MOSFET, the second MOSFET configurable to have a third resistance between the second source area and the second drain area through the second semiconductor well, and the second MOSFET configurable to have a fourth resistance between the second source area, the second drain area, and the second semiconductor well, after a programming operation is performed when the second gate electrode is coupled to a high impedance, a programming voltage is applied at the second source area, and the second drain area is coupled to a ground voltage to break the junction between the second drain area and the second semiconductor well to generate a current between the second source area, the second semiconductor well, and the second drain area.
This invention relates to an integrated circuit with a configurable MOSFET structure for resistance-based programming. The circuit includes a first MOSFET formed within a first semiconductor well, featuring a source area, drain area, base terminal, and gate electrode. The MOSFET can be configured to exhibit different resistance states between the source and drain through the semiconductor well or between the source, drain, and well. The circuit further includes a second MOSFET within a second semiconductor well isolated from the first by an isolation area. The second MOSFET has a similar structure with a source area, drain area, base terminal, and gate electrode. The second MOSFET can be programmed by applying a programming voltage to the source area while the drain area is grounded and the gate electrode is at high impedance. This breaks the junction between the drain area and the semiconductor well, creating a conductive path that alters the resistance between the source, drain, and well. The programming operation enables the MOSFET to switch between different resistance states, useful for non-volatile memory or configurable circuit applications. The isolation between the wells ensures independent operation of the MOSFETs.
13. A method for forming an integrated circuit, the method comprising: forming a source area adjacent to a semiconductor well and above a substrate; forming a drain area adjacent to the semiconductor well and above the substrate, wherein a junction exists between the drain area and the semiconductor well; forming a base terminal coupled to the semiconductor well; and forming a gate electrode above the semiconductor well, the gate electrode coupled to the base terminal; wherein the source area, the semiconductor well, the gate electrode, and the drain area form a metal-oxide-semiconductor field-effect-transistor (MOSFET), the MOSFET configurable to have a first resistance between the source area and the drain area through the semiconductor well, and the MOSFET configurable to have a second resistance between the source area, the drain area, and the semiconductor well, after a programming operation is performed when the gate electrode is coupled to a high impedance, a programming voltage is applied at the source area, and the drain area is coupled to a ground voltage to break the junction between the drain area and the semiconductor well to generate a current between the source area, the semiconductor well, and the drain area.
This invention relates to integrated circuit fabrication, specifically a method for forming a programmable metal-oxide-semiconductor field-effect-transistor (MOSFET) structure. The MOSFET includes a source area and a drain area formed adjacent to a semiconductor well above a substrate, with a junction between the drain area and the semiconductor well. A base terminal is coupled to the semiconductor well, and a gate electrode is formed above the semiconductor well and connected to the base terminal. The MOSFET can operate in two configurations: a first resistance state between the source and drain through the semiconductor well, and a second resistance state after a programming operation. During programming, the gate electrode is held at high impedance, a programming voltage is applied to the source area, and the drain area is grounded. This breaks the junction between the drain area and the semiconductor well, creating a conductive path between the source, semiconductor well, and drain. The resulting structure enables reconfigurable resistance states in the MOSFET, useful for applications requiring programmable circuit elements. The method ensures precise control over the junction breakdown process to achieve desired electrical characteristics.
14. The method of claim 13 , wherein the substrate is a bulk substrate, a silicon-on-insulator (SOI) substrate, or a partial-depleted SOI substrate.
This invention relates to semiconductor fabrication, specifically methods for forming semiconductor devices on different types of substrates. The method addresses the challenge of optimizing device performance and manufacturing efficiency by accommodating various substrate types, including bulk substrates, silicon-on-insulator (SOI) substrates, and partially depleted SOI substrates. The process involves forming a semiconductor device structure on these substrates, ensuring compatibility and performance across different substrate configurations. Bulk substrates provide a traditional semiconductor base, while SOI substrates offer improved electrical isolation and reduced parasitic capacitance. Partially depleted SOI substrates balance performance and cost by allowing partial depletion of the silicon layer. The method ensures that the device structure, such as transistors or other semiconductor components, is properly integrated with the chosen substrate type, maintaining electrical and structural integrity. This flexibility in substrate selection allows manufacturers to tailor device characteristics for specific applications, such as high-speed logic, memory, or power devices, while optimizing cost and performance trade-offs. The invention enhances semiconductor fabrication by providing a versatile approach to substrate integration, improving yield and device reliability.
15. The method of claim 13 , wherein the MOSFET is a FinFET, or a planar MOSFET.
A method for fabricating semiconductor devices addresses the challenge of improving performance and reliability in advanced integrated circuits. The method involves forming a metal-oxide-semiconductor field-effect transistor (MOSFET) with enhanced structural features. The MOSFET may be either a FinFET or a planar MOSFET, depending on the specific application requirements. FinFETs are three-dimensional structures that provide better electrostatic control and reduced leakage currents, making them suitable for high-performance and low-power applications. Planar MOSFETs, on the other hand, are two-dimensional devices that are simpler to manufacture and may be used in less demanding applications. The method includes steps for forming the MOSFET structure, such as defining the active regions, depositing gate materials, and forming source and drain regions. The choice between FinFET and planar MOSFET depends on factors like device density, power consumption, and manufacturing complexity. The method ensures optimal device performance by carefully controlling the dimensions and materials used in the fabrication process. This approach helps address issues like short-channel effects, leakage currents, and thermal management, which are critical for modern semiconductor devices. The resulting MOSFETs exhibit improved switching speeds, lower power consumption, and better reliability, making them suitable for advanced electronic systems.
16. The method of claim 13 , wherein the semiconductor well is a n-type well or a p-type well.
This invention relates to semiconductor fabrication, specifically methods for forming semiconductor wells in integrated circuits. The problem addressed is the need for precise control over the conductivity type (n-type or p-type) of semiconductor wells to ensure proper device functionality in integrated circuits. The method involves forming a semiconductor well in a substrate, where the well can be either n-type or p-type, depending on the desired application. The well formation process includes doping the substrate with appropriate dopants to achieve the desired conductivity type. The method ensures that the well is formed with consistent electrical properties, which is critical for the performance of transistors and other semiconductor devices built within the well. The invention also includes steps for defining the well region, such as using masking techniques to selectively dope only the intended areas. The resulting semiconductor well provides a controlled environment for subsequent device fabrication, ensuring reliable operation of the integrated circuit. The flexibility to form either n-type or p-type wells allows for the implementation of various circuit designs, including complementary metal-oxide-semiconductor (CMOS) structures. The method is particularly useful in advanced semiconductor manufacturing processes where precise doping control is essential.
17. The method of claim 13 , wherein the first resistance is about 10 4 to 10 6 times larger than the second resistance.
This invention relates to a method for controlling electrical resistance in a system, particularly in applications where precise resistance ratios are critical, such as in sensor circuits, signal conditioning, or electronic measurement systems. The problem addressed is the need for a reliable and scalable way to maintain a specific resistance ratio between two components to ensure accurate signal processing or measurement. The method involves adjusting the resistance of a first component to be significantly higher than a second component, specifically in a ratio of approximately 10^4 to 10^6 times larger. This large resistance ratio is essential for applications where one component must dominate the electrical behavior of the system, such as in high-impedance sensing or when isolating a signal source from a load. The method ensures that the first component's resistance is sufficiently large to minimize current leakage or interference from the second component, improving system accuracy and stability. The technique may involve selecting materials, adjusting component dimensions, or using specific circuit configurations to achieve the desired resistance ratio. The method is particularly useful in systems where precise signal attenuation, filtering, or isolation is required, such as in biomedical sensors, precision instrumentation, or high-frequency circuits. By maintaining this ratio, the system can operate with reduced noise and improved signal integrity.
18. The method of claim 13 , wherein the gate electrode includes germanium (Ge), cobalt (Co), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, W, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, or InAlO.
The invention relates to semiconductor device fabrication, specifically to the composition of gate electrodes in transistors. A common challenge in semiconductor manufacturing is achieving high conductivity and stability in gate electrodes while ensuring compatibility with surrounding materials and processes. The invention addresses this by specifying a gate electrode composed of germanium (Ge), cobalt (Co), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, W, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, or InAlO. These materials are selected for their electrical properties, such as high conductivity and resistance to oxidation, which are critical for improving transistor performance and reliability. The gate electrode may be part of a field-effect transistor (FET) or other semiconductor device, where it controls the flow of current in the channel region. The specified materials enhance charge carrier mobility and reduce resistance, leading to faster switching speeds and lower power consumption. The invention also ensures compatibility with various semiconductor processes, including deposition and etching techniques, to maintain structural integrity during fabrication.
19. The method of claim 13 , wherein the programming operation is performed when the MOSFET is in an off state.
A method for performing a programming operation on a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) involves executing the operation while the MOSFET is in an off state. This technique is particularly useful in semiconductor devices where programming operations, such as configuring memory cells or adjusting transistor parameters, must be performed without disrupting the device's active operation. By conducting the programming operation while the MOSFET is off, the method ensures that the device remains in a stable state, preventing unintended current flow or voltage fluctuations that could degrade performance or damage components. The approach is applicable in integrated circuits, memory devices, and other semiconductor applications where precise control over transistor states is critical. The method may involve applying specific voltage or current signals to the MOSFET's gate, source, or drain terminals to achieve the desired programming effect while maintaining the transistor in a non-conductive state. This technique enhances reliability and efficiency in semiconductor manufacturing and device operation.
20. A computing device, comprising: a circuit board; and an antifuse memory array coupled to the circuit board, wherein the antifuse memory array includes a plurality of antifuse cells, an antifuse cell of the plurality of antifuse cells includes an antifuse element coupled to a first selector and a second selector, and wherein the antifuse element includes: a source area adjacent to a semiconductor well and above a substrate, the source area coupled to a word line of the antifuse memory array through the first selector; a drain area adjacent to the semiconductor well and above the substrate, the drain area coupled to a bit line of the antifuse memory array through the second selector, wherein a junction exists between the drain area and the semiconductor well; a base terminal coupled to the semiconductor well; and a gate electrode above the semiconductor well, the gate electrode coupled to the base terminal, and coupled to a source line of the antifuse memory array; wherein the source area, the semiconductor well, the gate electrode, and the drain area form a metal-oxide-semiconductor field-effect-transistor (MOSFET), the MOSFET configurable to have a first resistance between the source area and the drain area through the semiconductor well, and the MOSFET configurable to have a second resistance between the source area, the drain area, and the semiconductor well, after a programming operation is performed when the gate electrode is coupled to a high impedance, a programming voltage is applied at the source area, and the drain area is coupled to a ground voltage to break the junction between the drain area and the semiconductor well to generate a current between the source area, the semiconductor well, and the drain area.
This invention relates to a computing device with an antifuse memory array designed to address challenges in non-volatile memory programming and reliability. The device includes a circuit board and an antifuse memory array coupled to it. The array consists of multiple antifuse cells, each containing an antifuse element connected to two selectors. The antifuse element features a source area and a drain area adjacent to a semiconductor well above a substrate. The source area connects to a word line through the first selector, while the drain area connects to a bit line through the second selector. A junction exists between the drain area and the semiconductor well. The antifuse element also includes a base terminal coupled to the semiconductor well and a gate electrode above the well, which is connected to the base terminal and a source line. The source area, semiconductor well, gate electrode, and drain area form a metal-oxide-semiconductor field-effect-transistor (MOSFET). The MOSFET can be configured to have a first resistance between the source and drain areas through the semiconductor well. After a programming operation, the MOSFET can achieve a second resistance by breaking the junction between the drain area and the semiconductor well. This is done by applying a programming voltage to the source area while the drain area is grounded and the gate electrode is at high impedance, creating a current path between the source area, semiconductor well, and drain area. This design enhances memory programming efficiency and reliability by controlling resistance states through selective junction breakdown.
21. The computing device of claim 20 , wherein the first selector or the second selector is a PMOS transistor or a NMOS transistor.
This invention relates to computing devices incorporating transistor-based selectors for memory or logic applications. The problem addressed is the need for efficient, scalable selector components that can control current flow in integrated circuits, particularly in emerging memory technologies like resistive RAM (ReRAM) or neuromorphic computing systems. The computing device includes a selector circuit with a first selector and a second selector, each configured to control current flow between a first terminal and a second terminal. The selectors are implemented using either PMOS (p-channel metal-oxide-semiconductor) or NMOS (n-channel metal-oxide-semiconductor) transistors, which provide precise current modulation based on applied voltage. The selectors may operate in series or parallel configurations to enhance performance, such as reducing leakage current or improving switching speed. The transistors can be integrated with other components like memory cells or logic gates to form a functional circuit. The use of PMOS or NMOS transistors ensures compatibility with standard CMOS (complementary metal-oxide-semiconductor) fabrication processes, enabling cost-effective manufacturing. This design improves energy efficiency and scalability in advanced computing systems.
22. The computing device of claim 20 , wherein the MOSFET is a FinFET, or a planar MOSFET.
A computing device includes a memory array with memory cells, each having a transistor and a storage element. The transistor is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) that controls current flow between a source and a drain. The storage element stores data as a charge state. The device further includes a control circuit that applies voltages to the transistor to read, write, or erase data in the storage element. The transistor can be either a FinFET (Fin Field-Effect Transistor) or a planar MOSFET. FinFETs use a fin-shaped channel to improve gate control and reduce leakage, while planar MOSFETs have a flat channel structure. The control circuit adjusts voltages based on the transistor type to ensure reliable operation. The memory array may be organized in rows and columns, with word lines and bit lines connecting the transistors. The device may also include error correction circuitry to detect and correct data errors. The transistor type (FinFET or planar MOSFET) is selected based on performance, power, and manufacturing requirements. The control circuit ensures compatibility with both transistor types, allowing flexible design choices.
23. The computing device of claim 20 , wherein the programming operation is performed when the MOSFET is in an off state.
This invention relates to computing devices incorporating metal-oxide-semiconductor field-effect transistors (MOSFETs) and methods for programming such devices. The technology addresses challenges in efficiently and reliably programming MOSFET-based memory cells, particularly in non-volatile memory applications where data retention and low-power operation are critical. The invention describes a computing device with a MOSFET that includes a floating gate or charge storage layer. The device is configured to perform a programming operation on the MOSFET while it is in an off state, meaning the transistor is not conducting current during the programming process. This approach reduces power consumption and minimizes interference with other circuit operations. The programming operation involves applying a voltage to the control gate of the MOSFET to inject or remove charge from the floating gate, thereby altering the transistor's threshold voltage and storing data. The device may also include additional circuitry, such as a voltage generator to supply the necessary programming voltages and a controller to manage the timing and sequence of the programming operation. The invention ensures that the programming process does not disrupt normal circuit functionality, making it suitable for embedded memory applications in microprocessors, microcontrollers, or other integrated circuits. The technique improves energy efficiency and reliability in memory operations.
24. The computing device of claim 20 , wherein the computing device is a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a touchscreen controller, a display, a battery, a processor, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera.
This invention relates to computing devices, specifically wearable or mobile devices, designed to integrate multiple components for enhanced functionality. The device includes at least one of the following: an antenna, touchscreen controller, display, battery, processor, audio codec, video codec, power amplifier, GPS device, compass, Geiger counter, accelerometer, gyroscope, speaker, or camera. These components enable the device to perform various tasks such as communication, navigation, environmental sensing, and multimedia processing. The inclusion of specialized sensors like a Geiger counter allows for radiation detection, while motion sensors like accelerometers and gyroscopes support activity tracking. The device may also incorporate audio and video codecs for media playback and processing, along with a power amplifier for signal transmission. The combination of these components in a compact form factor makes the device suitable for portable applications, providing users with versatile computing and sensing capabilities in a single unit. This design addresses the need for integrated, multifunctional devices that can operate efficiently in diverse environments.
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April 2, 2018
March 15, 2022
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