Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example method includes providing data values stored by a plurality of first registers and a plurality of second registers. The method includes: during a first mode of operation, receiving the data values by groups of first registers of the plurality of the first registers and holding the data values by the plurality of second registers; during a second mode of operation, inverting a data value by one first register of the plurality of first registers at a time and holding the data values by the plurality of second registers; and during a third mode of operation, either inverting the data value by one first register of the plurality of first registers while holding the data values by the plurality of second registers or inverting a data value by one second register of the plurality of second registers while holding the data values by the plurality of first registers.
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1. An apparatus, comprising: an adjustable delay line; and a shift register circuit configured to provide delay control signals to adjust an amount of the adjustable delay line, the shift register circuit including: a plurality of first registers coupled in series to one another, each first register of the plurality of first registers is configured store first data having either a first value or a second value, wherein each first register of the plurality of first registers is configured to provide the first data, wherein an adjacent first register is configured to receive the first data responsive to a shift clock signal; and a plurality of second registers coupled in series to one another, each second register of the plurality of second registers is configured to store second data either the first value or the second value, wherein either one first register or one second register storing data having the first value is configured to receive next data having the second value responsive to the shift clock signal.
This invention relates to a programmable delay circuit used in electronic systems to synchronize signals. The problem addressed is the need for precise, adjustable signal delay in applications like clock synchronization, data alignment, or phase control, where fixed delay lines lack flexibility. The apparatus includes an adjustable delay line and a shift register circuit that controls the delay. The shift register circuit has two sets of registers: a primary set (first registers) and a secondary set (second registers). Both sets are connected in series and store binary data (first or second value). The primary registers pass their stored data to adjacent registers in response to a shift clock signal. The secondary registers operate similarly but with a constraint: if either a primary or secondary register holds the first value, the next incoming data must be the second value. This design allows dynamic adjustment of the delay line by shifting data through the registers, where the stored values determine the delay amount. The secondary registers add a conditional logic layer to ensure controlled data transitions, improving delay resolution and stability. The system enables fine-tuned delay adjustments without external control logic, making it suitable for high-speed digital circuits.
2. The apparatus of claim 1 , wherein the one first register is configured to receive the next data while storing the data when the plurality of second registers are configured to hold data responsive to a first hold control signal.
This invention relates to a data processing apparatus with a register-based data handling system. The apparatus includes a first register and multiple second registers. The first register is designed to receive new data while simultaneously retaining previously stored data. This operation occurs when the second registers are holding data in response to a first hold control signal. The system ensures continuous data flow by allowing the first register to accept incoming data without disrupting the stored data, while the second registers maintain their data states based on the control signal. This configuration is useful in high-speed data processing environments where data must be managed efficiently without interruptions. The apparatus may be part of a larger system where data integrity and timing are critical, such as in digital signal processing or memory management units. The first register's ability to handle new data while retaining old data, combined with the controlled state of the second registers, provides a robust mechanism for data synchronization and transfer. The invention addresses challenges in maintaining data consistency during rapid data transitions, ensuring reliable operation in time-sensitive applications.
3. The apparatus of claim 2 , wherein each second register of the plurality of second registers are configured to store a constant value in a first mode and a second mode.
The invention relates to a digital processing apparatus designed to enhance computational efficiency by utilizing a plurality of registers with configurable storage modes. The apparatus addresses the problem of inflexible register usage in conventional systems, where registers are typically dedicated to either constant values or variable data, limiting performance and resource utilization. The apparatus includes a plurality of first registers and a plurality of second registers. The first registers are configured to store variable data, allowing dynamic processing of changing values during computation. The second registers are uniquely designed to operate in two distinct modes: a first mode where they store constant values, and a second mode where they can also store variable data. This dual-mode functionality enables the apparatus to adapt to different computational requirements, optimizing register usage and reducing the need for additional hardware resources. By allowing the second registers to switch between storing constants and variables, the apparatus improves flexibility and efficiency in digital processing tasks. This design is particularly useful in applications requiring frequent switching between constant and variable data, such as in digital signal processing or arithmetic operations. The apparatus ensures that registers are utilized optimally, minimizing idle cycles and enhancing overall system performance.
4. The apparatus of claim 3 , wherein a group of first registers is configured to receive the second data while storing the first data in the first mode.
This invention relates to a data processing apparatus with a register management system for handling multiple data sets. The apparatus includes a group of registers that can operate in different modes to manage data storage and retrieval efficiently. In a first mode, the registers store a first set of data while simultaneously receiving a second set of data. This dual-function capability allows the apparatus to process incoming data without interrupting ongoing operations, improving throughput and reducing latency. The registers are configured to transition between modes dynamically, ensuring seamless data handling. The apparatus may also include additional components, such as a controller, to manage register operations and ensure data integrity during mode transitions. This design is particularly useful in high-performance computing environments where rapid data processing and minimal downtime are critical. The invention addresses the challenge of efficiently managing multiple data streams in real-time systems, enhancing overall system performance and reliability.
5. The apparatus of claim 3 , wherein the one second register is configured to receive the next data while storing the data, when the plurality of first registers are configured to hold data responsive to a second hold control signal that is a complementary signal of the first hold control signal in a third mode.
This invention relates to a data processing apparatus with a register-based data handling system. The apparatus addresses the challenge of efficiently managing data flow in high-speed processing environments where data must be continuously received and stored without interruption. The system includes a plurality of first registers and at least one second register. The first registers are configured to hold data in response to a first hold control signal, allowing them to temporarily store data when needed. The second register is designed to receive new data while simultaneously storing previously received data, ensuring continuous operation without data loss. In a third mode, the first registers hold data in response to a second hold control signal, which is a complementary signal to the first hold control signal. This complementary signaling ensures synchronized data handling between the registers, preventing conflicts and maintaining data integrity during high-speed operations. The apparatus optimizes data throughput by enabling seamless data transfer and storage, particularly in applications requiring real-time processing and minimal latency. The system's ability to handle data in parallel and maintain synchronization through complementary control signals enhances its reliability and efficiency in demanding computational tasks.
6. The apparatus of claim 5 , further comprising a control signal generator circuit, wherein the control signal generator circuit is configured to provide a reverse signal, wherein the adjacent first register is adjacent is a first direction, wherein one or more second registers of the plurality of second registers are configured to provide the data to an adjacent second register in a second direction responsive to the shift clock signal and further responsive to the reverse signal in an active state, and wherein one or more second registers of the plurality of second registers are configured to provide the data to an adjacent second register in a third direction opposite to the second direction responsive to the shift clock signal and further responsive to the reverse signal in an inactive state.
This invention relates to a data processing apparatus with configurable shift register functionality. The apparatus includes a plurality of first registers and a plurality of second registers, where the second registers are arranged to receive data from the first registers. The apparatus further includes a control signal generator circuit that provides a reverse signal to control the direction of data shifting between the second registers. When the reverse signal is active, the second registers shift data in a second direction to an adjacent second register. When the reverse signal is inactive, the second registers shift data in a third direction, opposite to the second direction. The shifting operation is synchronized by a shift clock signal. This bidirectional shifting capability allows for flexible data routing and processing within the apparatus, enabling efficient data manipulation in different operational modes. The control signal generator circuit dynamically adjusts the data flow direction based on the reverse signal state, enhancing the apparatus's adaptability in various applications.
7. The apparatus of claim 6 , further comprising a shift direction selector configured to provide one of a shift direction signal and its complementary signal to the plurality of second registers responsive to the reverse signal.
This invention relates to digital signal processing systems, specifically apparatuses for managing data flow in shift register-based circuits. The problem addressed is the need for efficient and flexible data shifting operations, particularly in systems requiring both forward and reverse data movement. The apparatus includes a plurality of first registers connected in series for sequential data transfer, and a plurality of second registers connected in parallel to the first registers. The second registers are configured to receive data from the first registers and shift the data in a selected direction. A reverse signal generator produces a reverse signal to control the direction of data shifting. The apparatus further includes a shift direction selector that provides either a shift direction signal or its complementary signal to the second registers based on the reverse signal. This allows the second registers to shift data in either a forward or reverse direction, enhancing flexibility in data processing operations. The system ensures synchronized and controlled data movement, improving efficiency in applications such as digital filters, data buffers, or signal processing pipelines.
8. A method, comprising: providing data values stored by a plurality of first registers and a plurality of second registers, comprising: during a first mode of operation, receiving the data values by a plurality of groups of first registers of the plurality of first registers and holding the data values by the plurality of second registers; during a second mode of operation, inverting a data value by one first register of the plurality of first registers at a time and holding the data values by the plurality of second registers; and during a third mode of operation, either: inverting the data value by one first register of the plurality of first registers while holding the data values by the plurality of second registers, or inverting a data value by one second register of the plurality of second registers while holding the data values by the plurality of first registers.
This invention relates to a method for managing data values in a register-based system, particularly for applications requiring selective inversion of data values while maintaining the integrity of other stored values. The problem addressed is the need for efficient and flexible data manipulation in systems where certain data values must be inverted while others remain unchanged, without requiring full system resets or complex data transfer operations. The method involves a system with multiple first registers and multiple second registers. During a first mode, data values are received and stored by groups of first registers, while the second registers hold their current values. In a second mode, individual first registers invert their stored data values one at a time, while the second registers continue to hold their values unchanged. In a third mode, the system can either invert a data value in a first register while the second registers hold their values, or invert a data value in a second register while the first registers hold their values. This selective inversion capability allows for precise control over data manipulation, ensuring that only the intended data values are modified while others remain stable. The method is particularly useful in digital circuits, processors, or memory systems where selective data inversion is required for operations such as error correction, signal processing, or state management.
9. The method of claim 8 , further comprising: receiving a power supply by another first register of the plurality of first registers; during the first mode, the other first register in a group of the plurality of groups is configured to provide the power supply to the rest of first registers in the group; and during the second mode and the third mode, the other first register is configured to provide the power supply to an adjacent first register of the plurality of first registers coupled in series.
This invention relates to a power distribution system for a plurality of registers arranged in groups, where the system dynamically adjusts power supply distribution based on operational modes. The problem addressed is efficient power management in systems with multiple registers, ensuring reliable power delivery while minimizing energy waste. The system includes a plurality of first registers organized into groups, where each group has a designated register responsible for power distribution. In a first mode, this designated register supplies power to all other registers within its group. In a second and third mode, the designated register instead provides power to only an adjacent register in a series connection. This selective power distribution optimizes energy usage by limiting power flow to only necessary registers during different operational states. The system also includes a plurality of second registers, each coupled to a corresponding first register, where the second registers are configured to receive and process data. The first registers manage power distribution to the second registers based on the operational mode, ensuring that power is directed efficiently. This dynamic power management is particularly useful in systems requiring flexible power allocation, such as digital circuits or memory arrays, where different components may require varying levels of power at different times. The invention improves energy efficiency and reliability by adapting power distribution to the current operational requirements.
10. The method of claim 8 , further comprising: providing a reverse signal during the third mode; providing the data to an adjacent second register in a first direction by at least one second register of the plurality of second registers responsive to a shift clock signal and further responsive to the reverse signal in an active state; and providing the data to another adjacent second register in a second direction by at least one second register of the plurality of second registers responsive to the shift clock signal and further responsive to the reverse signal in an inactive state.
A method for bidirectional data shifting in a register-based system addresses the need for flexible data movement in digital circuits. The system includes a plurality of second registers arranged to transfer data between them. The method operates in multiple modes, with a third mode enabling bidirectional shifting. During this mode, a reverse signal controls the direction of data transfer. When the reverse signal is active, data is shifted in a first direction to an adjacent second register in response to a shift clock signal. When the reverse signal is inactive, data is shifted in a second, opposite direction to another adjacent second register, also in response to the shift clock signal. This bidirectional capability allows for efficient data routing and processing in applications requiring dynamic data flow control, such as digital signal processing or memory management systems. The method ensures that data movement is synchronized with the shift clock signal, maintaining timing integrity across the register network. The reverse signal provides a simple yet effective mechanism to switch between forward and reverse data transfer directions, enhancing the versatility of the register-based system.
11. The method of claim 10 , further comprising: executing a logical operation of one first register and an adjacent first register of the plurality of first registers; and providing the reverse signal responsive, at least in part, to the logical operation; and providing a first hold signal and a second hold signal that is a complementary signal of the first hold signal, responsive, at least in part, to the logical operation; and wherein the plurality of second registers are configured to hold the data values responsive to the second hold signal; and wherein the plurality of first registers are configured to hold the data values responsive to the first hold signal.
This invention relates to a method for managing data values in a processing system, specifically addressing the need for efficient data transfer and synchronization between registers. The method involves executing a logical operation between a first register and an adjacent first register within a set of first registers. The result of this logical operation generates a reverse signal, which is used to control data flow. Additionally, the method produces a first hold signal and a complementary second hold signal based on the logical operation. The second hold signal is used to control a set of second registers, causing them to retain their data values. Similarly, the first hold signal controls the first registers, ensuring they also hold their data values. This approach enables precise synchronization and data retention in processing systems, particularly where coordinated register operations are required. The logical operation between adjacent registers allows for conditional data transfer and control, enhancing system efficiency and reliability. The complementary hold signals ensure that data integrity is maintained during operations, preventing unintended data loss or corruption. This method is particularly useful in digital signal processing, parallel computing, and other applications requiring synchronized register operations.
12. The method of claim 10 , further comprising: providing one of a shift direction signal and its complementary signal to the plurality of second registers responsive to the reverse signal.
A system and method for managing data transfer in a digital circuit, particularly in applications requiring bidirectional data flow or reverse data transfer. The invention addresses the challenge of efficiently controlling data movement in integrated circuits where data must be shifted in both forward and reverse directions, such as in memory systems, data processing units, or communication interfaces. The method involves a plurality of registers configured to store and transfer data sequentially. A control mechanism generates a reverse signal to indicate when data should be shifted in the opposite direction. In response to this reverse signal, a shift direction signal or its complementary signal is provided to a plurality of second registers, which are part of the data transfer pathway. These second registers adjust their operation to facilitate reverse data shifting, ensuring proper data alignment and integrity during bidirectional transfers. The system may include additional registers or control logic to manage data flow, synchronization, and error handling. The invention improves efficiency and reliability in circuits requiring dynamic data direction changes, such as in reconfigurable computing, data pipelines, or memory access systems.
13. The method of claim 8 , further comprising: providing data values stored by the plurality of first registers as a first plurality of control signals; providing data values stored by the plurality of second registers as a second plurality of control signals; adjusting a delay of a phase mixer circuit by providing a plurality of steps of delay adjustment; receiving a first clock signal and a second clock signal at the phase mixer circuit, receiving the first plurality of control signals at a first stage of the phase mixer circuit; providing a first intermediate clock signal by mixing a first weight of the first clock signal of and a second weight of the second clock signal responsive to a first portion of first plurality of control signals; providing a second intermediate clock signal by mixing a third weight of the first clock signal and a fourth weight of the second clock signal responsive to a second portion of first plurality of control signals; receiving the second plurality of control signals and the first and second intermediate clock signals at a second stage of the phase mixer circuit; and providing an output clock signal by mixing a fifth weight of the first intermediate clock signal of and a sixth weight of the second intermediate clock signal, responsive to the second plurality of control signals.
This invention relates to clock signal generation in digital circuits, specifically a method for generating an output clock signal with precise phase and delay adjustments using a multi-stage phase mixer circuit. The problem addressed is the need for fine-grained control over clock signal phase and delay in high-performance digital systems, where traditional phase mixers lack flexibility in adjusting multiple delay steps or weights dynamically. The method involves a phase mixer circuit with two stages, each controlled by separate sets of registers. The first stage receives two input clock signals and generates two intermediate clock signals by mixing them with adjustable weights. The weights are determined by control signals derived from a first set of registers. The second stage then combines these intermediate signals into a final output clock signal, with weights controlled by a second set of registers. The phase mixer circuit supports multiple steps of delay adjustment, allowing precise tuning of the output clock phase. The use of separate register sets for each stage enables independent control of the mixing weights at each stage, enhancing flexibility in clock signal generation. This approach improves clock signal accuracy and adaptability in applications requiring dynamic phase and delay adjustments.
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January 15, 2020
March 22, 2022
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