A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a polymer layer and a redistribution layer. The encapsulant laterally encapsulates the die. The polymer layer is on the encapsulant and the die. The polymer layer includes an extending portion having a bottom surface lower than a top surface of the die. The redistribution layer penetrates through the polymer layer to connect to the die.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A package structure, comprising: a die; an encapsulant, laterally encapsulating the die; a polymer layer on the encapsulant and the die, wherein the polymer layer comprises an extending portion having a bottom surface lower than a top surface of the die, and the polymer layer has a substantially flat top surface, wherein the extending portion of the polymer layer extends into a filler of the encapsulant; and a redistribution layer penetrating through the polymer layer to connect to the die.
This invention relates to semiconductor packaging, specifically addressing challenges in forming reliable electrical connections in advanced integrated circuit (IC) packages. Traditional packaging methods often struggle with maintaining flat surfaces for subsequent processing steps, particularly when integrating redistribution layers (RDLs) that connect to dies embedded in encapsulant materials. The invention solves this by providing a package structure with improved planarization and electrical connectivity. The structure includes a die laterally encapsulated by an encapsulant material. A polymer layer is deposited over both the encapsulant and the die, featuring an extending portion that penetrates into the encapsulant's filler material. This extending portion has a bottom surface lower than the die's top surface, ensuring a substantially flat top surface for the polymer layer. The polymer layer's flatness facilitates precise formation of a redistribution layer (RDL) that penetrates through it to connect with the die, improving electrical performance and manufacturing yield. The design ensures mechanical stability and reliable electrical connections while accommodating variations in die height and encapsulant properties. This approach is particularly useful in fan-out wafer-level packaging (FOWLP) and other advanced packaging technologies where planarization and fine-line RDL formation are critical.
2. The package structure of claim 1 , wherein the extending portion of the polymer layer is laterally surrounded by the filler of the encapsulant.
The invention relates to a package structure for electronic devices, particularly addressing the challenge of protecting sensitive components from environmental damage while maintaining structural integrity. The structure includes a polymer layer with an extending portion that provides mechanical support and electrical insulation. A key feature is the encapsulant, which surrounds the extending portion of the polymer layer with a filler material. This filler ensures uniform stress distribution and prevents delamination or cracking, enhancing the package's reliability. The encapsulant also protects against moisture, contaminants, and mechanical stress, extending the device's lifespan. The polymer layer's extending portion may include conductive or insulating materials, depending on the application, and the filler is selected to match the thermal expansion properties of the polymer to minimize stress. This design is particularly useful in semiconductor packaging, where robust encapsulation is critical for performance and durability. The invention improves upon prior art by ensuring the polymer layer's extending portion is fully encapsulated, reducing failure risks in harsh operating conditions.
3. The package structure of claim 1 , wherein the extending portion of the polymer layer is in contact with an inner sidewall of the filler.
The invention relates to a package structure for electronic devices, particularly addressing issues of moisture ingress and mechanical stability in semiconductor packaging. The structure includes a substrate with an electronic component mounted thereon, a polymer layer covering the component, and a filler material surrounding the polymer layer. The polymer layer has an extending portion that contacts the inner sidewall of the filler, enhancing adhesion and sealing to prevent moisture penetration. This design improves reliability by reducing delamination and cracks, which are common failure points in traditional packaging. The filler material, typically an epoxy or resin, provides structural support and further protects the electronic component from environmental stresses. The extending portion of the polymer layer ensures a continuous barrier, minimizing gaps that could allow moisture or contaminants to reach the component. This configuration is particularly useful in high-reliability applications where environmental resistance is critical, such as in automotive or aerospace electronics. The invention focuses on optimizing the interface between the polymer layer and filler to enhance durability and performance.
4. The package structure of claim 1 , wherein the polymer layer comprises a first portion directly on the die, and a second portion comprising the extending portion which is directly on a portion of the encapsulant, a second thickness of the second portion is larger than a first thickness of the first portion.
This invention relates to semiconductor packaging, specifically addressing the challenge of improving structural integrity and reliability in integrated circuit (IC) packages. The package structure includes a die encapsulated within a protective material, with a polymer layer applied over the die and extending onto the encapsulant. The polymer layer has two distinct portions: a first portion directly on the die and a second portion extending onto the encapsulant. The second portion has a greater thickness than the first portion. This design ensures enhanced adhesion and mechanical stability, reducing stress concentrations at the interface between the die and encapsulant. The thicker extending portion compensates for differences in material properties between the die and encapsulant, preventing delamination and improving overall package robustness. The polymer layer may also serve as a barrier against moisture and contaminants, further protecting the die. The invention is particularly useful in advanced packaging applications where reliability under thermal and mechanical stress is critical.
5. The package structure of claim 1 , wherein the encapsulant has a first pit, and the extending portion of the polymer layer is filled in the first pit.
The invention relates to semiconductor packaging, specifically addressing the challenge of improving structural integrity and reliability in packaged semiconductor devices. The package structure includes a semiconductor chip encapsulated within an encapsulant material, which is typically a mold compound or epoxy resin. A polymer layer is formed over the chip and encapsulant, with an extending portion of the polymer layer filling a first pit in the encapsulant. This pit is a recessed area in the encapsulant surface, and the polymer layer's extension into the pit enhances adhesion between the polymer layer and the encapsulant. The polymer layer may also include a second pit, which can be filled with an additional material, such as a solder mask or underfill material, to further improve mechanical stability. The structure ensures better protection against environmental factors like moisture and mechanical stress, extending the device's lifespan. The polymer layer may be a polyimide or other insulating material, and the encapsulant is typically a rigid material like epoxy molding compound. The invention aims to prevent delamination and cracking, which are common failure modes in semiconductor packaging.
6. The package structure of claim 5 , wherein the polymer layer has a second pit directly over the first pit, and a height of the second pit is less than a height of the first pit.
The invention relates to a package structure with a polymer layer containing pits, addressing issues in semiconductor packaging where precise alignment and structural integrity are critical. The structure includes a substrate with a first pit formed in a surface, and a polymer layer deposited over the substrate. The polymer layer has a second pit directly aligned with the first pit, where the height of the second pit is less than the height of the first pit. This configuration ensures proper alignment and mechanical stability, preventing misalignment or structural failure during manufacturing or operation. The polymer layer may be part of a larger packaging system, such as a chip package, where precise layer-to-layer alignment is essential for electrical and thermal performance. The height difference between the pits allows for controlled material deposition and reduces stress concentrations, improving reliability. The invention is particularly useful in advanced packaging technologies where multiple layers must be precisely aligned to maintain functionality and durability.
7. The package structure of claim 5 , wherein the polymer layer is free of pit directly over the first pit.
The invention relates to a package structure for semiconductor devices, specifically addressing the issue of pit formation in polymer layers used in packaging. The structure includes a substrate with a first pit formed in a surface, a polymer layer deposited over the substrate, and a second pit formed in the polymer layer. The polymer layer is designed to be free of pits directly over the first pit, preventing alignment of defects between the substrate and the polymer layer. This misalignment reduces the risk of electrical or mechanical failures caused by pit propagation. The polymer layer may be formed using a spin-coating or lamination process, and the second pit is positioned offset from the first pit to ensure structural integrity. The invention improves reliability in semiconductor packaging by minimizing defect-induced failures in the polymer layer.
8. The package structure of claim 1 , wherein the redistribution layer comprises a via embedded in the polymer layer and a trace extending on a top surface of the polymer layer; and a base angle of the via is a right angle or an acute angle.
The invention relates to semiconductor packaging, specifically a package structure with an improved redistribution layer (RDL) design. The problem addressed is optimizing electrical connectivity and manufacturing efficiency in integrated circuit (IC) packaging by improving the via and trace configuration within the RDL. The package structure includes a polymer layer with embedded conductive vias and traces. The via is embedded within the polymer layer, while the trace extends along the top surface of the polymer layer. The via has a base angle that is either a right angle or an acute angle, which enhances electrical performance and reduces manufacturing defects. This design ensures reliable electrical connections between different layers of the package while maintaining structural integrity. The via and trace configuration allows for precise routing of electrical signals, improving signal integrity and reducing resistance. The polymer layer provides insulation and mechanical support, while the via and trace materials are conductive, typically metals like copper. This structure is particularly useful in advanced packaging technologies where high-density interconnects are required, such as in system-in-package (SiP) or fan-out wafer-level packaging (FOWLP) applications. The invention aims to improve yield, reliability, and performance in semiconductor packaging by optimizing the RDL geometry.
9. The package structure of claim 8 , wherein a top surface of the via is lower than a top surface of the polymer layer.
The invention relates to semiconductor packaging, specifically addressing the challenge of optimizing electrical connections in advanced packaging structures. The technology involves a package structure with a via extending through a polymer layer, where the top surface of the via is positioned lower than the top surface of the polymer layer. This configuration ensures proper electrical connectivity while maintaining structural integrity. The via is formed within the polymer layer, which acts as an insulating material, and is electrically connected to an underlying conductive layer. The via's recessed top surface prevents short circuits and improves reliability in high-density interconnect applications. The structure may include additional layers, such as a redistribution layer (RDL) or a dielectric layer, to enhance functionality. The polymer layer provides mechanical support and electrical insulation, while the via facilitates vertical electrical connections between different layers of the package. This design is particularly useful in semiconductor devices requiring precise control over electrical pathways and mechanical stability. The recessed via top surface ensures consistent electrical performance and reduces the risk of defects during manufacturing or operation. The overall structure enables efficient signal transmission and power distribution in integrated circuits, addressing the need for compact, high-performance packaging solutions.
10. A package structure, comprising: a first die, comprising a first connector and a first protection layer laterally aside the first connector, the first connector comprises a first seed layer and a first conductive post, wherein the first conductive post is disposed on and laterally surrounded by the first seed layer; an encapsulant, laterally encapsulating the first die; and a redistribution layer (RDL) structure on the first die and the encapsulant, wherein the first seed layer is in contact with the RDL structure.
The invention relates to semiconductor packaging, specifically addressing challenges in electrical connectivity and structural integrity in integrated circuit (IC) packages. Traditional packaging methods often suffer from poor electrical connections or reliability issues due to inadequate seed layer integration and conductive post formation. This invention provides a robust package structure with improved electrical performance and mechanical stability. The package includes a first die with a first connector and a first protection layer adjacent to the connector. The first connector consists of a first seed layer and a first conductive post, where the conductive post is positioned on and laterally enclosed by the seed layer. The seed layer ensures strong adhesion and electrical conductivity between the conductive post and the redistribution layer (RDL) structure. An encapsulant laterally surrounds the first die, providing mechanical support and protection. The RDL structure is formed over both the first die and the encapsulant, with the seed layer directly interfacing with the RDL to ensure reliable electrical connections. This design enhances signal integrity and structural robustness in semiconductor packaging.
11. The package structure of claim 10 , wherein a portion of the first seed layer is laterally sandwiched between the first conductive post and the first protection layer and has a top surface in contact with the RDL structure.
The invention relates to semiconductor packaging, specifically to a package structure with improved electrical and mechanical reliability. The problem addressed is the risk of delamination or cracking at interfaces between conductive posts, seed layers, and protective layers in advanced packaging, which can degrade performance and reliability. The package structure includes a first conductive post formed on a substrate, a first seed layer deposited on the substrate and partially underlying the first conductive post, and a first protection layer covering the first seed layer. A portion of the first seed layer is laterally sandwiched between the first conductive post and the first protection layer, ensuring mechanical stability and electrical continuity. The top surface of the first seed layer is in direct contact with a redistribution layer (RDL) structure, enhancing signal transmission and reducing resistance. The structure may also include a second conductive post and a second seed layer, with the second seed layer partially underlying the second conductive post and extending laterally to contact the first seed layer. This interconnection improves electrical connectivity between the conductive posts. The protection layers may be made of a dielectric material to insulate the seed layers while allowing controlled exposure for electrical connections. The design ensures robust adhesion and minimizes stress concentrations, improving overall package reliability.
12. The package structure of claim 10 , wherein the first conductive post is separated from the first protection layer by the first seed layer therebetween.
A semiconductor package structure includes a substrate with conductive posts and a protection layer. The structure addresses challenges in electrical connectivity and protection in semiconductor packaging, particularly ensuring reliable signal transmission while preventing short circuits or damage. The first conductive post is electrically connected to the substrate and extends through an opening in the first protection layer, which insulates and protects underlying components. A first seed layer is deposited between the first conductive post and the first protection layer, acting as an adhesion and nucleation layer to improve bonding and conductivity. The seed layer ensures proper deposition of the conductive post material while maintaining electrical isolation from the protection layer. This configuration enhances reliability by preventing delamination or corrosion at the interface between the conductive post and the protection layer. The structure may also include additional conductive posts, seed layers, and protection layers to form multi-layered interconnects, enabling complex routing and high-density packaging. The design is particularly useful in advanced semiconductor devices requiring fine-pitch interconnects and robust electrical insulation.
13. The package structure of claim 10 , wherein a portion of the encapsulant is laterally between a polymer layer of the RDL structure and the first protection layer.
The invention relates to semiconductor packaging, specifically addressing the challenge of protecting sensitive components while maintaining electrical connectivity in advanced integrated circuit (IC) packages. The package structure includes a redistribution layer (RDL) structure with polymer layers that route electrical signals, a first protection layer that shields underlying components, and an encapsulant that provides mechanical support and environmental protection. A key feature is that a portion of the encapsulant extends laterally between a polymer layer of the RDL and the first protection layer. This configuration ensures that the encapsulant fills gaps in the structure, preventing voids that could compromise reliability. The RDL structure typically includes conductive traces embedded in polymer layers, while the first protection layer may be a dielectric or passivation layer. The encapsulant, often a mold compound or underfill material, surrounds the IC die and other components, with its lateral extension between the RDL polymer and protection layer enhancing adhesion and structural integrity. This design is particularly useful in fan-out wafer-level packaging (FOWLP) and other high-density packaging applications where minimizing defects and improving robustness are critical. The invention improves yield and long-term reliability by eliminating potential failure points caused by incomplete encapsulation.
14. The package structure of claim 10 , wherein the RDL structure comprises a polymer layer covering the die and the encapsulant, and a surface roughness of a top surface of the polymer layer is less than a surface roughness of a top surface of the encapsulant.
This invention relates to semiconductor packaging, specifically a package structure with a redistribution layer (RDL) that improves surface uniformity for subsequent processing. The problem addressed is the uneven surface topology created by conventional encapsulant materials, which can cause defects in later fabrication steps such as photolithography or bonding. The package structure includes a semiconductor die embedded in an encapsulant material. A polymer layer is applied over both the die and the encapsulant, forming part of the RDL. The polymer layer has a smoother top surface compared to the encapsulant, with a lower surface roughness. This smoother surface reduces defects during subsequent processing, such as when additional conductive traces or bonding pads are formed on the RDL. The polymer layer may also provide mechanical protection and electrical insulation. The RDL may further include conductive traces or vias for interconnecting the die to external components. The smoother surface of the polymer layer ensures better adhesion and alignment for these conductive features, improving overall package reliability. This solution is particularly useful in advanced packaging technologies where fine-pitch interconnects and high-density integration are required.
15. The package structure of claim 10 , further comprising: a second die laterally aside the first die and encapsulated by the encapsulant, the second die comprises a second connector and a second protection layer laterally aside the second connector, the second connector comprises a second seed layer and a second conductive post on the second seed layer; wherein the second seed layer is separated from the RDL structure by the second conductive post therebetween.
The invention relates to semiconductor packaging, specifically addressing challenges in integrating multiple dies within a single package while ensuring reliable electrical connections and protection. The structure includes a first die with a first connector and a first protection layer, where the first connector comprises a seed layer and a conductive post on the seed layer. The first seed layer is separated from a redistribution layer (RDL) structure by the conductive post. The invention further includes a second die positioned laterally adjacent to the first die and encapsulated by an encapsulant. The second die has a second connector and a second protection layer laterally adjacent to the second connector. The second connector comprises a second seed layer and a second conductive post on the second seed layer, with the second seed layer separated from the RDL structure by the second conductive post. This design ensures electrical isolation between the seed layers and the RDL while maintaining structural integrity and protection for the dies. The encapsulant provides mechanical support and environmental protection for the integrated dies. The invention improves packaging efficiency and reliability in multi-die semiconductor devices.
16. A method of forming a package structure, comprising: forming a die comprising a connector and a protection layer laterally aside and surrounding the connector, wherein the connector is formed after forming the protection layer, the connector comprises a seed layer and a conductive post, wherein the conductive post is disposed on and laterally surrounded by the seed layer; forming an encapsulant to laterally encapsulate the die; and forming a RDL structure on the die and the encapsulant, wherein the seed layer is in contact with the RDL structure.
This invention relates to semiconductor packaging, specifically addressing challenges in forming reliable electrical connections between a die and a redistribution layer (RDL) structure. The problem involves ensuring robust electrical contact while protecting the die's active regions during packaging. The method involves forming a die with a connector and a protection layer. The protection layer is formed first, surrounding the connector. The connector itself consists of a seed layer and a conductive post, where the post is disposed on and laterally surrounded by the seed layer. This structure ensures the seed layer provides a stable foundation for the conductive post while the protection layer shields the die's sensitive areas. Next, an encapsulant is formed around the die to provide mechanical support and protection. Finally, a redistribution layer (RDL) structure is formed on both the die and the encapsulant. The seed layer of the connector is in direct contact with the RDL structure, ensuring reliable electrical connectivity between the die and the external circuitry. This approach improves packaging reliability by isolating the connector formation from the protection layer, reducing defects and enhancing electrical performance. The method is particularly useful in advanced semiconductor packaging where precise electrical connections and robust protection are critical.
17. The method of claim 16 , wherein forming the protection layer comprises: forming a protection material layer to cover a conductive pad of the die; patterning the protection material layer to form the protection layer; and performing a curing process to cure the protection layer, wherein a shrinkage rate of protection layer after the curing process with respect to the protection material layer before the curing process ranges from 0 to 2%.
This invention relates to semiconductor packaging, specifically to forming a protection layer over conductive pads on a die to prevent damage during subsequent processing steps. The problem addressed is ensuring reliable electrical connections while minimizing defects caused by stress or misalignment during packaging. The method involves depositing a protection material layer over a conductive pad of the die. This layer is then patterned to form the protection layer, which selectively covers the conductive pad. A curing process is performed to harden the protection layer, with a controlled shrinkage rate of 0 to 2% compared to the original protection material layer. This minimal shrinkage prevents misalignment or stress-induced defects while maintaining structural integrity. The protection layer ensures the conductive pad remains intact during subsequent processing, such as bonding or encapsulation, without compromising electrical connectivity. The process is particularly useful in advanced semiconductor packaging where fine-pitch connections require precise protection to avoid short circuits or pad damage. The controlled curing step ensures dimensional stability, reducing the risk of delamination or cracking.
18. The method of claim 17 , wherein forming the protection material layer comprises performing a soft bake process on the protection material layer, and the curing process is performed at a temperature higher than that of the soft bake process.
This invention relates to semiconductor manufacturing, specifically to methods of forming protection material layers on substrates during fabrication processes. The problem addressed is ensuring proper curing of protection material layers while preventing defects such as cracking or delamination, which can occur due to improper thermal processing. The method involves applying a protection material layer onto a substrate, followed by a soft bake process to partially cure the layer at a lower temperature. This initial soft bake stabilizes the layer before a subsequent curing process, which is performed at a higher temperature to fully cure the material. The higher curing temperature ensures complete hardening of the protection material, while the prior soft bake prevents defects that could arise from rapid or uneven heating. The protection material layer may be applied using techniques such as spin coating or deposition, and the soft bake process is performed at a temperature lower than the final curing temperature. This two-step thermal process ensures uniform curing without damaging the underlying substrate or causing material degradation. The method is particularly useful in semiconductor fabrication where precise control of material properties is critical.
19. The method of claim 17 , wherein patterning the protection material layer comprises forming an opening in the protection layer exposing the conductive pad of the die, and the connector is formed on the conductive pad within the opening of the protection layer.
This invention relates to semiconductor packaging, specifically methods for forming electrical connections to conductive pads on a die while protecting the surrounding area. The problem addressed is ensuring reliable electrical connectivity to die pads while preventing damage to adjacent structures during the connection process. The method involves depositing a protection material layer over the die, which covers the conductive pads and other sensitive areas. The protection layer is then patterned to create openings that expose only the intended conductive pads, leaving the rest of the die protected. A connector, such as a conductive bump or wire, is then formed directly on the exposed conductive pad within the opening. This selective exposure ensures that the connection process does not damage surrounding structures, improving yield and reliability. The protection layer may be made of materials like polyimide or other insulating films, and the patterning can be done using photolithography or other precision techniques. The method is particularly useful in advanced packaging applications where multiple connections must be made to densely packed die pads without compromising structural integrity.
20. The method of claim 19 , wherein forming the connector comprises: forming a seed material layer on the protection layer and filling into the opening; forming a conductive material layer on the seed material layer and filling into the opening; and performing a patterning process to remove portions of the seed material layer and the conductive material layer over a top surface of the protection layer.
This invention relates to semiconductor manufacturing, specifically to forming electrical connectors in integrated circuits. The problem addressed is the reliable formation of conductive connectors through protective layers in semiconductor devices, ensuring proper electrical contact while maintaining structural integrity. The method involves forming a connector through an opening in a protection layer on a semiconductor substrate. First, a seed material layer is deposited on the protection layer, filling the opening. Next, a conductive material layer is formed on the seed material layer, also filling the opening. Finally, a patterning process removes portions of the seed material layer and the conductive material layer from the top surface of the protection layer, leaving the connector only within the opening. The seed material layer facilitates the deposition of the conductive material, ensuring uniform filling of the opening. The patterning step ensures that excess material is removed, preventing short circuits or other defects on the surface. This method improves the reliability of electrical connections in semiconductor devices by ensuring proper filling of the opening and precise removal of unwanted material, enhancing device performance and yield. The process is particularly useful in advanced semiconductor manufacturing where precise conductive pathways are critical.
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December 16, 2019
March 22, 2022
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