The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.
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1. A device comprising: a first source/drain feature disposed in a semiconductor substrate, the first source/drain feature including a first semiconductor material with a first type dopant; a second source/drain feature formed in the semiconductor substrate, the second source/drain feature including a second semiconductor material with a second type dopant, the second source/drain feature further including a doping species, the second semiconductor material being formed of a different semiconductor material than the first semiconductor material, the second type dopant being opposite conductivity of the first type dopant; and a first silicide feature disposed on the first source/drain feature, the first silicide feature including the doping species at a first concentration; and a second silicide feature disposed on the second source/drain feature, the second silicide feature including the doping species at a second concentration that is different than the first concentration.
This invention relates to semiconductor devices, specifically addressing challenges in optimizing source/drain (S/D) contact resistance and performance in advanced transistors. The device includes a semiconductor substrate with two distinct source/drain features. The first source/drain feature is formed from a first semiconductor material doped with a first type dopant (e.g., n-type or p-type). The second source/drain feature is formed from a different semiconductor material, doped with an opposite conductivity type (e.g., p-type if the first is n-type, or vice versa). Additionally, the second source/drain feature includes a specific doping species not present in the first feature. The device further includes silicide features on each source/drain feature. The first silicide feature, formed on the first source/drain, incorporates the doping species at a first concentration. The second silicide feature, formed on the second source/drain, includes the same doping species but at a different concentration. This differential doping in the silicide features helps tailor the electrical properties of the contacts, improving performance by optimizing contact resistance and minimizing parasitic effects. The use of different semiconductor materials and controlled doping in the silicide layers enables enhanced device functionality in advanced semiconductor manufacturing processes.
2. The device of claim 1 , wherein the first concentration is greater than the second concentration.
A device is disclosed for managing fluid concentrations in a system, addressing the need to control and maintain distinct concentration levels in different regions of a fluid flow. The device includes a first region where a fluid is maintained at a first concentration and a second region where the same fluid is maintained at a second concentration. The first concentration is higher than the second concentration, ensuring that the fluid in the first region has a greater concentration of a specific component compared to the fluid in the second region. This differential concentration control is achieved through a separation mechanism that prevents or limits mixing between the two regions, allowing for precise regulation of fluid properties in each area. The device may include structural features such as barriers, valves, or flow channels that facilitate the separation and maintenance of the concentration gradient. The system can be applied in various fields, including chemical processing, medical devices, or environmental control, where maintaining distinct fluid concentrations is critical for optimal performance. The invention ensures efficient operation by preventing unwanted dilution or contamination between the regions, thereby enhancing the reliability and effectiveness of the fluid management process.
3. The device of claim 2 , wherein the first type dopant in a n-type dopant and the second type dopant is a p-type dopant.
This invention relates to semiconductor devices, specifically to a doped semiconductor structure designed to improve electrical performance. The device includes a semiconductor substrate with a first region doped with a first type dopant and a second region doped with a second type dopant. The first type dopant is an n-type dopant, such as phosphorus or arsenic, which introduces free electrons into the semiconductor, while the second type dopant is a p-type dopant, such as boron or aluminum, which introduces free holes. The n-type and p-type regions create a p-n junction, enabling controlled charge carrier movement and rectification. The device may be part of a larger semiconductor structure, such as a transistor or diode, where the doping profile is optimized for specific electrical properties like conductivity, breakdown voltage, or switching speed. The invention addresses challenges in semiconductor manufacturing, such as precise dopant distribution and minimizing defects, to enhance device reliability and performance. The n-type and p-type doping regions are strategically placed to form a functional junction, ensuring efficient charge transport and minimizing leakage currents. This doping configuration is critical for applications in power electronics, integrated circuits, and other semiconductor-based systems.
4. The device of claim 1 , wherein the doping species includes a metal.
A semiconductor device includes a substrate with a doped region containing a metal dopant. The metal dopant is incorporated into the substrate to modify its electrical properties, such as conductivity or carrier concentration. The substrate may be silicon, gallium arsenide, or another semiconductor material. The doped region is formed by introducing the metal dopant through techniques like ion implantation, diffusion, or in-situ doping during material deposition. The metal dopant may include transition metals, rare earth elements, or other metals that alter the semiconductor's electronic behavior. The device may be a transistor, diode, or other semiconductor component where controlled doping enhances performance. The metal dopant concentration and distribution are optimized to achieve desired electrical characteristics, such as improved carrier mobility, reduced leakage current, or enhanced thermal stability. The doping process may involve annealing or other thermal treatments to activate the dopants and repair lattice damage. The device may also include insulating layers, conductive contacts, and other structural features to integrate the doped region into a functional electronic circuit. The metal doping technique is particularly useful in high-performance or specialized semiconductor applications where conventional dopants like boron or phosphorus are insufficient.
5. The device of claim 4 , wherein the metal is selected from the group consisting of Ytterbium (Yb), Erbium (Er), Yttrium (Y), Selenium (Se), Platinum (Pt) and Barium (Ba).
This invention relates to a device incorporating a metal selected from Ytterbium (Yb), Erbium (Er), Yttrium (Y), Selenium (Se), Platinum (Pt), or Barium (Ba). The device addresses challenges in material science and engineering, particularly in applications requiring specific optical, electronic, or catalytic properties. The selected metals are chosen for their unique characteristics, such as high thermal stability, optical absorption, or catalytic activity, which enhance the device's performance in targeted applications. The device may be used in fields like photonics, energy storage, or chemical processing, where precise material properties are critical. The inclusion of these metals allows for tailored functionality, such as improved conductivity, enhanced light emission, or optimized catalytic reactions. The device's design leverages the inherent properties of these metals to achieve superior performance compared to conventional materials. This innovation is particularly useful in advanced manufacturing, where material selection directly impacts efficiency and functionality. The metals' distinct attributes enable the device to operate effectively in demanding environments, ensuring reliability and durability.
6. The device of claim 1 , wherein the first source/drain feature includes the doping species at a third concentration that is different than first concentration, and wherein the second source/drain feature includes the doping species at a fourth concentration that is different than second concentration.
This invention relates to semiconductor devices, specifically to the doping of source/drain features in transistors to improve performance. The problem addressed is optimizing doping concentrations in source/drain regions to enhance device functionality while maintaining compatibility with existing fabrication processes. The device includes a first source/drain feature and a second source/drain feature, each doped with a specific species. The first feature has a doping concentration distinct from the second feature, allowing for tailored electrical properties. The first feature is doped at a third concentration, which differs from a first concentration used elsewhere in the device, while the second feature is doped at a fourth concentration, distinct from a second concentration. This differential doping enables precise control over carrier mobility, conductivity, and threshold voltage, improving overall device performance. The doping concentrations are adjusted to optimize the device for specific applications, such as high-speed logic or low-power operation. The technique ensures that the source/drain regions are doped independently, avoiding uniformity constraints that could degrade performance. This approach enhances flexibility in semiconductor design, allowing for better integration into advanced integrated circuits. The invention is particularly useful in finFETs, nanowire transistors, and other advanced transistor architectures where precise doping control is critical.
7. The device of claim 1 , wherein the first semiconductor material includes carbon and the second semiconductor material includes germanium.
This invention relates to semiconductor devices, specifically those incorporating multiple semiconductor materials to enhance performance. The device comprises a first semiconductor material containing carbon and a second semiconductor material containing germanium, forming a heterojunction structure. The combination of carbon and germanium in the semiconductor materials is designed to improve electrical properties such as carrier mobility, bandgap engineering, or thermal stability. The device may be used in high-speed electronics, optoelectronic applications, or advanced transistors where precise control of material properties is critical. The use of carbon in the first semiconductor material provides high electron mobility and thermal conductivity, while germanium in the second semiconductor material offers compatibility with silicon-based fabrication processes and tunable bandgap characteristics. The heterojunction formed between these materials enables efficient charge carrier transport and reduces leakage currents, improving overall device efficiency. This configuration is particularly useful in applications requiring high-performance semiconductor components with optimized electrical and thermal properties.
8. A device comprising: a first source/drain feature disposed in a semiconductor substrate, the first source/drain feature including a first semiconductor material with an n-type dopant; a second source/drain feature formed in the semiconductor substrate, the second source/drain feature including a second semiconductor material with a p-type dopant; and a first silicide feature disposed on the first source/drain feature, the first silicide feature including a metal doping species at a first concentration; and a second silicide feature disposed on the second source/drain feature, the second silicide feature including the metal doping species at second concentration that is less than the first concentration.
The invention relates to semiconductor devices, specifically addressing the challenge of optimizing contact resistance in transistors with different source/drain doping types. In semiconductor manufacturing, transistors with n-type and p-type source/drain regions often require different silicide contact materials to achieve low contact resistance. The invention describes a device with a first source/drain feature in a semiconductor substrate, containing an n-type doped semiconductor material, and a second source/drain feature with a p-type doped semiconductor material. A first silicide feature is formed on the n-type source/drain, incorporating a metal doping species at a first concentration. A second silicide feature is formed on the p-type source/drain, also containing the same metal doping species but at a lower concentration than the first silicide. This differential doping in the silicide features allows for tailored contact resistance optimization for both n-type and p-type regions, improving overall device performance. The invention ensures compatibility with existing semiconductor fabrication processes while enhancing electrical characteristics.
9. The device of claim 8 , wherein the first source/drain feature includes the metal doping species at a third concentration that is different than the first concentration, and wherein the second source/drain feature includes the metal doping species at a fourth concentration that is different than the second concentration.
This invention relates to semiconductor devices, specifically to a transistor structure with asymmetrically doped source/drain regions. The problem addressed is optimizing transistor performance by controlling the distribution of metal doping species in the source and drain regions to enhance electrical properties such as conductivity, threshold voltage, and reliability. The device includes a transistor with a gate structure and two source/drain features. The first source/drain feature is doped with a metal species at a first concentration, while the second source/drain feature is doped with the same metal species at a second concentration. The key innovation is that the first source/drain feature also includes the metal doping species at a third concentration, different from the first concentration, and the second source/drain feature includes the metal doping species at a fourth concentration, different from the second concentration. This asymmetric doping profile allows for fine-tuning of the transistor's electrical characteristics, such as reducing contact resistance, improving carrier mobility, or adjusting threshold voltage asymmetry. The metal doping species may include elements like nickel, cobalt, or platinum, which are introduced during fabrication to modify the work function or enhance conductivity. The different concentrations in each source/drain feature enable tailored performance for specific applications, such as high-speed logic or low-power circuits. This approach improves device efficiency and reliability compared to conventional uniform doping techniques.
10. The device of claim 8 , further comprising: a fin structure disposed on the semiconductor substrate; a high-k dielectric layer disposed on the fin structure; and a metal gate electrode disposed on the high-k dielectric layer.
This invention relates to semiconductor devices, specifically fin-based transistors used in advanced integrated circuits. The problem addressed is improving the performance and reliability of fin field-effect transistors (FinFETs) by optimizing the gate structure. The device includes a semiconductor substrate with a fin structure extending upward from the substrate. A high-k dielectric layer is deposited on the fin structure to enhance gate capacitance and reduce leakage current. A metal gate electrode is formed on the high-k dielectric layer to control the channel region within the fin. The fin structure provides a three-dimensional channel, improving electrostatic control and reducing short-channel effects compared to planar transistors. The high-k dielectric layer ensures efficient gate coupling while minimizing gate leakage, and the metal gate electrode provides low resistance and compatibility with advanced manufacturing processes. This configuration enhances transistor performance, scalability, and power efficiency, making it suitable for high-density integrated circuits. The invention builds on prior finFET designs by integrating a high-k dielectric and metal gate to address challenges in gate leakage and threshold voltage control.
11. The device of claim 8 , further comprising a dielectric isolation structure disposed in the semiconductor substrate, and wherein one of the first and second source/drain features interfaces with the dielectric isolation structure.
A semiconductor device includes a fin structure formed on a semiconductor substrate, where the fin structure has a first source/drain feature and a second source/drain feature. The device further includes a gate structure that wraps around a channel region of the fin structure, where the gate structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer is disposed on the channel region, and the gate electrode is disposed on the gate dielectric layer. The device also includes a dielectric isolation structure disposed in the semiconductor substrate, where one of the first and second source/drain features interfaces with the dielectric isolation structure. The dielectric isolation structure may electrically isolate the source/drain feature from adjacent regions of the substrate, improving device performance and reducing leakage current. The fin structure may be part of a FinFET or other multi-gate transistor architecture, where the gate structure controls current flow between the source/drain features. The dielectric isolation structure may be formed using shallow trench isolation (STI) or other isolation techniques to define active regions in the substrate. This configuration enhances device scalability and integration density while maintaining electrical isolation.
12. The device of claim 8 , wherein the second source/drain feature has a greater concentration of the metal doping species than the first source drain feature.
This invention relates to semiconductor devices, specifically to a field-effect transistor (FET) with asymmetrically doped source/drain regions. The problem addressed is improving device performance by optimizing carrier mobility and reducing parasitic resistance in advanced semiconductor structures. The device includes a semiconductor channel with first and second source/drain features formed on opposite sides. The first source/drain feature has a lower concentration of a metal doping species compared to the second source/drain feature. This asymmetric doping profile enhances electrical characteristics by improving carrier injection efficiency at the second source/drain while maintaining low resistance at the first source/drain. The metal doping species may include elements like nickel, cobalt, or platinum, which modify the work function and conductivity of the semiconductor material. The channel may be formed from silicon, silicon-germanium, or other semiconductor compounds, and the doping concentration gradient is controlled during fabrication to achieve the desired performance benefits. This asymmetric doping approach is particularly useful in high-performance transistors where balanced electrical properties are critical for optimal operation.
13. The device of claim 8 , wherein the second source/drain feature has a greater concentration of the metal doping species than the second silicide feature.
A semiconductor device includes a substrate with a first source/drain feature and a second source/drain feature, each formed in the substrate. The first source/drain feature is doped with a first metal doping species, and the second source/drain feature is doped with a second metal doping species. A first silicide feature is formed on the first source/drain feature, and a second silicide feature is formed on the second source/drain feature. The second source/drain feature has a higher concentration of the second metal doping species compared to the concentration of the second metal doping species in the second silicide feature. This configuration improves electrical conductivity and reduces contact resistance in the semiconductor device. The device may also include a gate structure adjacent to the first and second source/drain features, with a gate dielectric layer and a gate electrode. The first and second source/drain features may be formed using an epitaxial growth process, and the silicide features may be formed by reacting a metal layer with the underlying source/drain features. The differing doping concentrations between the source/drain features and the silicide features optimize device performance by enhancing carrier mobility and reducing parasitic resistance.
14. The device of claim 8 , wherein the metal doping species includes Ytterbium (Yb).
This invention relates to a doped semiconductor device, specifically a gallium nitride (GaN) based device, designed to improve performance by incorporating a rare-earth metal doping species. The device addresses the challenge of enhancing carrier mobility and reducing defect-related losses in GaN-based semiconductors, which are widely used in high-power and high-frequency applications. The doping species, which includes Ytterbium (Yb), is introduced into the semiconductor material to modify its electrical and optical properties. Yb doping is particularly effective in reducing threading dislocation densities and improving carrier lifetime, leading to higher efficiency and reliability in the device. The device may be a transistor, light-emitting diode (LED), or other semiconductor component where GaN is used as the base material. The doping process involves precise control of Yb concentration to avoid clustering and ensure uniform distribution within the semiconductor lattice. This results in improved charge transport characteristics and reduced thermal generation of carriers, making the device suitable for high-performance applications such as power electronics and optoelectronics. The invention focuses on optimizing the doping process to achieve the desired material properties without compromising the structural integrity of the GaN lattice.
15. A device comprising: a first source/drain feature disposed in a semiconductor substrate, the first source/drain feature including a first semiconductor material with a first type dopant, the first source/drain feature including a doping species at a first concentration; a second source/drain feature formed in the semiconductor substrate, the second source/drain feature including a second semiconductor material with a second type dopant, the second type being opposite the first type, the second source/drain feature including the doping species at a second concentration; and a first silicide feature disposed on the first source/drain feature, the first silicide feature including the doping species at a third concentration that is different than the first concentration; and a second silicide feature disposed on the second source/drain feature, the second silicide feature including the doping species at a fourth concentration that is different than the second concentration.
This invention relates to semiconductor devices, specifically addressing challenges in optimizing source/drain (S/D) regions and silicide contacts in integrated circuits. The device includes a semiconductor substrate with first and second S/D features, each containing different semiconductor materials and opposite-type dopants (e.g., n-type and p-type). The first S/D feature incorporates a first semiconductor material with a first dopant type at a first concentration of a doping species, while the second S/D feature uses a second semiconductor material with an opposite-type dopant at a second concentration of the same doping species. The device further includes first and second silicide features formed on the respective S/D features. The first silicide feature contains the doping species at a third concentration, distinct from the first concentration in the underlying S/D feature, while the second silicide feature contains the doping species at a fourth concentration, distinct from the second concentration in its underlying S/D feature. This configuration allows independent tuning of dopant concentrations in the S/D regions and their corresponding silicide contacts, improving electrical performance and reliability by optimizing carrier mobility and contact resistance. The invention is particularly useful in advanced semiconductor nodes where precise control of dopant profiles is critical for device functionality.
16. The device of claim 15 , wherein the second source/drain feature includes more than 70% of the concentration of the doping species across the second source/drain feature and the second silicide feature.
This invention relates to semiconductor devices, specifically to the doping and silicide formation in source/drain regions of transistors. The problem addressed is achieving uniform doping distribution and efficient silicide formation in source/drain features to improve electrical performance and reliability. The device includes a semiconductor substrate with a transistor structure having source/drain features and silicide features formed thereon. The second source/drain feature, which may be part of a p-type or n-type transistor, contains a doping species distributed such that more than 70% of the total concentration of the doping species is present within the second source/drain feature itself, rather than in the adjacent second silicide feature. This ensures that the silicide feature does not excessively consume the doping species, which could degrade electrical contact resistance and device performance. The doping species may include elements such as boron, phosphorus, arsenic, or other dopants used in semiconductor manufacturing. The silicide feature, typically formed from a metal such as nickel, cobalt, or titanium, is engineered to minimize doping species diffusion into it, maintaining high doping concentration in the source/drain region for optimal conductivity. This design improves transistor performance by ensuring low resistance contacts and stable doping profiles.
17. The device of claim 15 , wherein the first source/drain feature includes more than 70% of the concentration of the doping species across the first source/drain feature and the first silicide feature.
This invention relates to semiconductor devices, specifically to the doping concentration distribution in source/drain features and their associated silicide regions. The problem addressed is optimizing the doping profile in source/drain regions to improve electrical performance while maintaining reliable contact resistance. The device includes a semiconductor substrate with a first source/drain feature and a first silicide feature formed thereon. The first source/drain feature is doped with a specific doping species, and the first silicide feature is formed on the first source/drain feature to provide electrical contact. A key aspect is that the first source/drain feature contains more than 70% of the total concentration of the doping species across both the first source/drain feature and the first silicide feature. This ensures that the majority of the doping species remains in the source/drain region rather than diffusing into the silicide, which could degrade device performance. The doping species may be uniformly distributed or graded within the first source/drain feature. The first silicide feature may be formed from a metal such as nickel, cobalt, or titanium, and the first source/drain feature may be doped with boron, phosphorus, or arsenic, depending on the device requirements. The device may also include additional features such as a gate structure, spacers, and other source/drain features with similar or different doping profiles. The controlled doping distribution helps maintain low contact resistance while preventing excessive dopant diffusion into the silicide, which could lead to junction leakage or reliability issues.
18. The device of claim 15 , wherein the first concentration is greater than the third concentration, and wherein the second concentration is less than the fourth concentration.
This invention relates to a device for controlling fluid concentrations in a system, addressing the challenge of maintaining precise concentration levels in different fluid streams. The device includes a first fluid stream with a first concentration of a substance and a second fluid stream with a second concentration of the same substance. The device also has a third fluid stream with a third concentration and a fourth fluid stream with a fourth concentration. The device is designed to ensure that the first concentration is greater than the third concentration, while the second concentration is less than the fourth concentration. This configuration allows for controlled mixing or separation of fluids to achieve desired concentration levels in different parts of the system. The device may include sensors, valves, or other mechanisms to monitor and adjust the concentrations dynamically. The invention is particularly useful in applications requiring precise fluid concentration management, such as chemical processing, pharmaceutical manufacturing, or environmental monitoring.
19. The device of claim 18 , wherein the first type dopant is a n-type dopant and the second type dopant is a p-type dopant, and wherein the doping species includes a metal.
This invention relates to semiconductor devices, specifically to a doped semiconductor structure designed to improve electrical performance. The problem addressed is the need for efficient charge carrier management in semiconductor materials, particularly in devices requiring precise control over conductivity and carrier type. The device includes a semiconductor substrate with a first region doped with a first type dopant and a second region doped with a second type dopant. The first type dopant is an n-type dopant, which introduces free electrons, while the second type dopant is a p-type dopant, which introduces holes. The doping species in both regions includes a metal, which enhances dopant activation and stability. The first and second regions are positioned to form a junction, enabling controlled charge carrier movement. The metal dopant improves electrical conductivity and reduces thermal degradation, making the device suitable for high-performance applications such as transistors, diodes, or sensors. The structure ensures efficient charge separation and minimizes leakage currents, improving overall device efficiency.
20. The device of claim 15 , further comprising a gate stack associated with one of the first and second source/drain features, the gate stack including: a high-k dielectric layer disposed on the semiconductor substrate; a metal gate electrode disposed on the high-k dielectric layer; and a sidewall spacer disposed along a sidewall of the gate stack, the sidewall spacer having a bottom surface facing the semiconductor substrate, and wherein the one of the first and second source/drain features interfaces with the bottom surface of the sidewall spacer.
This invention relates to semiconductor devices, specifically to an improved gate stack structure for transistors. The problem addressed is optimizing the interface between source/drain features and the gate stack to enhance device performance and reliability. The device includes a semiconductor substrate with first and second source/drain features formed thereon. A gate stack is associated with one of these source/drain features. The gate stack comprises a high-k dielectric layer directly on the semiconductor substrate, a metal gate electrode on the high-k dielectric layer, and a sidewall spacer along the gate stack's sidewall. The sidewall spacer has a bottom surface facing the substrate, and the source/drain feature directly interfaces with this bottom surface. This configuration improves electrical contact and reduces parasitic resistance, enhancing overall transistor efficiency. The high-k dielectric ensures strong gate control, while the metal gate electrode provides low resistance and compatibility with advanced manufacturing processes. The sidewall spacer's design minimizes leakage and improves structural integrity. This structure is particularly useful in advanced CMOS technologies where precise control of the gate-to-source/drain interface is critical for performance and scalability.
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December 17, 2019
March 29, 2022
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