A method includes: receiving a first result obtained by performing BIP check on a sent first to-be-checked bit stream; performing BIP check on a received second to-be-checked bit stream to obtain a second result, where the second to-be-checked bit stream is a bit stream received by a receiving device after the first to-be-checked bit stream is transmitted; detecting a type of a control block in the second to-be-checked bit stream, and determining a third result based on impact of the type of the control block on a BIP check result; comparing the first result, the second result, and the third result; and if the first result is different from the second result, the first result is different from the third result, and the second result is different from a predetermined result, determining that a bit error occurs when the first to-be-checked bit stream is transmitted.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method, comprising: receiving, by a receiving device, a first result, wherein the first result is obtained by a sending device by performing a first bit interleaving parity (BIP) check on a first to-be-checked bit stream that is sent by the sending device to the receiving device; receiving, by the receiving device, a second to-be-checked bit stream after the first to-be-checked bit stream is sent by the sending device, wherein the first to-be-checked bit stream is the same as the second to-be-checked bit stream, or one or more blocks are added to or deleted from the first to-be-checked bit stream during transmission of the first to-be-checked bit stream, to form the second to-be-checked bit stream that is received by the receiving device; performing, by the receiving device, a second BIP check on the second to-be-checked bit stream to obtain a second result; detecting, by the receiving device, a type of a control block comprised in the second to-be-checked bit stream; determining, by the receiving device, a third result based on impact of the type of the control block on the second result; comparing, by the receiving device, the first result, the second result, and the third result; and in response to determining that the first result is different from the second result, the first result is different from the third result, and the second result is different from a predetermined result, determining that a bit error occurred when the first to-be-checked bit stream was transmitted by the sending device.
This invention relates to error detection in digital communication systems, specifically addressing the challenge of accurately identifying bit errors in transmitted data streams when control blocks may affect parity checks. The method involves a receiving device analyzing two versions of a bit stream: an original version sent by a sending device and a received version that may differ due to transmission errors or modifications. The sending device performs a first bit interleaving parity (BIP) check on the original bit stream and sends the result to the receiving device. The receiving device then performs a second BIP check on the received bit stream. The receiving device also detects the type of control block present in the received bit stream to assess its impact on the BIP check result. The receiving device compares the first BIP result, the second BIP result, and an adjusted result accounting for the control block type. If the first and second results differ, the first and adjusted results differ, and the second result does not match a predetermined value, the receiving device concludes that a bit error occurred during transmission. This approach improves error detection reliability by accounting for control block influences on parity checks.
2. The method according to claim 1 , further comprising: in response to detecting an invalid block or an error block in the second to-be-checked bit stream, determining that a bit error occurred when the first to-be-checked bit stream was transmitted by the sending device.
This invention relates to error detection in digital communication systems, specifically for identifying transmission errors in bit streams. The method involves comparing two bit streams—a first bit stream received by a receiving device and a second bit stream generated by the receiving device based on the first bit stream. If the second bit stream contains an invalid block or an error block, the method concludes that a bit error occurred during transmission of the first bit stream by the sending device. The comparison process ensures data integrity by verifying the consistency between the received and regenerated bit streams. The method is particularly useful in systems where reliable data transmission is critical, such as in wireless communications, data storage, or network protocols. By detecting errors in the second bit stream, the system can trigger corrective actions, such as retransmission or error correction, to maintain data accuracy. The approach leverages block-based validation to efficiently identify transmission errors without requiring extensive computational resources. This technique enhances reliability in digital communication by providing a robust mechanism for error detection.
3. The method according to claim 1 , wherein the type of the control block is a local fault block type, a remote fault block type, an idle block type, or a low power idle block type.
This invention relates to a method for managing control blocks in a computing system, particularly for optimizing resource allocation and power consumption. The method involves classifying control blocks into different types to improve system efficiency. The control blocks are categorized as local fault blocks, remote fault blocks, idle blocks, or low power idle blocks. Local fault blocks handle errors detected within the same processing unit, while remote fault blocks manage errors detected in other units. Idle blocks represent inactive processing units, and low power idle blocks are idle units operating in a reduced power state to conserve energy. The method dynamically assigns these types based on system conditions, such as error detection, workload distribution, or power requirements, to enhance performance and reduce power consumption. This classification allows the system to prioritize error handling, allocate resources efficiently, and transition idle units to low-power states when appropriate, ensuring optimal operation under varying conditions. The approach is particularly useful in multi-core processors, distributed systems, or embedded devices where resource management and power efficiency are critical.
4. The method according to claim 3 , wherein the predetermined result is 00000000 or 01010010 when it is detected that the type of the control block in the second to-be-checked bit stream is the local fault block type and the second to-be-checked bit stream comprises consecutive local fault blocks.
This invention relates to error detection in data streams, specifically for identifying and handling local fault blocks within a bit stream. The problem addressed is the need to accurately detect and process sequences of local fault blocks to ensure data integrity and system reliability. The method involves analyzing a second to-be-checked bit stream to determine if it contains consecutive local fault blocks. If detected, the method assigns a predetermined result value of either 00000000 or 01010010 to the control block within the bit stream. This result is used to flag or handle the detected fault blocks appropriately, ensuring that the system can take corrective action or log the error for further analysis. The method builds upon a prior step of identifying the type of control block in the bit stream, specifically confirming it as a local fault block type before applying the predetermined result. The predetermined result values are chosen to uniquely identify the presence of consecutive local fault blocks, distinguishing them from other error conditions or normal data patterns. This approach enhances error detection accuracy and system robustness in environments where local fault blocks may occur, such as in data storage, transmission, or processing systems.
5. The method according to claim 3 , wherein the predetermined result is 00000000 or 10010010 when it is detected that the type of the control block in the second to-be-checked bit stream is the remote fault block type and the second to-be-checked bit stream comprises consecutive remote fault blocks.
This invention relates to error detection and correction in data transmission systems, specifically for identifying and handling remote fault conditions in bit streams. The problem addressed is the need to accurately detect and process consecutive remote fault blocks within a bit stream to ensure reliable data integrity and system performance. The method involves analyzing a second to-be-checked bit stream to determine the type of control block present. If the control block is identified as a remote fault block type, the method further checks whether the bit stream contains consecutive remote fault blocks. Based on this detection, the method outputs a predetermined result of either 00000000 or 10010010. This result is used to signal the presence of consecutive remote fault blocks, enabling downstream systems to take appropriate corrective actions, such as error recovery or system alerts. The method builds upon a broader process of checking bit streams for specific patterns or conditions, ensuring that remote fault conditions are properly flagged and managed. By distinguishing between isolated and consecutive remote fault blocks, the system can improve error handling efficiency and reduce false positives in fault detection. This approach is particularly useful in communication protocols or storage systems where uninterrupted data flow is critical.
6. The method according to claim 3 , wherein determining the third result based on the impact of the type of the control block on the second result comprises: in response to detecting that the type of the control block in the second to-be-checked bit stream is the local fault block type and a quantity of local fault blocks in the second to-be-checked bit stream is 1, reversing bit values at second, fourth, and seventh bit positions in the second result, to obtain the third result.
This invention relates to error detection and correction in digital systems, specifically for handling control blocks in bit streams to improve fault detection accuracy. The problem addressed is the need to accurately process different types of control blocks, such as local fault blocks, to ensure reliable error correction. The method involves analyzing a bit stream containing control blocks to determine the type of each block. When a local fault block is detected and there is only one such block in the bit stream, the method modifies the error detection result by reversing specific bit positions. Specifically, the second, fourth, and seventh bits of the intermediate error detection result are inverted to produce the final corrected result. This adjustment accounts for the unique characteristics of local fault blocks, ensuring accurate error correction. The process includes identifying the control block type, counting the number of local fault blocks, and applying the bit reversal only under specific conditions to avoid unnecessary modifications. This selective bit inversion improves the reliability of error detection in systems where local fault blocks are present, reducing false positives and ensuring correct data integrity. The method is particularly useful in digital communication systems, storage devices, and other applications where error detection and correction are critical.
7. The method according to claim 3 , wherein determining the third result based on impact of the type of the control block on the second result comprises: in response to detecting that the type of the control block in the second to-be-checked bit stream is the remote fault block type and a quantity of remote fault blocks in the second to-be-checked bit stream is 1, reversing bit values at first, fourth, and seventh bit positions in the second result, to obtain the third result.
This invention relates to error detection and correction in digital systems, specifically for handling remote fault blocks in bit streams. The problem addressed is the accurate identification and correction of errors in data transmission or storage systems where remote fault blocks may introduce specific error patterns. Remote fault blocks are control blocks that indicate errors originating from a remote source, and their presence can affect the interpretation of error correction results. The method involves processing a bit stream to detect and correct errors, with a focus on remote fault blocks. When a remote fault block is detected in the bit stream and there is exactly one such block, the method modifies the error correction result by reversing the bit values at specific positions (first, fourth, and seventh) in the corrected data. This adjustment accounts for the impact of the remote fault block on the error correction process, ensuring accurate data recovery. The technique is particularly useful in systems where remote faults can distort error patterns, such as in communication protocols or storage systems with distributed error correction mechanisms. The method improves reliability by dynamically adapting the correction process based on the type and quantity of detected remote fault blocks.
8. The method according to claim 3 , wherein determining the third result based on the impact of the type of the control block on the second result comprises: in response to detecting that the type of the control block in the second to-be-checked bit stream is the idle block or the low power idle block, reversing bit values at second, third, fourth, and fifth bit positions in the second result, to obtain the third result.
This invention relates to data processing in communication systems, specifically methods for handling control blocks in bit streams to ensure accurate data interpretation. The problem addressed is the need to correctly process different types of control blocks, such as idle blocks or low power idle blocks, which may require specific bit manipulations to maintain data integrity. The method involves analyzing a bit stream containing control blocks and determining their type. If the control block is identified as an idle block or a low power idle block, the method reverses the bit values at specific positions (second, third, fourth, and fifth) in the processed result. This bit reversal ensures that the final output accurately reflects the intended data, compensating for the unique characteristics of these control block types. The process is part of a broader method for validating and transforming bit streams, where intermediate results are adjusted based on control block types to produce a final, corrected output. This approach is particularly useful in systems where control blocks may introduce distortions that need to be systematically corrected to maintain reliable communication.
9. The method according to claim 1 , further comprising: receiving a first parity value collected by the sending device, wherein the first parity value indicates a quantity of blocks in the first to-be-checked bit stream; collecting a quantity of blocks in the second to-be-checked bit stream, and generating a second parity value; and in response to determining the first result is the same as the third result and the first parity value is the same as the second parity value, determining that a bit error occurred when the first to-be-checked bit stream was transmitted.
This invention relates to error detection in digital communication systems, specifically for identifying bit errors during transmission of data streams. The method involves comparing two bit streams—a first to-be-checked bit stream received by a receiving device and a second to-be-checked bit stream generated by the receiving device—to detect discrepancies. The receiving device processes the first bit stream to produce a first result and generates the second bit stream to produce a third result. If these results match, the method further checks parity values to confirm transmission integrity. The sending device collects a first parity value representing the quantity of blocks in the first bit stream, while the receiving device collects a second parity value for the second bit stream. If both the results and parity values match, the method concludes that a bit error occurred during transmission of the first bit stream. This approach enhances error detection by combining result comparison with parity validation, ensuring higher accuracy in identifying transmission errors. The method is particularly useful in systems where data integrity is critical, such as telecommunications, networking, or storage applications.
10. The method according to claim 1 , further comprising: after determining that a bit error occurred when the first to-be-checked bit stream was transmitted, accumulating a quantity of bit errors occurring in a preset time period; calculating a bit error rate based on a total quantity of bit errors accumulated in the preset time period and a total quantity of received bits; and sending the total quantity of bit errors or the bit error rate to the sending device.
This invention relates to error detection and reporting in digital communication systems, specifically addressing the need to monitor and report bit errors during data transmission. The method involves detecting bit errors in a received bit stream and, upon identifying an error, accumulating the number of errors that occur within a predefined time window. The system then calculates a bit error rate by dividing the total accumulated errors by the total number of received bits during that period. This error rate or the raw error count is then transmitted back to the sending device, enabling it to assess transmission quality and potentially adjust its operations. The method ensures real-time monitoring of communication reliability, allowing for dynamic adjustments to improve data integrity. The invention is particularly useful in high-speed or error-sensitive communication systems where maintaining low error rates is critical. By providing feedback on error rates, the system helps optimize transmission parameters and reduce data loss. The approach is applicable to various communication protocols and can be integrated into existing error detection frameworks to enhance performance.
11. An apparatus, comprising: a transceiver, configured to: receive a first result, wherein the first result is obtained by a sending device by performing first bit interleaving parity (BIP) check on a first to-be-checked bit stream that is sent by the sending device to the apparatus; and receive a second to-be-checked bit stream after the first to-be-checked bit stream is sent by the sending device, wherein the first to-be-checked bit stream is the same as the second to-be-checked bit stream, or one or more blocks are added to or deleted from the first to-be-checked bit stream during transmission of the first to-be-checked bit stream, to form the second to-be-checked bit stream that is received by the apparatus; a processor; and a non-transitory computer-readable storage medium storing a program to be executed by the processor, the program including instructions for: performing a second BIP check on the second to-be-checked bit stream, to obtain a second result; detecting a type of a control block in the second to-be-checked bit stream; and determining a third result based on impact of the type of the control block on the second result; comparing the first result, the second result, and the third result; and in response to the first result being different from the second result, the first result being different from the third result, and the second result being different from a predetermined result, determine that a bit error occurred when the first to-be-checked bit stream was transmitted.
This invention relates to error detection in digital communication systems, specifically addressing bit error detection in transmitted bit streams. The apparatus includes a transceiver that receives a first result from a sending device, which is obtained by performing a first bit interleaving parity (BIP) check on a first to-be-checked bit stream sent to the apparatus. The transceiver also receives a second to-be-checked bit stream after the first bit stream is sent, where the second bit stream may be identical to the first or may have blocks added or deleted during transmission. The apparatus further includes a processor and a non-transitory storage medium storing a program executed by the processor. The program performs a second BIP check on the second bit stream to obtain a second result, detects the type of control block in the second bit stream, and determines a third result based on the impact of the control block type on the second result. The first, second, and third results are compared. If the first result differs from the second, the first differs from the third, and the second differs from a predetermined result, the apparatus determines that a bit error occurred during transmission of the first bit stream. This method enhances error detection by accounting for control block variations and ensuring accurate identification of transmission errors.
12. The apparatus according to claim 11 , wherein the type of the control block is a local fault block type, a remote fault block type, an idle block type, or a low power idle block type.
This invention relates to a control apparatus for managing operational states in a system, particularly addressing the need for efficient state transitions and power management. The apparatus includes a control block that dynamically adjusts its operational mode based on system conditions. The control block can be configured as a local fault block, a remote fault block, an idle block, or a low power idle block. A local fault block detects and handles faults within its immediate domain, while a remote fault block manages faults originating from external sources. The idle block maintains a standby state with minimal activity, and the low power idle block further reduces power consumption by entering a deeper standby mode. The apparatus also includes a state transition module that monitors system parameters and triggers transitions between these block types to optimize performance and energy efficiency. The invention ensures reliable fault handling and power management by dynamically adapting the control block's type to current operational demands, reducing unnecessary power consumption and improving system responsiveness.
13. The apparatus according to claim 12 , wherein the predetermined result is 00000000 or 01010010 when it is detected that the type of the control block in the second to-be-checked bit stream is the local fault block type and the second to-be-checked bit stream comprises consecutive local fault blocks.
This invention relates to error detection in data storage systems, specifically for identifying and handling local fault blocks in bit streams. The problem addressed is the need to accurately detect and process consecutive local fault blocks within a bit stream to ensure data integrity and reliable error correction. The apparatus includes a detection unit that analyzes a second bit stream to determine if it contains consecutive local fault blocks. If detected, the apparatus generates a predetermined result value, which is either 00000000 or 01010010, depending on the specific conditions of the bit stream. This result is used to flag or process the consecutive local fault blocks appropriately, ensuring that the system can take corrective action or log the error for further analysis. The detection unit operates by first identifying the type of control block in the bit stream. If the control block is classified as a local fault block, the unit then checks for consecutive occurrences of such blocks. The predetermined result values are assigned based on the presence and sequence of these blocks, providing a standardized output for error handling. This mechanism improves the reliability of data storage systems by ensuring that consecutive local faults are detected and managed efficiently.
14. The apparatus according to claim 12 , wherein the predetermined result is 00000000 or 10010010 when it is detected that the type of the control block in the second to-be-checked bit stream is the remote fault block type and the second to-be-checked bit stream comprises consecutive remote fault blocks.
This invention relates to error detection in data transmission systems, specifically for identifying and handling remote fault conditions in bit streams. The problem addressed is the need to accurately detect and process consecutive remote fault blocks within a bit stream to ensure reliable communication. The apparatus includes a detection module that analyzes a second bit stream to determine if it contains consecutive remote fault blocks. A control block type identifier within the detection module checks whether the control block in the second bit stream is of the remote fault block type. If consecutive remote fault blocks are detected, a result generator produces a predetermined result, which is either 00000000 or 10010010, to indicate the fault condition. This result can then be used by downstream systems for error correction or fault management. The apparatus also includes a first bit stream analyzer that processes an initial bit stream to generate the second bit stream for further analysis. The detection module operates on the second bit stream to ensure that remote fault blocks are correctly identified and flagged. The predetermined result values (00000000 or 10010010) serve as standardized indicators for consecutive remote fault blocks, allowing consistent handling across different systems. This approach improves fault detection accuracy and simplifies error management in data transmission systems.
15. The apparatus according to claim 12 , wherein determining the third result based on the impact of the type of the control block on the second result comprises: when it is detected that the type of the control block in the second to-be-checked bit stream is the local fault block type and a quantity of local fault blocks in the second to-be-checked bit stream is 1, reversing bit values at second, fourth, and seventh bit positions in the second result, to obtain the third result.
This invention relates to error detection and correction in data processing systems, specifically for handling control blocks in bit streams to improve fault detection accuracy. The problem addressed is the need to accurately determine the impact of different control block types on error detection results, particularly when local fault blocks are present in a bit stream. The apparatus includes a processing unit configured to analyze a bit stream containing control blocks, which are segments of data used to manage or control data processing operations. The system evaluates the type of control block in a bit stream and adjusts the error detection result accordingly. For a bit stream containing a single local fault block—a type of control block indicating a localized error—the system modifies the error detection result by reversing the bit values at specific positions (second, fourth, and seventh) in the intermediate result. This adjustment ensures that the final error detection result accurately reflects the presence and impact of the local fault block, improving the reliability of error correction mechanisms. The apparatus further includes components for generating and comparing bit streams, as well as determining the type and quantity of control blocks within them. The system dynamically adjusts the error detection process based on the detected control block type, ensuring accurate fault identification and correction. This method enhances the robustness of data integrity checks in systems where control blocks are used to manage data flow or processing operations.
16. The apparatus according to claim 12 , wherein determining the third result based on the impact of the type of the control block on the second result comprises: when it is detected that the type of the control block in the second to-be-checked bit stream is the remote fault block type and a quantity of remote fault blocks in the second to-be-checked bit stream is 1, reversing bit values at first, fourth, and seventh bit positions in the second result, to obtain the third result.
This invention relates to error detection and correction in digital systems, specifically addressing the handling of control blocks in bit streams to improve fault detection accuracy. The problem solved involves accurately processing control blocks, particularly remote fault blocks, to ensure correct error identification in data transmission or storage systems. The apparatus processes a bit stream containing control blocks, which are used to manage or indicate errors in the data. When a control block of the remote fault block type is detected in a bit stream, and there is exactly one such block in the stream, the apparatus modifies the error detection result by reversing the bit values at specific positions (first, fourth, and seventh) in the intermediate result. This adjustment accounts for the unique impact of the remote fault block type on error detection, ensuring the final result accurately reflects the true error state of the bit stream. The method involves analyzing the type and quantity of control blocks in the bit stream, applying a predefined transformation to the intermediate error detection result based on the detected remote fault block, and generating a corrected final result. This approach enhances reliability in systems where control blocks influence error detection outcomes, such as in communication protocols or memory systems. The solution ensures that the presence of a single remote fault block does not lead to misinterpretation of errors in the data.
17. The apparatus according to claim 12 , wherein determining the third result based on the impact of the type of the control block on the second result comprises: when it is detected that the type of the control block in the second to-be-checked bit stream is the idle block type or the low power idle block type, reversing bit values at second, third, fourth, and fifth bit positions in the second result, to obtain the third result.
This invention relates to data processing systems, specifically methods for handling control blocks in bit streams to optimize performance or power efficiency. The problem addressed involves accurately interpreting control blocks in data streams, particularly when certain block types (idle or low-power idle) require specific bit manipulations to ensure correct processing. The apparatus processes a bit stream containing control blocks, where each block type affects how subsequent data is interpreted. The system first generates a second result by analyzing a second to-be-checked bit stream. If the control block in this stream is identified as either an idle block or a low-power idle block, the system modifies the second result by reversing the bit values at the second, third, fourth, and fifth bit positions. This reversal produces a third result, ensuring proper handling of these block types. The reversal operation corrects or adjusts the data interpretation to account for the unique characteristics of idle or low-power idle blocks, which may otherwise lead to misprocessing. This technique is particularly useful in systems where control blocks influence data flow, power states, or error handling, ensuring accurate and efficient operation. The invention improves reliability and performance by dynamically adapting to different control block types.
18. The apparatus according to claim 11 , wherein the transceiver is further configured to: receive a first parity value collected by the sending device, wherein the first parity value indicates a quantity of blocks in the first to-be-checked bit stream; and wherein the program further includes instructions for: collecting a quantity of blocks in the second to-be-checked bit stream; generating a second parity value; and when the first result is the same as the third result and the first parity value is the same as the second parity value, determining that a bit error occurs when the first to-be-checked bit stream was transmitted.
This invention relates to error detection in data transmission systems, specifically for identifying bit errors in transmitted bit streams. The system includes a sending device and a receiving device, each configured to process and compare bit streams to detect discrepancies. The sending device generates a first to-be-checked bit stream and a first parity value, where the parity value indicates the quantity of blocks in the first bit stream. The receiving device processes a second to-be-checked bit stream, which is a received version of the first bit stream, and generates a second parity value based on the blocks in the second bit stream. The system compares the first and second bit streams to produce a first result and a third result, respectively. If the first and third results match and the first and second parity values match, the system determines that a bit error occurred during transmission. This method ensures reliable error detection by cross-verifying both the content and structural integrity of the transmitted data. The apparatus includes a transceiver for receiving the first parity value and a program for executing the parity comparison and error determination steps. The invention improves data transmission reliability by detecting errors that may arise from bit flips or corruption during transmission.
19. The apparatus according to claim 11 , wherein the program further includes instructions for: accumulating a quantity of bit errors occurring in a preset time period, and calculating a bit error rate based on a total quantity of bit errors accumulated in the preset time period and a total quantity of received bits; and sending the total quantity of bit errors or the bit error rate to the sending device.
This invention relates to error detection and reporting in communication systems, specifically for monitoring and transmitting bit error rates (BER) to improve data transmission reliability. The apparatus includes a receiver that processes incoming data and detects bit errors, which are discrepancies between transmitted and received data. The system accumulates the number of bit errors over a predefined time interval and calculates the BER by dividing the total bit errors by the total received bits during that period. The calculated BER or the raw error count is then transmitted back to the sending device, enabling it to assess transmission quality and adjust parameters such as modulation, coding, or retransmission strategies to mitigate errors. The apparatus may also include a transmitter for sending data and a processor for executing error detection algorithms. The error reporting mechanism allows real-time feedback, enhancing system performance by dynamically adapting to channel conditions. This solution addresses the need for accurate error monitoring in communication systems to ensure reliable data transfer, particularly in environments with high interference or noise. The invention is applicable in wireless, wired, or optical communication systems where maintaining low error rates is critical.
20. A non-transitory computer readable storage medium storing a program executable by at least one processor, the program including instructions for: receiving a first result, wherein the first result is obtained by a sending device by performing first bit interleaving parity (BIP) check on a first to-be-checked bit stream that is sent by the sending device; receiving a second to-be-checked bit stream after the first to-be-checked bit stream is sent by the sending device, wherein the first to-be-checked bit stream is the same as the second to-be-checked bit stream, or one or more blocks are added to or deleted from the first to-be-checked bit stream during transmission of the first to-be-checked bit stream, to form the second to-be-checked bit stream that is received; performing second BIP check on the second to-be-checked bit stream to obtain a second result; detecting a type of a control block in the second to-be-checked bit stream; determining a third result based on impact of the type of the control block on the second result; comparing the first result, the second result, and the third result; and in response to determining the first result is different from the second result, the first result is different from the third result, and the second result is different from a predetermined result, determining that a bit error occurred when the first to-be-checked bit stream was transmitted.
This invention relates to error detection in digital communication systems, specifically addressing the challenge of accurately identifying bit errors in transmitted data streams when control blocks may affect parity checks. The system involves a non-transitory computer-readable storage medium storing a program executable by a processor. The program receives a first result from a sending device, which is obtained by performing a first bit interleaved parity (BIP) check on a first to-be-checked bit stream sent by the device. The program then receives a second to-be-checked bit stream, which may be identical to the first bit stream or modified by the addition or deletion of one or more blocks during transmission. A second BIP check is performed on the second bit stream to obtain a second result. The program detects the type of control block present in the second bit stream and determines a third result based on the impact of the control block type on the second result. The first, second, and third results are compared. If the first result differs from the second result, the first result differs from the third result, and the second result differs from a predetermined result, the system concludes that a bit error occurred during transmission of the first bit stream. This method improves error detection reliability by accounting for control block influences on parity checks.
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June 25, 2020
March 29, 2022
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