A low voltage drive circuit (LVDC) includes a drive sense circuit operable to convert analog outbound data into an analog transmit signal and convert analog receive signals into analog inbound data, a transmit digital to analog circuit operable to convert transmit digital data into the analog outbound data, and a receive analog to digital circuit including an analog to digital converter, a digital filtering circuit, and a data formatting module. The data formatting module includes a sample and hold circuit operable to sample and hold an n-bit digital value of filtered digital data from the digital filtering circuit to produce an n-bit sampled digital data value, a digital to digital converter circuit operable to adjust formatting of the n-bit sampled digital data value to produce a formatted digital value, and a data packeting circuit operable to generate a packet of received digital data from a plurality of formatted digital values.
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1. A low voltage drive circuit (LVDC) comprises: a drive sense circuit configured to: convert analog outbound data into an analog transmit signal that is transmitted on a bus; receive an analog receive signal from the bus; and convert the analog receive signal into analog inbound data; a transmit digital to analog circuit configured to convert transmit digital data into the analog outbound data; and a receive analog to digital circuit that includes: an analog to digital converter configured to convert the analog inbound data into digital inbound data; a digital filtering circuit configured to filter the digital inbound data to produce filtered digital data; and a data formatting module including: a sample and hold circuit configured to sample and hold an n-bit digital value of the filtered digital data to produce an n-bit sampled digital data value; a digital to digital converter circuit configured to adjust formatting of the n-bit sampled digital data value to produce a formatted digital value; and a data packeting circuit configured to generate a packet of received digital data from a plurality of formatted digital values.
2. The LVDC of claim 1 , wherein the data formatting module further comprises: an interpreter configured to: receive a plurality of n-bit sampled digital data values from the sample and hold circuit; convert the plurality of n-bit sampled digital data values into a plurality of interpreted n-bit sampled digital data values; and output, to the digital to digital converter circuit, the plurality of interpreted n-bit sampled digital data values on an interpreted n-bit sampled digital data value to interpreted n-bit sampled digital data value basis in accordance with a write clock.
This invention relates to low-voltage differential signaling (LVDS) systems, specifically addressing the challenge of efficiently processing and converting sampled digital data values for transmission. The system includes a data formatting module that further comprises an interpreter. The interpreter receives a plurality of n-bit sampled digital data values from a sample and hold circuit. These values are then converted into a plurality of interpreted n-bit sampled digital data values. The interpreter outputs these interpreted values to a digital-to-digital converter circuit on a value-by-value basis, synchronized with a write clock. This ensures precise timing and accurate data conversion, improving signal integrity and transmission efficiency in LVDS applications. The interpreter's role is to process the raw sampled data, ensuring it is correctly formatted and synchronized before conversion, which is critical for maintaining data accuracy in high-speed communication systems. The system enhances the reliability and performance of LVDS by optimizing the data handling process between sampling and conversion stages.
3. The LVDC of claim 2 , wherein the interpreter converts the plurality of n-bit sampled digital data values into the plurality of interpreted n-bit sampled digital data values based on n-bit to binary data conversion.
A system for processing low-voltage differential signaling (LVDS) data converts n-bit sampled digital data values into interpreted n-bit sampled digital data values using an interpreter. The interpreter performs n-bit to binary data conversion to transform the sampled data into a format suitable for further processing. The system includes a receiver circuit that captures the LVDS data and a sampling circuit that generates the n-bit sampled digital data values from the received signal. The interpreter then processes these values to produce the interpreted n-bit sampled digital data values, which may be used for error detection, data validation, or other signal processing tasks. The conversion ensures compatibility with binary-based systems while preserving the integrity of the original LVDS data. This approach is particularly useful in high-speed communication systems where accurate data interpretation is critical for reliable transmission and reception of digital signals. The system may be integrated into communication devices, data acquisition systems, or other applications requiring precise digital signal processing.
4. The LVDC of claim 2 , wherein the interpreter outputs, to a first buffer of the data formatting module, the plurality of interpreted n-bit sampled digital data values on the interpreted n-bit sampled digital data value to the interpreted n-bit sampled digital data value basis in accordance with the write clock.
A low-voltage differential current (LVDC) system processes digital data by interpreting n-bit sampled digital data values and formatting them for output. The system includes an interpreter that receives sampled digital data and converts it into interpreted n-bit values. These interpreted values are then output to a first buffer within a data formatting module. The output occurs on a per-value basis, meaning each interpreted n-bit value is individually transferred to the buffer. The transfer is synchronized with a write clock, ensuring timing consistency. The data formatting module further processes the buffered values for subsequent use, such as transmission or storage. This approach improves data handling efficiency by ensuring precise timing and structured formatting of digital signals. The system is particularly useful in applications requiring high-speed, low-latency data processing, such as telecommunications, digital signal processing, or high-performance computing. The interpreter and buffer interaction ensures reliable data flow, reducing errors and improving system performance.
5. The LVDC of claim 1 , wherein the data formatting module further comprises: a first buffer configured to: receive a plurality of n-bit sampled digital data values from the sample and hold circuit, wherein the plurality of n-bit sampled digital data values includes the n-bit sampled digital data value; store the n-bit sampled digital data values on an n-bit sampled digital value by n-bit sampled digital value basis in accordance with a write clock; and output a plurality of digital words on a digital word by digital word basis in accordance with a read clock, wherein a digital word of the plurality of digital words includes a set of n-bit sampled digital data values of the plurality of n-bit sampled digital data values.
This invention relates to low-voltage differential signaling (LVDS) systems, specifically addressing the challenge of efficiently formatting and transmitting high-speed digital data. The system includes a data formatting module that processes sampled digital data values for transmission. The module features a first buffer that receives multiple n-bit sampled digital data values from a sample-and-hold circuit. These values are stored sequentially in the buffer according to a write clock, allowing for organized data accumulation. The buffer then outputs these values as a series of digital words, each word comprising a set of n-bit sampled digital data values, synchronized to a read clock. This approach ensures efficient data packaging and transmission, optimizing bandwidth usage and reducing latency in high-speed communication systems. The buffer's dual-clock operation (write and read) enables flexible data handling, accommodating varying input and output rates while maintaining data integrity. The invention improves upon prior art by providing a structured method for managing digital data streams in LVDS applications, enhancing performance in systems requiring precise timing and high data throughput.
6. The LVDC of claim 5 , wherein the digital to digital converter circuit is further configured to: generate a plurality of formatted digital words from the plurality of digital words.
This invention relates to low-voltage direct current (LVDC) systems, specifically addressing the need for efficient digital signal processing in power conversion applications. The system includes a digital-to-digital converter circuit designed to process digital signals within an LVDC architecture. The converter circuit receives a plurality of digital words and generates a plurality of formatted digital words. The formatting process ensures compatibility with downstream components, such as power converters or control systems, by adjusting parameters like bit depth, resolution, or encoding schemes. This allows for seamless integration of digital signals into the LVDC system, improving efficiency and reliability in power management applications. The converter circuit may also include additional features, such as error correction or signal conditioning, to enhance data integrity and performance. The overall system enables precise control and monitoring of power conversion processes, making it suitable for applications in renewable energy, electric vehicles, and industrial power systems. The invention focuses on optimizing digital signal handling to support advanced power management techniques in modern LVDC environments.
7. The LVDC of claim 6 , wherein the data formatting module further comprises: a second buffer configured to: store the plurality of formatted digital words on a formatted digital word by formatted digital word basis in accordance with the read clock of the first buffer to produce a plurality of buffered digital words; and output the plurality of buffered digital words to the data packeting circuit on a buffered digital word by buffered digital word basis in accordance with a second read clock.
This invention relates to low-voltage differential signaling (LVDS) systems, specifically addressing the challenge of efficiently formatting and transmitting digital data in high-speed communication applications. The system includes a data formatting module that processes digital words for transmission via an LVDS interface. The module contains a first buffer that stores incoming digital words and outputs them in accordance with a first read clock. A data formatting circuit then formats these digital words into a standardized format suitable for LVDS transmission. A second buffer stores these formatted digital words on an individual basis, synchronized with the first buffer's read clock, producing a plurality of buffered digital words. These buffered words are then output to a data packeting circuit, which organizes them into packets for transmission, using a second read clock. This dual-buffer approach ensures synchronized data flow and minimizes latency in high-speed data transmission. The system is designed to improve data integrity and transmission efficiency in LVDS-based communication systems.
8. The LVDC of claim 7 , wherein the data packeting circuit is further configured to: generate the packet to include a set of buffered digital words of the plurality of buffered digital words in accordance with a packet clock.
A system for low-voltage differential communication (LVDC) includes a data packeting circuit that processes digital data for transmission. The system addresses the challenge of efficiently transmitting digital signals over differential communication channels while maintaining signal integrity and minimizing power consumption. The data packeting circuit buffers a plurality of digital words and organizes them into packets for transmission. The circuit is configured to generate packets that include a subset of the buffered digital words, with the selection and timing of these words controlled by a packet clock. This ensures synchronized and efficient data transmission, reducing latency and improving reliability in communication systems. The packet clock governs the timing of packet generation, allowing for precise control over data flow and ensuring compatibility with various communication protocols. The system is particularly useful in applications requiring high-speed, low-power differential signaling, such as in embedded systems, industrial automation, and high-performance computing.
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March 30, 2021
April 5, 2022
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