A structure that can be used to manufacture at least one active layer made of a III-V material thereon includes a substrate comprising a carrier having a main face, a dielectric layer located on the main face of the carrier, and a plurality of single-crystal semiconductor islands located directly on the dielectric layer. The islands have an upper surface in order to serve as a seed surface for the growth of the active layer. The structure further comprises a seed layer located between the single-crystal semiconductor islands, directly on the portion of the dielectric layer that is not covered by the islands, without masking the upper surface of the islands, so that the dielectric layer is not exposed to the external environment.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor substrate structure for producing at least one active layer made of a III-V material thereon, comprising: a carrier having a main face; a dielectric layer located over the main face of the carrier; a plurality of single-crystal semiconductor islands located directly on the dielectric layer, each of the plurality of single-crystal semiconductor islands having an exposed upper surface to be used as a seed surface for growth of the at least one active layer; and a polycrystalline AlN seed layer located between the single-crystal semiconductor islands, directly on a portion of the dielectric layer not covered by the single-crystal semiconductor islands such that the portion of the dielectric layer is not exposed to its environment, the polycrystalline AlN seed layer exhibiting a first thickness less than a second thickness of the plurality of single-crystal semiconductor islands.
2. The semiconductor substrate structure of claim 1 , wherein the carrier comprises silicon or sapphire.
3. The semiconductor substrate structure of claim 2 , wherein the dielectric layer comprises silicon oxide and/or silicon nitride.
4. The semiconductor substrate structure of claim 3 , wherein the single-crystal semiconductor islands comprise a III-V material.
5. The semiconductor substrate structure of claim 4 , wherein the single-crystal semiconductor islands comprise InGaN.
6. The semiconductor substrate structure of claim 1 , wherein the dielectric layer comprises silicon oxide and/or silicon nitride.
7. The semiconductor substrate structure of claim 1 , wherein the single-crystal semiconductor islands comprise a III-V material.
8. The semiconductor substrate structure of claim 7 , wherein the single-crystal semiconductor islands comprise InGaN.
9. A method for producing a semiconductor substrate structure, comprising: providing a structure including a carrier having a main face, a dielectric layer located over the main face of the carrier, and a plurality of single-crystal semiconductor islands located directly on the dielectric layer, each of the plurality of single-crystal semiconductor islands having an exposed upper surface to be used as a seed surface for growth of an active layer of III-V material; and prior to growth on the exposed upper surface, forming a polycrystalline AlN seed layer between the single-crystal semiconductor islands and directly on a portion of the dielectric layer that is not covered by the single-crystal semiconductor islands such that the portion of the dielectric layer is not exposed to an external environment, the polycrystalline AlN seed layer exhibiting a first thickness less than a second thickness of the plurality of single-crystal semiconductor islands.
10. The method according to claim 9 , wherein forming the polycrystalline AlN seed layer comprises depositing the polycrystalline AlN seed layer onto and between the single-crystal semiconductor islands, and then selectively removing portions of the polycrystalline AlN seed layer located on the single-crystal semiconductor islands.
11. The method of claim 10 , wherein selectively removing the portions of the polycrystalline AlN seed layer located on the single-crystal semiconductor islands comprises subjecting the portions of the polycrystalline AlN seed layer located on the single-crystal semiconductor islands to a mechanical-chemical polishing process.
12. The method of claim 9 , wherein forming the polycrystalline AlN seed layer comprises selectively forming a protective layer on the single-crystal semiconductor islands, depositing the polycrystalline AlN seed layer onto the protective layer and onto an exposed surface of the dielectric layer between the single-crystal semiconductor islands, and selectively removing the protective layer and portions of the polycrystalline AlN seed layer located on the single-crystal semiconductor islands.
13. The method of claim 12 , wherein the protective layer comprises a photosensitive resin and selectively forming the protective layer on the single-crystal semiconductor islands comprises using a photolithography process to selectively form the protective layer on the single-crystal semiconductor islands.
14. The method of claim 12 , wherein selectively removing the protective layer and the portions of the polycrystalline AlN seed layer located on the single-crystal semiconductor islands comprises chemically etching the protective layer and/or portions of the polycrystalline AlN seed layer located on the single-crystal semiconductor islands.
15. A method for manufacturing a semiconductor device, comprising: providing a substrate structure including: a carrier having a main face; a dielectric layer located over the main face of the carrier; a plurality of single-crystal semiconductor islands located directly on the dielectric layer, each of the plurality of single-crystal semiconductor islands having an exposed upper surface to be used as a seed surface for growth of at least one active layer; and a polycrystalline AlN seed layer located between the single-crystal semiconductor islands, directly on a portion of the dielectric layer not covered by the single-crystal semiconductor islands such that the portion of the dielectric layer is not exposed to its environment, the polycrystalline AlN seed layer exhibiting a first thickness less than a second thickness of the plurality of single-crystal semiconductor islands; and forming the at least one active layer of a III-V material on the single-crystal semiconductor islands.
16. The semiconductor substrate structure of claim 1 , wherein the polycrystalline AlN seed layer comprises a plurality of polycrystalline AlN layers stacked on top of one another.
17. The semiconductor substrate structure of claim 1 , wherein the polycrystalline AlN seed layer is selected to have sufficient chemical affinity with constituents of the at least one active layer to be formed such that the polycrystalline AlN seed layer prevents the constituents from settling on edges of the exposed upper surface of the plurality of single-crystal semiconductor islands.
18. The method of claim 9 , further comprising exposing the structure to precursor gases to form the active layer of III-V material on the exposed upper surface of the plurality of single-crystal semiconductor islands.
19. The method of claim 18 , wherein exposing the structure to precursor gases comprises forming a residue layer on the polycrystalline AlN seed layer.
20. The method of claim 18 , wherein exposing the structure to precursor gases comprises preventing chemical species from the precursor gases from migrating and settling on edges of the exposed upper surface of the plurality of single-crystal semiconductor islands.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 21, 2017
April 5, 2022
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