A polarization induced strain coupled two dimensional field effect transistor (PoSt FET) memory cell is disclosed which includes a transistor including a source contact, a drain contact, a gate contact, a back contact, a channel disposed atop the gate contact, wherein the channel and the gate are separated by an electrically insulating material, and a piezoelectric (PE)/ferroelectric(FE) (PE/FE) layer disposed between the gate contact and the back contact and configured to store bit information in form of ferroelectric polarization (P), wherein a ratio of cross-sectional area of the channel to cross-sectional area of the PE/FE layer is between about 0.03 to about 0.07.
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1. A polarization induced strain coupled two dimensional field effect transistor (PoSt FET) memory cell, comprising: a transistor comprising: a source contact; a drain contact; a gate contact; a back contact; a channel disposed atop the gate contact, wherein the channel and the gate are separated by an electrically insulating material; and a piezoelectric (PE)/ferroelectric(FE) (PE/FE) layer disposed between the gate contact and the back contact and configured to store bit information in form of ferroelectric polarization (P), wherein a ratio of cross-sectional area of the channel to cross-sectional area of the PE/FE layer is between about 0.03 to about 0.07.
This disclosure relates to electronic memory devices and specifically to a novel transistor architecture for memory storage. The problem addressed is the need for efficient and reliable data storage in transistor-based memory cells. The invention describes a polarization-induced strain coupled two-dimensional field effect transistor (PoSt FET) memory cell. The cell includes a transistor with a source contact, a drain contact, a gate contact, and a back contact. A channel is positioned above the gate contact, with an electrically insulating material separating the channel and the gate. Crucially, a piezoelectric/ferroelectric (PE/FE) layer is integrated between the gate contact and the back contact. This PE/FE layer is engineered to store digital information by utilizing its ferroelectric polarization (P). The design also specifies a particular geometric relationship between the channel and the PE/FE layer, where the ratio of their cross-sectional areas is maintained within a range of approximately 0.03 to 0.07. This structural characteristic is key to the operation of the device for memory applications.
2. The PoSt FET memory cell of claim 1 , wherein the channel is made of a two dimensional transition metal dichalcogenides (2D TMD) material.
A memory cell design addresses challenges in scaling conventional semiconductor memory technologies by utilizing a phase-change and storage transistor (PoSt) architecture. The memory cell includes a channel region formed from a two-dimensional transition metal dichalcogenide (2D TMD) material, which provides enhanced electrical and thermal properties compared to traditional silicon-based channels. The 2D TMD material enables improved carrier mobility, reduced leakage currents, and better thermal stability, making it suitable for high-density memory applications. The memory cell operates by leveraging phase-change materials integrated with the transistor structure to store data through resistive switching mechanisms. The 2D TMD channel enhances the switching efficiency and reliability of the memory cell, allowing for faster read/write operations and longer retention times. This design is particularly advantageous for non-volatile memory applications, where low power consumption, high endurance, and scalability are critical requirements. The use of 2D TMD materials also facilitates integration with advanced fabrication processes, enabling the production of compact and high-performance memory devices.
3. The PoSt FET memory cell of claim 2 , wherein the 2D TMD material is selected from the group consisting of MoS 2 , MoSe 2 , WS 2 , WSe 2 , and any combinations thereof.
This invention relates to a phase-change field-effect transistor (PoSt FET) memory cell incorporating a two-dimensional transition metal dichalcogenide (2D TMD) material. The memory cell addresses challenges in conventional memory technologies, such as limited scalability, high power consumption, and slow switching speeds, by leveraging the unique electrical and structural properties of 2D TMD materials. These materials exhibit strong in-plane anisotropy, high carrier mobility, and tunable bandgap characteristics, making them suitable for high-performance memory applications. The memory cell includes a 2D TMD material layer, which serves as the active channel for charge transport. The 2D TMD material is selected from a group consisting of MoS2, MoSe2, WS2, WSe2, or any combination thereof. These materials are chosen for their stability, high on/off ratios, and compatibility with semiconductor fabrication processes. The PoSt FET memory cell operates by switching between distinct resistive states through phase transitions induced by electrical stimuli, enabling non-volatile data storage. The use of 2D TMD materials enhances switching efficiency, reduces power consumption, and improves device reliability compared to traditional memory technologies. The memory cell can be integrated into advanced electronic systems, including high-density storage devices and neuromorphic computing architectures.
4. The PoSt FET memory cell of claim 1 , wherein the PE/FE layer is made of a material selected from the group consisting of PZT, silicon doped HfO 2 , and combinations thereof.
This invention relates to a phase-change ferroelectric field-effect transistor (PoSt FET) memory cell, specifically addressing the material composition of the ferroelectric (FE) layer within the cell. The memory cell leverages the properties of ferroelectric materials to achieve non-volatile data storage by utilizing the polarization states of the FE layer to represent binary data. The invention focuses on optimizing the performance and reliability of the memory cell by selecting specific materials for the FE layer, which is a critical component in determining the cell's switching speed, endurance, and data retention capabilities. The FE layer in the PoSt FET memory cell is composed of materials such as lead zirconate titanate (PZT), silicon-doped hafnium oxide (HfO2), or combinations thereof. These materials are chosen for their strong ferroelectric properties, which enable efficient polarization switching and stable data storage. PZT is known for its high polarization density and fast switching characteristics, while silicon-doped HfO2 offers improved thermal stability and compatibility with semiconductor manufacturing processes. The use of these materials ensures that the memory cell operates reliably under varying environmental conditions and maintains data integrity over extended periods. By incorporating these specific FE materials, the PoSt FET memory cell achieves enhanced performance metrics, including lower power consumption, faster read/write operations, and longer retention times compared to conventional memory technologies. This innovation is particularly valuable in applications requiring high-density, non-volatile memory solutions, such as embedded systems, solid-state drives, and neuromorphic computing architectures. The selection of these materials al
5. The PoSt FET memory cell of claim 4 , wherein the PE/FE layer is made of PZT-5H.
The invention relates to a ferroelectric field-effect transistor (FET) memory cell incorporating a lead zirconate titanate (PZT-5H) layer for data storage. The memory cell addresses the need for high-density, non-volatile memory with fast switching speeds and low power consumption. The cell structure includes a ferroelectric (FE) layer, which is made of PZT-5H, a material known for its strong ferroelectric properties and high polarization retention. This layer is integrated into the FET to enable data storage by switching between polarized states, which modulate the channel conductivity. The PZT-5H material provides enhanced performance characteristics, such as improved polarization stability and reduced switching voltage, compared to other ferroelectric materials. The memory cell operates by applying voltage pulses to the gate electrode, which polarizes the FE layer, altering the channel conductance to represent binary data states. The use of PZT-5H ensures reliable data retention and efficient switching, making the memory cell suitable for high-performance applications. The invention focuses on optimizing the FE layer composition to improve memory cell efficiency and reliability.
6. The PoSt FET memory cell of claim 1 , wherein the PE/FE layer is configured to maintain a bit value based on polarization of the PE/FE layer, whereby the polarization induced strain in the PE/FE layer that is transferred to the channel.
This invention relates to a ferroelectric field-effect transistor (FET) memory cell incorporating a polarization-induced strain mechanism for data storage. The memory cell addresses challenges in non-volatile memory by leveraging the polarization properties of a ferroelectric (FE) or polar-electret (PE) layer to store bit values. The PE/FE layer maintains a bit value through its polarization state, which induces mechanical strain in the layer. This strain is transferred to the channel region of the FET, modulating its electrical properties. The polarization state can be switched between two stable configurations, representing binary data states (e.g., "0" and "1"). The strain-induced modulation of the channel's conductivity enables non-volatile data retention without requiring continuous power. This approach improves memory density and energy efficiency compared to conventional FET-based memory cells by eliminating the need for separate charge storage elements. The invention is particularly useful in low-power, high-density memory applications, such as embedded memory in integrated circuits or standalone non-volatile memory devices. The polarization-induced strain mechanism ensures reliable data retention and fast switching, addressing limitations in traditional flash memory and DRAM technologies.
7. The PoSt FET memory cell of claim 6 , wherein the bit value is read by i) applying a voltage across the gate contact and the back contact (|V GB |) less than a coercive voltage (V C ) associated with the PE/FE layer, ii) applying a voltage across the gate contact and the source contact (V GS ) greater than a threshold voltage (V t ) of the transistor, and iii) comparing a source-to-drain current (I DS ) to threshold currents (I LRS /I HRS ) where if the I DS is above the I LRS , the bit value is associated with a first value and if the I DS is below the I HRS , the but value is associated with a second value opposite the first value.
This invention relates to a ferroelectric field-effect transistor (FET) memory cell, specifically a PoSt (Program/Store) FET memory cell, designed to address challenges in non-volatile memory technology. The memory cell includes a ferroelectric (FE) or phase-change (PE) layer integrated with a transistor structure, enabling data storage through polarization or phase state changes. The cell features a gate contact, a source contact, a drain contact, and a back contact, with the FE/PE layer positioned to influence the transistor's channel conductivity. The reading process involves applying a voltage across the gate and back contacts (|V_GB|) that is less than the coercive voltage (V_C) of the FE/PE layer, ensuring the stored state remains unchanged. Simultaneously, a voltage (V_GS) is applied across the gate and source contacts that exceeds the transistor's threshold voltage (V_t), activating the channel. The source-to-drain current (I_DS) is then measured and compared to predefined threshold currents (I_LRS for low-resistance state and I_HRS for high-resistance state). If I_DS exceeds I_LRS, the stored bit is a first value (e.g., '1'), while if it falls below I_HRS, the bit is a second, opposite value (e.g., '0'). This method ensures non-destructive readout while maintaining the integrity of the stored data. The design leverages the FE/PE layer's bistable nature to achieve reliable, high-density memory storage.
8. The PoSt FET memory cell of claim 6 , wherein the bit value is written to by applying a voltage across the gate contact and the back contact (|V GB |) greater than a coercive voltage (V C ) associated with the PE/FE layer, wherein if the V GB is greater than V c , a P+ polarization is induced into the PE/FE layer, and if the V GB is less than −V c , a P− polarization is induced into the PE/FE layer.
The invention relates to a ferroelectric field-effect transistor (FET) memory cell incorporating a phase-change/ferroelectric (PE/FE) layer for non-volatile data storage. The technology addresses the need for high-density, low-power memory devices with fast switching capabilities. The memory cell includes a gate contact, a back contact, and a PE/FE layer positioned between them. The PE/FE layer exhibits polarization states that can be manipulated to store binary data. To write a bit value, a voltage is applied across the gate and back contacts. If the applied voltage magnitude exceeds a coercive voltage (Vc) associated with the PE/FE layer, the polarization state of the layer changes. A positive voltage greater than Vc induces a positive polarization (P+), while a negative voltage less than -Vc induces a negative polarization (P-). These distinct polarization states correspond to different binary values, enabling data storage. The coercive voltage threshold ensures reliable switching between states, minimizing errors during write operations. This mechanism allows for compact, energy-efficient memory cells suitable for advanced electronic applications.
9. A method of maintain a digital bit value in a polarization induced strain coupled two dimensional field effect transistor (PoSt FET) memory cell, comprising: providing a transistor configured to maintain a bit value comprising: a source contact; a drain contact; a gate contact; a back contact; a channel disposed atop the gate contact, wherein the channel and the gate are separated by an electrically insulating material; and a piezoelectric (PE)/ferroelectric(FE) (PE/FE) layer disposed between the gate contact and the back contact and configured to store bit information in form of ferroelectric polarization (P), wherein a ratio of cross-sectional area of the channel to cross-sectional area of the PE/FE layer is between about 0.03 to about 0.07, and wherein the bit value is maintained based on polarization of the PE/FE layer, whereby the polarization induced strain in the PE/FE layer is transferred to the channel.
This invention relates to a polarization-induced strain coupled two-dimensional field-effect transistor (PoSt FET) memory cell designed to maintain a digital bit value. The memory cell addresses challenges in non-volatile memory by leveraging ferroelectric polarization to store data while minimizing power consumption and improving stability. The device includes a transistor with a source, drain, gate, and back contact. A two-dimensional channel is positioned above the gate, separated by an insulating layer. A piezoelectric/ferroelectric (PE/FE) layer is placed between the gate and back contact, storing bit information as ferroelectric polarization. The PE/FE layer induces strain in the channel, which is transferred to modulate the channel's electrical properties. The ratio of the channel's cross-sectional area to the PE/FE layer's cross-sectional area is optimized between 0.03 and 0.07 to ensure efficient strain coupling and reliable bit retention. The polarization state of the PE/FE layer determines the stored bit value, with the strain effect enhancing readout stability and reducing power requirements. This design enables non-volatile memory with improved endurance and scalability compared to conventional approaches.
10. The method of claim 9 , wherein the channel is made of a two dimensional transition metal dichalcogenides (2D TMD) material selected from the group consisting of MoS 2 , MoSe 2 , WS 2 , WSe 2 , and any combinations thereof and the PE/FE layer is made of a material selected from the group consisting of PZT, silicon doped HfO 2 , and combinations thereof.
This invention relates to a method for fabricating a non-volatile memory device using a two-dimensional (2D) transition metal dichalcogenide (TMD) material for the channel and a ferroelectric/piezoelectric (PE/FE) layer for data storage. The device addresses challenges in conventional memory technologies, such as limited scalability, high power consumption, and slow switching speeds, by leveraging the unique properties of 2D TMDs and ferroelectric materials. The method involves forming a channel from a 2D TMD material, which may include MoS2, MoSe2, WS2, WSe2, or combinations thereof. These materials exhibit excellent electrical and mechanical properties, making them suitable for high-performance memory applications. The PE/FE layer, which interacts with the channel to store data, is made from materials such as PZT (lead zirconate titanate) or silicon-doped HfO2, known for their strong ferroelectric and piezoelectric responses. The combination of these materials enables non-volatile data storage with low power consumption and fast switching capabilities. The invention improves upon existing memory technologies by integrating 2D TMDs with ferroelectric materials, enhancing device performance, scalability, and energy efficiency. This approach is particularly useful for advanced memory applications requiring high-speed, low-power operation.
11. The method of claim 10 , wherein the PE/FE layer is made of PZT-5H.
A method for fabricating a piezoelectric device involves forming a piezoelectric/electrode (PE/FE) layer using lead zirconate titanate (PZT-5H), a high-performance piezoelectric material known for its strong electromechanical coupling and high dielectric constant. The PE/FE layer is integrated into the device to convert mechanical energy into electrical energy or vice versa, depending on the application. The method includes depositing the PZT-5H material onto a substrate or between electrode layers to create a functional piezoelectric structure. The use of PZT-5H enhances the device's efficiency and responsiveness, making it suitable for applications such as sensors, actuators, and energy harvesters. The fabrication process may involve thin-film deposition techniques like sputtering or sol-gel processing to ensure precise control over the material's properties. The resulting device leverages the superior piezoelectric characteristics of PZT-5H to achieve high performance in converting mechanical stress into electrical signals or generating mechanical motion from electrical inputs. This approach addresses the need for reliable, high-efficiency piezoelectric materials in advanced electronic and electromechanical systems.
12. The method of claim 9 , further comprising: reading the bit value by i) applying a voltage across the gate contact and the back contact (V GB ) less than a coercive voltage (V C ) associated with the PE/FE layer, ii) applying a voltage across the gate contact and the source contact (V GS ) greater than a threshold voltage (V t ) of the transistor, and iii) comparing a source-to-drain current (I DS ) to threshold currents (I LRS /I HRS ) where if the I DS is above the I LRS , the bit value is associated with a first value and if the I DS is below the I HRS , the but value is associated with a second value opposite the first value, writing the bit value by applying the |V GB | greater than the V C associated with the PE/FE layer, wherein if the V GB is greater than V c , a P+ polarization is induced into the PE/FE layer, and if the V GB is less than −V c , a P− polarization is induced into the PE/FE layer.
This invention relates to a method for reading and writing bit values in a transistor device incorporating a polarizable ferroelectric (PE/FE) layer. The device includes a gate contact, a source contact, a drain contact, and a back contact, with the PE/FE layer positioned between the gate and back contacts. The method addresses the challenge of reliably detecting and modifying the polarization state of the PE/FE layer to store and retrieve binary data. To read a bit value, the method applies a gate-to-back voltage (V_GB) below the coercive voltage (V_C) of the PE/FE layer, ensuring the polarization state remains unchanged. A gate-to-source voltage (V_GS) exceeding the transistor's threshold voltage (V_t) is applied, enabling current flow. The source-to-drain current (I_DS) is then compared to predefined threshold currents (I_LRS for low-resistance state and I_HRS for high-resistance state). If I_DS exceeds I_LRS, the bit is assigned a first value (e.g., logic 1), while if I_DS falls below I_HRS, it is assigned the opposite value (e.g., logic 0). To write a bit value, the method applies a gate-to-back voltage (V_GB) exceeding the coercive voltage (V_C) in magnitude. A positive V_GB induces a positive polarization (P+) in the PE/FE layer, while a negative V_GB induces a negative polarization (P−). This polarization change alters the transistor's resistance state, encoding the desired bit value. The method ensures non-destructive readout and reliable data storage by leveraging the PE/FE layer's bistable polarization properties.
13. A memory array, comprising: a plurality of polarization induced strain coupled two dimensional field effect transistor (PoSt FET) memory cells, disposed in one or more rows and one or more columns, each PoSt FET memory cell comprising: a transistor comprising: a source contact; a drain contact; a gate contact; a back contact; a channel disposed atop the gate contact, wherein the channel and the gate are separated by an electrically insulating material; and a piezoelectric (PE)/ferroelectric(FE) (PE/FE) layer disposed between the gate contact and the back contact and configured to store bit information in form of ferroelectric polarization (P), wherein a ratio of cross-sectional area of the channel to cross-sectional area of the PE/FE layer is between about 0.03 to about 0.07, the gate contact of each of the PoSt FET memory cells in each row of the one or more rows is coupled to an associated word line (WL) for said row, the back contact of each of the PoSt FET memory cells in each column of the one or more columns is coupled to an associated write bit line (WBL) for said column, and drain contact of each of the PoSt FET memory cells in each column of the one or more columns is coupled to an associated read bit line (RBL) for said column, wherein a PoSt FET memory cell in a row and a column is written to by activating an associated WBL and WL and a PoSt FET memory cell in a row and a column is read from by activating an associated RBL and WL.
This invention relates to a memory array using polarization-induced strain coupled two-dimensional field-effect transistor (PoSt FET) memory cells. The technology addresses the need for high-density, non-volatile memory with fast read/write operations and low power consumption. The memory array consists of multiple PoSt FET memory cells arranged in rows and columns. Each PoSt FET memory cell includes a transistor with a source, drain, gate, and back contact. The transistor has a channel separated from the gate by an insulating layer, and a piezoelectric/ferroelectric (PE/FE) layer between the gate and back contact. The PE/FE layer stores bit information as ferroelectric polarization, with the channel-to-PE/FE layer cross-sectional area ratio optimized between 0.03 and 0.07 for efficient operation. The gate contacts of cells in each row are connected to a word line (WL), while the back contacts and drain contacts of cells in each column are connected to a write bit line (WBL) and read bit line (RBL), respectively. Writing to a cell involves activating its WBL and WL, while reading involves activating its RBL and WL. This design enables compact, high-performance memory storage with improved switching characteristics and reliability.
14. The memory array of claim 13 , wherein the channel is made of a two dimensional transition metal dichalcogenides (2D TMD) material.
This invention relates to memory arrays incorporating two-dimensional (2D) transition metal dichalcogenides (TMD) materials for improved performance. The memory array includes a plurality of memory cells, each comprising a channel region and a gate structure. The channel region is formed from a 2D TMD material, which provides enhanced electrical properties such as high mobility, strong gate control, and scalability for advanced memory applications. The gate structure is positioned adjacent to the channel region to modulate its conductivity, enabling data storage and retrieval. The use of 2D TMD materials in the channel region improves the memory cell's switching speed, energy efficiency, and reliability compared to traditional semiconductor materials. The memory array may be integrated into various electronic devices, including but not limited to, non-volatile memory, logic circuits, and neuromorphic computing systems. The invention addresses challenges in scaling conventional memory technologies by leveraging the unique properties of 2D TMD materials, such as atomic-level thickness, high on/off ratios, and compatibility with flexible substrates. This approach enables the development of high-density, low-power memory solutions for next-generation electronics.
15. The memory array of claim 14 , wherein the 2D TMD material is selected from the group consisting of MoS 2 , MoSe 2 , WS 2 , WSe 2 , and any combinations thereof.
This invention relates to memory arrays incorporating two-dimensional transition metal dichalcogenide (2D TMD) materials for improved performance. The technology addresses challenges in conventional memory devices, such as limited scalability, high power consumption, and slow switching speeds, by leveraging the unique electronic and structural properties of 2D TMDs. These materials exhibit excellent charge carrier mobility, strong electrostatic control, and atomic-scale thickness, making them ideal for next-generation memory applications. The memory array includes a plurality of memory cells, each comprising a 2D TMD material as the active layer. The 2D TMD material is selected from MoS2, MoSe2, WS2, WSe2, or combinations thereof, chosen for their superior semiconductor properties, including high on/off ratios and low leakage currents. The memory cells are arranged in a grid-like structure, with each cell interfacing with word lines and bit lines for read/write operations. The 2D TMD layer is integrated into a transistor or resistive switching device, enabling efficient data storage and retrieval. The use of these materials enhances memory density, reduces power consumption, and improves switching speeds compared to traditional silicon-based memory technologies. The invention also includes variations in the TMD composition to optimize performance for specific applications, such as high-speed computing or low-power embedded systems.
16. The memory array of claim 13 , wherein the PE/FE layer is made of a material selected from the group consisting of PZT, silicon doped HfO 2 , and combinations thereof.
This invention relates to memory arrays incorporating a phase-change or ferroelectric (PE/FE) layer for non-volatile data storage. The technology addresses the need for high-density, low-power memory solutions with fast switching speeds and improved retention characteristics. Traditional memory technologies, such as flash, suffer from limitations in scalability, endurance, and write/erase speeds. The invention leverages materials like PZT (lead zirconate titanate) and silicon-doped HfO2 (hafnium oxide) to enable compact, energy-efficient memory cells with enhanced performance. The memory array includes a PE/FE layer integrated into the cell structure, where the material composition is critical for achieving desired electrical properties. PZT is a well-known ferroelectric material with strong polarization switching capabilities, while silicon-doped HfO2 offers ferroelectric behavior in a CMOS-compatible material system. The use of these materials allows for non-volatile data storage through polarization states, which can be read and written electrically. The array may also incorporate additional layers or structures to optimize performance, such as electrodes, barriers, or selectors, to ensure reliable operation. By selecting materials from the group consisting of PZT, silicon-doped HfO2, or combinations thereof, the memory array achieves improved switching efficiency, endurance, and data retention. This innovation is particularly relevant for applications requiring high-density storage, such as embedded memory, neuromorphic computing, and high-performance computing systems. The disclosed material choices provide flexibility in design while maintaining compatibility with existing semiconductor manufacturing processes.
17. The memory array of claim 16 , wherein the PE/FE layer is made of PZT-5H.
The invention relates to memory arrays incorporating a processing-in-memory (PIM) architecture, specifically focusing on the material composition of the processing and front-end (PE/FE) layer within the memory array. The technology addresses the challenge of improving computational efficiency and performance in memory systems by integrating processing capabilities directly within the memory array, reducing data transfer bottlenecks between memory and processing units. The memory array includes a plurality of memory cells, each with a processing-in-memory (PIM) structure that combines memory storage and computational functions. The PE/FE layer, which is a critical component of this structure, is made of PZT-5H, a lead zirconate titanate (PZT) material known for its high piezoelectric and ferroelectric properties. PZT-5H is selected for its superior electromechanical coupling coefficient, which enhances the efficiency of data processing operations within the memory array. This material choice improves the speed and energy efficiency of in-memory computations, particularly for tasks involving analog or mixed-signal processing. The memory array may further include additional layers or components, such as a back-end (BE) layer, which interfaces with the PE/FE layer to facilitate data storage and retrieval. The integration of PZT-5H in the PE/FE layer enables the memory array to perform complex computations directly within the memory fabric, reducing latency and power consumption compared to traditional architectures where data must be transferred to external processors. This innovation is particularly beneficial for applications requiring high-speed, low-power processing, such as artificial intelligence, machine learning, and real-time signal processing.
18. The memory array of claim 13 , wherein the PE/FE layer is configured to maintain a bit value based on polarization of the PE/FE layer, whereby the polarization induced strain in the PE/FE layer that is transferred to the channel.
This memory stores information as bits by changing the polarization of a material layer. The strain caused by this polarization then represents the stored bit.
19. The memory array of claim 18 , wherein the bit value of an associated PoSt FET memory cell is read by i) applying a voltage across the gate contact and the back contact (|V GB |) less than a coercive voltage (V C ) associated with the PE/FE layer, ii) applying a voltage across the gate contact and the source contact (V GS ) greater than a threshold voltage (V t ) of the transistor, and iii) comparing a source-to-drain current (I DS ) to threshold currents (I LRS /I HRS ) where if the I DS is above the I LRS , the bit value is associated with a first value and if the I DS is below the I HRS , the but value is associated with a second value opposite the first value.
This invention relates to a memory array incorporating PoSt FET (Polarity-Switching Ferroelectric Field-Effect Transistor) memory cells, addressing challenges in non-volatile memory read operations. The memory array includes a plurality of PoSt FET memory cells, each comprising a ferroelectric/piezoelectric (PE/FE) layer, a gate contact, a source contact, a drain contact, and a back contact. The PE/FE layer enables non-volatile data storage by switching polarization states, which modulate the transistor's conductivity. To read the bit value stored in a PoSt FET memory cell, a voltage is applied across the gate and back contacts (|V_GB|) that is less than the coercive voltage (V_C) of the PE/FE layer, ensuring the polarization state remains unchanged during the read operation. Simultaneously, a voltage is applied across the gate and source contacts (V_GS) that exceeds the transistor's threshold voltage (V_t), activating the channel. The resulting source-to-drain current (I_DS) is then compared to predefined threshold currents (I_LRS for low-resistance state and I_HRS for high-resistance state). If I_DS exceeds I_LRS, the bit value is determined to be a first value (e.g., logic '1'), while if I_DS falls below I_HRS, the bit value is determined to be a second, opposite value (e.g., logic '0'). This method ensures reliable read operations without disturbing the stored data.
20. The memory array of claim 19 , wherein the PoSt FET memory cells that are not to be read are governed by one of A) the |V GB | is less than the V C and the V GS is smaller than the V t of the transistor; or B) the |V GB | is less than the V C and a substantially zero voltage across the drain contact and the source contact (V DS ).
This invention relates to memory arrays using PoSt FET (Programmable Single Transistor Field Effect Transistor) memory cells, addressing challenges in selectively reading specific cells while preventing unintended read operations in adjacent or unselected cells. The memory array includes multiple PoSt FET memory cells arranged in rows and columns, where each cell comprises a transistor with a gate, source, and drain. The invention focuses on controlling the voltage conditions for unselected cells to ensure they remain in a non-conductive state during read operations, preventing data corruption or interference. For unselected cells, two voltage control schemes are employed. In the first scheme, the absolute value of the gate-to-body voltage (|V_GB|) is maintained below a critical voltage (V_C), and the gate-to-source voltage (V_GS) is kept below the transistor's threshold voltage (V_t), ensuring the transistor remains off. In the second scheme, |V_GB| is also kept below V_C, but the voltage difference between the drain and source (V_DS) is set to substantially zero, preventing any current flow through the transistor. These conditions ensure that only the targeted memory cell is read, while all other cells in the array remain inactive, improving read accuracy and reliability. The invention is particularly useful in high-density memory arrays where minimizing interference between cells is critical.
21. The memory array of claim 18 , wherein the bit value is written to by applying a voltage across the gate contact and the back contact (|V GB |) greater than a coercive voltage (V C ) associated with the PE/FE layer, wherein if the V GB is greater than V c , a P+ polarization is induced into the PE/FE layer, and if the V GB is less than −V c , a P− polarization is induced into the PE/FE layer.
This invention relates to a memory array incorporating a ferroelectric/piezoelectric (PE/FE) layer for non-volatile data storage. The technology addresses the need for high-density, low-power memory devices with fast write/read operations. The memory array includes memory cells with a gate contact and a back contact, where data is stored as polarization states in the PE/FE layer. Writing a bit value involves applying a voltage (V_GB) between the gate and back contacts. If the applied voltage exceeds a coercive voltage (V_C), the PE/FE layer polarizes in one direction (P+). If the voltage is below the negative coercive voltage (−V_C), the layer polarizes in the opposite direction (P−). These distinct polarization states represent binary data (e.g., 1 and 0). The memory array leverages the hysteresis behavior of ferroelectric materials to retain data without power, enabling non-volatile storage. The design ensures reliable switching between polarization states, facilitating efficient data writing and retention. This approach improves upon traditional memory technologies by combining the advantages of ferroelectric materials with scalable semiconductor fabrication techniques.
22. The memory array of claim 21 , wherein the PoSt FET memory cells that are not to be written to are governed by one of A) (|V GB |) is less than the coercive voltage for the associated PoSt FET memory cells; or B) substantially zero volts at the V GB , substantially zero volts across the gate contact and the source contact (V GS ), and substantially zero volts across the drain contact and the source contact (V DS ).
This invention relates to memory arrays incorporating PoSt FET (Programmable Spin Transfer Torque Ferroelectric Field-Effect Transistor) memory cells, addressing challenges in selectively writing data while minimizing unintended programming of adjacent cells. The memory array includes multiple PoSt FET memory cells, each with a ferroelectric layer and a magnetic layer, where data is stored based on the polarization state of the ferroelectric layer and the magnetization state of the magnetic layer. The invention focuses on controlling the gate bias voltage (V GB) and terminal voltages (V GS, V DS) to prevent unintended writing to cells that are not targeted for programming. For cells that should not be written, the gate bias voltage (|V GB|) is kept below the coercive voltage required to switch the ferroelectric layer, ensuring no polarization change occurs. Alternatively, the gate bias voltage (V GB) and terminal voltages (V GS, V DS) are maintained at substantially zero volts, preventing any voltage-induced switching. This selective control allows precise data writing while preserving the states of adjacent cells, improving memory array reliability and efficiency. The invention is particularly useful in high-density memory applications where minimizing unintended programming is critical.
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June 16, 2021
April 5, 2022
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