A computer-implemented method, according to one approach, is for calibrating read voltages associated with a block of memory having more than one word-line therein. The computer-implemented method includes: for each of the word-lines in the block: calculating an absolute shift value for a reference read voltage associated with the given word-line. A relative shift value is also determined for each of the remaining read voltages associated with the given word-line, and the relative shift values are determined with respect to the reference read voltage. Moreover, each of the read voltages associated with the given word-line are adjusted using the absolute shift value and each of the respective relative shift values.
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1. A computer-implemented method for calibrating read voltages associated with a block of memory having more than one word-line therein, comprising: for each of the word-lines in the block: calculating an absolute shift value for a reference read voltage associated with the given word-line, determining a relative shift value for each of the remaining read voltages associated with the given word-line, wherein the relative shift values are determined with respect to the reference read voltage, and adjusting each of the read voltages associated with the given word-line using the absolute shift value and each of the respective relative shift values.
2. The computer-implemented method of claim 1 , comprising: determining a current operating state of the block, wherein more than one read voltage is associated with each of the word-lines, wherein the relative shift values are determined for the remaining read voltages using a predetermined voltage mapping which corresponds to the current operating state of the block.
This invention relates to memory storage systems, specifically to techniques for optimizing read operations in non-volatile memory devices, such as flash memory. The problem addressed is the degradation of read accuracy over time due to factors like wear, temperature changes, and data retention issues, which can cause shifts in read voltage thresholds. Traditional methods use fixed read voltages, leading to increased error rates as memory cells age. The method involves dynamically adjusting read voltages for memory blocks based on their current operating state. Multiple read voltages are associated with each word-line, and the system determines the current state of the block to apply appropriate voltage adjustments. For the primary read voltage, a shift value is directly determined, while for the remaining read voltages, shift values are derived using a predetermined voltage mapping that corresponds to the block's current state. This ensures that all read voltages are optimized for the block's condition, improving read accuracy and reliability. The voltage mapping is preconfigured to account for expected shifts in different operating states, such as wear level, temperature, or retention time. By dynamically adjusting voltages, the method reduces read errors and extends the usable life of the memory device.
3. The computer-implemented method of claim 2 , wherein determining the relative shift value for each of the remaining read voltages associated with the given word-line includes: matching the current operating state of the block with a corresponding one of a number of predetermined operating states; and extracting the relative shift values from the predetermined voltage mapping which is assigned to the matching predetermined operating state.
The invention relates to a method for adjusting read voltages in a non-volatile memory system, particularly to optimize read operations in flash memory devices. The problem addressed is the degradation of memory cells over time, which affects the accuracy of read operations due to shifts in threshold voltage distributions. The method dynamically adjusts read voltages based on the current operating state of the memory block to improve data retrieval accuracy. The method involves determining a relative shift value for each read voltage associated with a given word-line. This is done by first matching the current operating state of the memory block with one of several predetermined operating states. Each operating state represents a different stage of memory wear or performance degradation. Once the matching state is identified, the method extracts the corresponding relative shift values from a predetermined voltage mapping assigned to that state. These shift values are then applied to adjust the read voltages, compensating for the shifts in threshold voltages caused by wear or other factors. The predetermined voltage mappings are pre-calibrated and stored, ensuring that the adjustments are based on reliable data. This approach allows the system to dynamically adapt to the memory block's condition, improving read accuracy without requiring extensive real-time calculations. The method is particularly useful in solid-state storage devices where maintaining data integrity over prolonged use is critical.
4. The computer-implemented method of claim 2 , wherein the current operating state of the block is determined using one or more statistics which correspond to the block, wherein the one or more statistics used to determine the current operating state of the block are selected from the group consisting of: a cycle count, a read disturb count, and a retention time.
This invention relates to a computer-implemented method for managing the operating state of a memory block, particularly in non-volatile memory systems such as flash memory. The method addresses the challenge of accurately assessing the health and performance of memory blocks to optimize data storage and retrieval operations. The key problem solved is determining the current operating state of a memory block using specific statistical metrics that reflect its usage and degradation over time. The method involves analyzing one or more statistics associated with the memory block to determine its operating state. These statistics include a cycle count, which tracks the number of program-erase cycles the block has undergone; a read disturb count, which measures the number of times neighboring blocks have been read, potentially causing interference; and a retention time, which indicates how long data has been stored in the block without being refreshed. By evaluating these metrics, the method can assess the block's wear level, reliability, and potential for errors, enabling better decision-making for data management, such as wear leveling, error correction, or block retirement. The approach ensures that memory operations are optimized based on real-time performance indicators, improving overall system efficiency and longevity.
5. The computer-implemented method of claim 1 , wherein the memory is non-volatile random access memory (NVRAM).
This invention relates to computer memory systems, specifically addressing the need for efficient and reliable data storage in non-volatile random access memory (NVRAM). Traditional memory systems often rely on volatile memory for fast access but require additional power or backup mechanisms to retain data during power loss. NVRAM combines the speed of RAM with the persistence of non-volatile storage, eliminating the need for external backup systems. The method involves using NVRAM as the primary memory for storing data, ensuring that information remains intact even when power is interrupted. The system is designed to handle data writes and reads efficiently, leveraging the low-latency characteristics of NVRAM while maintaining data integrity. The invention may include additional features such as wear-leveling algorithms to extend the lifespan of the NVRAM cells, error correction mechanisms to detect and correct data corruption, and power management techniques to optimize energy consumption. By integrating NVRAM into the memory architecture, the system provides a robust solution for applications requiring both high performance and data persistence, such as embedded systems, enterprise storage, and real-time computing environments. The use of NVRAM reduces the complexity and cost associated with traditional backup systems while improving overall system reliability.
6. The computer-implemented method of claim 5 , wherein the NVRAM includes three-dimensional triple-level-cell NAND Flash.
This invention relates to non-volatile random-access memory (NVRAM) systems, specifically addressing the need for high-density, high-performance storage solutions. The method involves using three-dimensional triple-level-cell (TLC) NAND Flash memory to enhance storage capacity and efficiency. Three-dimensional TLC NAND Flash allows each memory cell to store three bits of data, significantly increasing storage density compared to traditional single-level or multi-level cell designs. The three-dimensional architecture further improves performance by stacking memory cells vertically, reducing footprint and enabling higher storage capacities in compact form factors. This approach is particularly useful in applications requiring large-scale data storage, such as enterprise servers, solid-state drives, and embedded systems, where both high capacity and efficient data access are critical. The method ensures reliable data retention and fast read/write operations by leveraging the advanced structure of 3D TLC NAND Flash, which mitigates issues like cell interference and wear leveling. The invention optimizes memory management by integrating this high-density storage technology into existing systems, providing a cost-effective solution for expanding storage capabilities without compromising performance.
7. The computer-implemented method of claim 5 , wherein the NVRAM includes three-dimensional quad-level-cell NAND Flash.
This invention relates to a computer-implemented method for managing data storage in a non-volatile random-access memory (NVRAM) system, specifically utilizing three-dimensional quad-level-cell (QLC) NAND Flash memory. The method addresses the challenge of efficiently storing and retrieving data in high-density NAND Flash memory, which is prone to errors due to its multi-level cell (MLC) architecture. The system includes a controller that processes read and write operations for the NVRAM, which is structured as a three-dimensional array of QLC NAND Flash cells. Each cell stores four bits of data per cell, enabling high storage density but requiring sophisticated error correction and wear-leveling techniques to maintain reliability. The controller manages these operations by applying error correction codes (ECC) to mitigate data corruption and implements wear-leveling algorithms to distribute write operations evenly across the memory cells, extending the lifespan of the storage medium. The method also includes techniques for optimizing read and write performance, such as adaptive voltage adjustments and dynamic threshold voltage management, to compensate for variations in cell characteristics. The overall system aims to balance high storage density with reliable data integrity and performance in NAND Flash memory applications.
8. A computer program product for calibrating read voltages associated with a block of memory having more than one word-line therein, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable and/or executable by a processor to cause the processor to: for each of the word-lines in the block: calculate, by the processor, an absolute shift value for a reference read voltage associated with the given word-line, determine, by the processor, a relative shift value for each of the remaining read voltages associated with the given word-line, wherein the relative shift values are determined with respect to the reference read voltage, and adjust, by the processor, each of the read voltages associated with the given word-line using the absolute shift value and each of the respective relative shift values.
This invention relates to calibrating read voltages in non-volatile memory systems, particularly for memory blocks with multiple word-lines. The problem addressed is ensuring accurate data retrieval by compensating for voltage shifts that occur due to factors like wear, temperature, or manufacturing variations. The solution involves a computer program that dynamically adjusts read voltages for each word-line in a memory block. For each word-line, the program calculates an absolute shift value for a reference read voltage and determines relative shift values for other read voltages based on this reference. These shifts are then applied to adjust all read voltages associated with the word-line, improving read accuracy. The process is repeated for every word-line in the block, ensuring consistent performance across the entire memory. This approach enhances reliability by compensating for individual word-line characteristics and environmental changes, which is critical for maintaining data integrity in storage devices. The invention is particularly useful in flash memory and other non-volatile storage technologies where precise voltage calibration is essential for reliable data access.
9. The computer program product of claim 8 , wherein the program instructions are readable and/or executable by the processor to cause the processor to: determine, by the processor, a current operating state of the block, wherein more than one read voltage is associated with each of the word-lines, wherein the relative shift values are determined for the remaining read voltages using a predetermined voltage mapping which corresponds to the current operating state of the block.
This invention relates to memory storage systems, specifically non-volatile memory such as flash memory, and addresses the challenge of accurately reading data from memory cells by adjusting read voltages based on the operating state of the memory block. The system determines the current operating state of a memory block, where each word-line in the block is associated with multiple read voltages. For the remaining read voltages, the system calculates relative shift values using a predetermined voltage mapping that corresponds to the current operating state of the block. This approach ensures that read operations account for variations in memory cell behavior due to factors like wear, temperature, or other environmental conditions, improving data integrity and reliability. The voltage mapping is preconfigured to provide optimized read voltage adjustments tailored to different operating states, allowing the system to dynamically adapt read operations without requiring real-time calibration. This method enhances the accuracy of data retrieval in non-volatile memory systems, particularly in scenarios where memory cells exhibit shifting threshold voltage distributions over time.
10. The computer program product of claim 9 , wherein determining the relative shift value for each of the remaining read voltages associated with the given word-line includes: matching the current operating state of the block with a corresponding one of a number of predetermined operating states; and extracting the relative shift values from the predetermined voltage mapping which is assigned to the matching predetermined operating state.
This invention relates to non-volatile memory systems, specifically to methods for adjusting read voltages in flash memory to account for variations in memory cell behavior over time. The problem addressed is the degradation of read accuracy due to changes in memory cell characteristics, such as threshold voltage shifts, which occur as the memory cells age or undergo repeated read/write cycles. These shifts can lead to incorrect data retrieval if the read voltages are not properly adjusted. The invention provides a computer-implemented method for dynamically adjusting read voltages in a flash memory system. The method involves determining a relative shift value for each read voltage associated with a given word-line in the memory. This determination is based on the current operating state of the memory block containing the word-line. The operating state is matched to one of several predetermined operating states, each representing different stages of memory wear or usage. For each matched state, a corresponding set of relative shift values is extracted from a predefined voltage mapping table. These shift values are then applied to adjust the read voltages, ensuring accurate data retrieval despite changes in memory cell behavior. The voltage mapping table is preconfigured with shift values that correspond to different operating states, allowing the system to compensate for known degradation patterns. By dynamically selecting the appropriate shift values based on the current state of the memory block, the method improves read reliability and extends the usable lifespan of the memory device. This approach is particularly useful in solid-state storage systems where maintaining data integrity over long-term usage is critical.
11. The computer program product of claim 9 , wherein the current operating state of the block is determined using one or more statistics which correspond to the block, wherein the one or more statistics used to determine the current operating state of the block are selected from the group consisting of: a cycle count, a read disturb count, and a retention time.
This invention relates to a computer program product for managing the operating state of memory blocks, particularly in non-volatile memory systems like flash storage. The problem addressed is the degradation of memory blocks over time due to factors such as repeated read operations, write cycles, and data retention, which can lead to data corruption or reduced performance. The solution involves monitoring and determining the current operating state of a memory block using specific statistical metrics to assess its health and reliability. The invention determines the operating state of a memory block by analyzing one or more statistics associated with the block. These statistics include a cycle count, which tracks the number of program-erase cycles the block has undergone; a read disturb count, which measures the number of times neighboring cells have been read, potentially causing interference; and a retention time, which indicates how long data has been stored in the block without being refreshed. By evaluating these metrics, the system can assess the block's wear level, susceptibility to errors, and remaining useful life. This information can then be used to optimize memory management, such as relocating data from degraded blocks or triggering maintenance operations to prolong the lifespan of the storage device. The approach ensures reliable data storage by proactively addressing potential failures based on measurable degradation indicators.
12. The computer program product of claim 8 , wherein the memory is non-volatile random access memory (NVRAM).
This invention relates to computer memory systems, specifically addressing the need for efficient and reliable data storage in computing devices. The invention involves a computer program product that includes a memory module, where the memory is non-volatile random access memory (NVRAM). NVRAM retains data even when power is removed, combining the speed of RAM with the persistence of traditional storage. The memory module is configured to store data in a manner that allows for fast read and write operations while ensuring data integrity. The system may include additional components such as a processor and a controller to manage data access and storage operations. The use of NVRAM eliminates the need for frequent data transfers between volatile and non-volatile storage, reducing latency and improving overall system performance. The invention is particularly useful in applications requiring high-speed data access with persistent storage, such as embedded systems, enterprise computing, and real-time data processing. The memory module may also include error correction mechanisms to enhance data reliability. By integrating NVRAM, the system achieves a balance between performance and durability, making it suitable for environments where data loss prevention and rapid access are critical.
13. The computer program product of claim 12 , wherein the NVRAM includes three-dimensional triple-level-cell NAND Flash.
This invention relates to a computer program product for managing data storage in a non-volatile random-access memory (NVRAM) system, specifically addressing the challenge of efficiently storing and retrieving data in high-density memory devices. The system utilizes three-dimensional triple-level-cell (3D TLC) NAND Flash memory, which offers higher storage density but introduces complexities in data management due to its multi-level cell structure and three-dimensional architecture. The computer program product includes instructions for executing a method that optimizes data storage and retrieval operations in such memory systems. The method involves determining a storage location within the NVRAM for incoming data, where the NVRAM is configured to store multiple bits per memory cell, and the storage location is selected based on factors such as wear leveling, error correction, and performance optimization. The program also handles data retrieval by accessing the stored data from the determined location and ensuring data integrity through error detection and correction mechanisms. The use of 3D TLC NAND Flash allows for increased storage capacity while maintaining reliable data access, addressing the need for efficient data management in high-density memory systems. The invention focuses on improving the reliability and performance of data storage operations in advanced NVRAM technologies.
14. The computer program product of claim 12 , wherein the NVRAM includes three-dimensional quad-level-cell NAND Flash.
This invention relates to non-volatile random access memory (NVRAM) systems, specifically addressing the challenge of improving storage density and performance in memory devices. The technology involves a computer program product that manages data storage in NVRAM, where the NVRAM includes three-dimensional quad-level-cell (QLC) NAND Flash memory. QLC NAND Flash stores four bits per cell, enabling higher storage density compared to traditional single-level-cell (SLC), multi-level-cell (MLC), or triple-level-cell (TLC) NAND. The system optimizes data handling, error correction, and wear leveling to mitigate the inherent reliability challenges of QLC NAND, such as higher error rates and reduced endurance. The program product may include algorithms for efficient data encoding, decoding, and error recovery, ensuring reliable operation despite the increased complexity of storing multiple bits per cell. Additionally, the system may incorporate techniques for managing read/write operations to prolong the lifespan of the memory cells. The invention is particularly useful in applications requiring high-capacity storage with cost-effective solutions, such as solid-state drives (SSDs) and embedded storage systems. By leveraging three-dimensional QLC NAND, the technology provides a balance between storage density, performance, and cost.
15. A system, comprising: a plurality of non-volatile random access memory (NVRAM) blocks configured to store data, wherein the blocks include more than one word-line therein; a processor; and logic integrated with and/or executable by the processor, the logic being configured to: for each of the word-lines in a given block: calculate, by the processor, an absolute shift value for a reference read voltage associated with the given word-line, determine, by the processor, a relative shift value for each remaining read voltage associated with the given word-line, wherein the relative shift values are determined with respect to the reference read voltage, and adjust, by the processor, each of the read voltages associated with the given word-line using the absolute shift value and each of the respective relative shift values.
This invention relates to a system for optimizing read voltage adjustments in non-volatile random access memory (NVRAM) blocks, particularly those with multiple word-lines. The system addresses the challenge of maintaining accurate data retrieval in NVRAM as memory cells degrade over time, which can cause read voltage shifts and lead to read errors. The system includes multiple NVRAM blocks, each containing more than one word-line, and a processor with integrated logic. For each word-line in a selected block, the processor calculates an absolute shift value for a reference read voltage. This reference voltage serves as a baseline for the word-line. The processor then determines relative shift values for the remaining read voltages associated with the same word-line, where these relative shifts are calculated with respect to the reference read voltage. Finally, the processor adjusts all read voltages for the word-line using the absolute shift value and the respective relative shift values. This approach ensures that read voltages are dynamically adjusted to compensate for cell degradation, improving data integrity and reliability in NVRAM storage. The system is particularly useful in high-density memory applications where precise voltage adjustments are critical for accurate data retrieval.
16. The system of claim 15 , wherein the logic is configured to: determine, by the processor, a current operating state of the given block, wherein more than one read voltage is associated with each of the word-lines, wherein the relative shift values are determined for the remaining read voltages using a predetermined voltage mapping which corresponds to the current operating state of the given block.
The invention relates to a memory system, specifically a non-volatile memory system such as NAND flash, that improves read operations by dynamically adjusting read voltages based on the current operating state of a memory block. The problem addressed is the degradation of read accuracy over time due to factors like wear, temperature changes, and data retention issues, which cause threshold voltage distributions to shift unpredictably. Traditional systems use fixed read voltages, leading to increased read errors as the memory block ages. The system includes logic that determines the current operating state of a given memory block, where each word-line in the block is associated with multiple read voltages. Instead of using a single fixed read voltage, the system applies a predetermined voltage mapping tailored to the block's current state. This mapping adjusts the remaining read voltages based on relative shift values, ensuring optimal read accuracy. The logic dynamically selects the appropriate read voltages to compensate for shifts in threshold voltage distributions, reducing read errors and improving data integrity. The system may also track historical data or environmental conditions to refine the voltage adjustments further. This approach enhances reliability in long-term storage and high-density memory applications.
17. The system of claim 16 , wherein determining the relative shift value for each of the remaining read voltages associated with the given word-line includes: matching the current operating state of the given block with a corresponding one of a number of predetermined operating states; and extracting the relative shift values from the predetermined voltage mapping which is assigned to the matching predetermined operating state.
The system relates to memory storage, specifically to adjusting read voltages in non-volatile memory devices to account for shifts in threshold voltage distributions over time. The problem addressed is the degradation of read accuracy due to changes in memory cell characteristics, such as those caused by program/erase cycles, retention effects, or temperature variations. The system dynamically adjusts read voltages to maintain reliable data retrieval. The system includes a memory controller that monitors the operating state of a memory block, which may include factors like the number of program/erase cycles, retention time, or temperature. Based on this state, the controller selects a predetermined voltage mapping from a set of mappings, each associated with a specific operating condition. The voltage mapping defines relative shift values for read voltages applied to a word-line. These shifts compensate for threshold voltage distribution shifts, ensuring accurate data reading. The system further includes a mechanism to determine the relative shift values for each read voltage associated with a given word-line. This involves matching the current operating state of the block to a corresponding predetermined state and then extracting the appropriate shift values from the assigned voltage mapping. The adjustments are applied to the read voltages to improve read accuracy under varying operating conditions. The system may also include a calibration process to update the voltage mappings based on observed memory behavior, ensuring long-term reliability.
18. The system of claim 16 , wherein the current operating state of the given block is determined using one or more statistics which correspond to the block, wherein the one or more statistics used to determine the current operating state of the given block are selected from the group consisting of: a cycle count, a read disturb count, and a retention time.
The system monitors and manages the operating state of memory blocks, particularly in non-volatile storage devices like flash memory, to improve reliability and performance. The system tracks key performance indicators (KPIs) for each memory block to assess its health and predict potential failures. These KPIs include a cycle count (number of program-erase cycles), a read disturb count (number of times adjacent blocks were read, which can degrade data integrity), and retention time (duration data has been stored without refresh). By analyzing these statistics, the system determines the current operating state of a given block, enabling proactive measures such as data migration, wear leveling, or error correction to extend the block's lifespan and prevent data loss. The system dynamically selects the most relevant statistics for each block to optimize decision-making, ensuring efficient resource utilization and maintaining storage reliability. This approach is particularly useful in solid-state drives (SSDs) and other high-density storage systems where memory endurance and data integrity are critical.
19. The system of claim 15 , wherein at least some of the NVRAM blocks are included in three-dimensional triple-level-cell NAND Flash.
This invention relates to a data storage system that uses non-volatile random-access memory (NVRAM) blocks, particularly in three-dimensional triple-level-cell (3D TLC) NAND Flash memory. The system is designed to address challenges in data storage efficiency, reliability, and performance, especially in high-density memory architectures where traditional storage methods may suffer from increased error rates or slower access times. The system includes a controller configured to manage data operations across multiple NVRAM blocks, which may be organized in a hierarchical or distributed manner to optimize storage and retrieval. The controller ensures data integrity by implementing error correction and wear-leveling techniques, which are critical in 3D TLC NAND Flash due to its higher cell density and susceptibility to wear. The system may also incorporate adaptive programming techniques to adjust voltage levels and improve endurance. At least some of the NVRAM blocks are implemented in 3D TLC NAND Flash, which provides higher storage density compared to single-level-cell (SLC) or multi-level-cell (MLC) NAND. However, 3D TLC NAND requires sophisticated management to mitigate issues like increased read/write latency and higher error rates. The system addresses these challenges by dynamically allocating data across blocks, balancing workloads, and applying advanced error correction algorithms tailored for TLC memory. The invention is particularly useful in applications requiring high-capacity, cost-effective storage with reliable performance, such as solid-state drives (SSDs), enterprise storage systems, and embedded memory solutions. The use of 3D TLC NAND Flash allows for compact, high-density storage while maintaining data integrity through intelligent management techni
20. The system of claim 15 , wherein at least some of the NVRAM blocks are included in three-dimensional quad-level-cell NAND Flash.
A system for data storage and retrieval includes a non-volatile random-access memory (NVRAM) configured to store data in a three-dimensional quad-level-cell (QLC) NAND Flash architecture. The NVRAM comprises multiple blocks, with at least some of these blocks implemented using QLC NAND Flash, which allows for higher storage density by storing four bits per cell. This system is designed to address the need for efficient, high-capacity data storage solutions, particularly in applications requiring large-scale data retention with improved density and cost-effectiveness. The use of three-dimensional QLC NAND Flash enhances storage capacity while maintaining performance and reliability. The system may also include additional components such as controllers, interfaces, and error correction mechanisms to manage data operations, ensuring data integrity and access speed. The integration of QLC NAND Flash in the NVRAM blocks enables the system to support high-density storage requirements while optimizing power consumption and physical space utilization. This approach is particularly beneficial in data centers, enterprise storage systems, and other environments where large-scale, cost-effective storage solutions are essential. The system may further include features for wear leveling, bad block management, and data encryption to enhance durability and security.
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January 14, 2021
April 12, 2022
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