A device for handling a semiconductor wafer in an epitaxy reactor has a susceptor; longitudinal holes extending through the susceptor; a wafer lifting shaft; wafer lifting pins guided through the longitudinal holes; a susceptor carrying shaft; susceptor carrying arms; susceptor support pins; guide sleeves anchored in the susceptor carrying arms; and guide elements protruding from the guide sleeves which, at upper ends, have bores into which wafer lifting pins are inserted, and which can be raised and lowered together with the wafer lifting pins by the wafer lifting shaft.
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1. A device for handling a semiconductor wafer in an epitaxy reactor, comprising: a susceptor; longitudinal holes extending through the susceptor; a wafer lifting shaft; wafer lifting pins made of silicon carbide, which are guided through the longitudinal holes; a susceptor carrying shaft; susceptor carrying arms; susceptor support pins; guide sleeves, which are anchored in the susceptor carrying arms; and guide elements consisting of quartz and slidable within the guide sleeves, which protrude upwardly from the guide sleeves and, at upper ends thereof, have bores into which the wafer lifting pins are inserted, and which can be raised and lowered together with the wafer lifting pins by means of the wafer lifting shaft, wherein the guide elements have a different thermal expansion as compared to the wafer lifting pins, and the wafer lifting pins and guide elements are dimensioned such that the wafer lifting pins are connected to the guide elements in a clamping fashion at temperatures greater than 900° C.
This invention relates to a device for handling semiconductor wafers in an epitaxy reactor, addressing the challenge of precise wafer positioning and thermal stability during high-temperature processing. The device includes a susceptor with longitudinal holes through which silicon carbide wafer lifting pins are guided. A wafer lifting shaft raises and lowers the pins, enabling wafer transfer. The susceptor is supported by a carrying shaft, carrying arms, and support pins. Guide sleeves anchored in the carrying arms house quartz guide elements, which slide within the sleeves and protrude upward. These guide elements have bores that receive the wafer lifting pins, allowing them to move together. The guide elements and wafer lifting pins have different thermal expansion properties, ensuring a clamping connection at temperatures exceeding 900°C. This design maintains precise alignment and stability during high-temperature epitaxial growth, preventing wafer misalignment or damage. The use of silicon carbide for the lifting pins and quartz for the guide elements ensures compatibility with the harsh chemical and thermal conditions of epitaxy reactors. The system enables efficient wafer handling while minimizing thermal stress and contamination risks.
2. The device of claim 1 , wherein the susceptor carrying arms form a one-piece star-shaped element, which is screwed onto an upper end of the susceptor carrying shaft.
A device for semiconductor processing includes a susceptor carrying mechanism designed to support and rotate a susceptor within a processing chamber. The susceptor carrying arms are integrated into a single, star-shaped element, which is rigidly attached to the upper end of a susceptor carrying shaft via a screw connection. This one-piece design ensures structural stability and precise alignment of the susceptor during operation. The star-shaped configuration of the arms allows for even distribution of weight and thermal load, reducing mechanical stress and improving rotational balance. The screw attachment method provides a secure and adjustable connection, enabling easy assembly and maintenance while maintaining alignment accuracy. This design is particularly useful in semiconductor manufacturing processes where precise control of susceptor movement is critical for uniform deposition or etching. The integrated arm structure minimizes vibration and enhances process repeatability, contributing to higher yield and reliability in semiconductor fabrication.
3. The device of claim 1 , wherein the clamping force is sufficient so as to prevent radial play of the wafer lifting pins.
A wafer handling system includes a mechanism for lifting and supporting semiconductor wafers during processing. The system addresses the challenge of maintaining precise wafer positioning by incorporating lifting pins that engage with the wafer's edge. A key feature is the application of a clamping force to these lifting pins to eliminate radial play, ensuring stable and accurate wafer alignment. The clamping force is applied through a mechanical or pneumatic mechanism that securely locks the pins in place, preventing any unwanted movement during wafer transfer or processing. This design enhances process reliability by minimizing positional deviations that could lead to defects or misalignment. The system is particularly useful in semiconductor manufacturing environments where precision and repeatability are critical. The clamping mechanism may include adjustable components to accommodate different wafer sizes or processing requirements, ensuring versatility across various applications. By eliminating radial play, the system improves yield and reduces the risk of damage to delicate wafer surfaces. The overall design integrates seamlessly with existing semiconductor processing equipment, providing a robust solution for high-precision wafer handling.
4. The device of claim 1 , wherein the wafer lifting pins self-center upon inserting into bores of the guide elements at room temperature.
A semiconductor wafer handling system includes a wafer support platform with multiple guide elements and wafer lifting pins. The guide elements are positioned around the platform and have bores that align with corresponding holes in the platform. The wafer lifting pins are inserted into these bores to support and lift the wafer during processing. The lifting pins are designed to self-center within the bores at room temperature, ensuring precise alignment and stability. This self-centering mechanism prevents misalignment during wafer handling, reducing the risk of damage or contamination. The system improves wafer positioning accuracy, which is critical for high-precision semiconductor manufacturing processes. The guide elements may be adjustable to accommodate different wafer sizes or processing requirements. The lifting pins are typically made of a material with low thermal expansion to maintain alignment across varying temperatures. This design enhances the reliability and efficiency of wafer handling in semiconductor fabrication.
5. The device of claim 1 , further comprising upright elements, which are connected height-adjustably to the susceptor carrying arms at the outer ends of the latter and have axial bores into which the susceptor support pins are inserted, the susceptor support pins having spherically rounded heads.
This invention relates to a device for supporting and positioning a susceptor in a semiconductor processing system, particularly for applications requiring precise temperature control and alignment. The device addresses the challenge of maintaining stable and adjustable support for a susceptor, which is a critical component in processes like chemical vapor deposition (CVD) or epitaxial growth, where thermal uniformity and positional accuracy are essential. The device includes a susceptor carrying mechanism with arms that extend outward to support the susceptor. Attached to the outer ends of these arms are upright elements, which are height-adjustable to accommodate variations in susceptor thickness or processing requirements. These upright elements feature axial bores that receive susceptor support pins. The support pins have spherically rounded heads, allowing for self-alignment and reducing stress concentrations during thermal expansion or mechanical adjustments. This design ensures that the susceptor remains level and properly positioned, even under high-temperature conditions. The height-adjustable connection between the upright elements and the carrying arms enables fine-tuning of the susceptor's position, while the spherical heads of the support pins minimize wear and improve stability. This configuration enhances process repeatability and reduces the risk of defects caused by misalignment or uneven heating. The invention is particularly useful in semiconductor manufacturing, where precise control of the susceptor's position is critical for achieving uniform deposition or growth across the substrate.
6. The device of claim 5 , further comprising elongate blind holes on a rear side of the susceptor for receiving the spherically rounded heads of the susceptor support pins, the length and width of the blind holes increasing in a direction of the opening of the blind holes.
This invention relates to a susceptor support system for semiconductor processing, particularly addressing the challenge of precise alignment and thermal stability in high-temperature environments. The device includes a susceptor with a rear side featuring elongate blind holes designed to receive spherically rounded heads of support pins. These blind holes have a tapered geometry, where both length and width increase toward the opening, ensuring secure engagement with the pin heads while accommodating thermal expansion and misalignment. The tapered design allows for self-centering of the pins within the holes, reducing stress and improving positional accuracy during heating cycles. The support pins, with their rounded heads, distribute load evenly and minimize point contact, enhancing durability and thermal uniformity. This configuration is particularly useful in semiconductor manufacturing, where precise temperature control and mechanical stability are critical for wafer processing. The system ensures consistent contact between the susceptor and support structure, preventing warping or displacement under thermal stress. The invention improves upon prior art by combining tapered blind holes with spherical pin heads, optimizing both alignment and load distribution in high-temperature applications.
7. A method for producing a semiconductor wafer having an epitaxial layer, comprising: providing a device of claim 1 an epitaxy reactor; placing a semiconductor wafer on the wafer lifting pins; placing the semiconductor wafer on the susceptor by lowering the wafer lifting pins; depositing an epitaxial layer on the semiconductor wafer to form an epitaxially coated semiconductor wafer; raising the epitaxially coated semiconductor wafer from the susceptor by raising the wafer lifting pins; and removing the semiconductor wafer with the epitaxial layer from the epitaxy reactor.
This invention relates to semiconductor manufacturing, specifically a method for producing a semiconductor wafer with an epitaxial layer using an epitaxy reactor. The process addresses challenges in handling and processing semiconductor wafers during epitaxial growth, ensuring precise placement and removal to maintain wafer integrity and deposition quality. The method begins with an epitaxy reactor equipped with a susceptor and wafer lifting pins. A semiconductor wafer is initially placed on the lifting pins, which are then lowered to position the wafer onto the susceptor. The susceptor heats the wafer, and an epitaxial layer is deposited onto its surface, forming an epitaxially coated wafer. After deposition, the lifting pins are raised to lift the coated wafer from the susceptor, and the wafer is then removed from the reactor. The lifting pins facilitate controlled wafer handling, preventing damage during transfer and ensuring proper alignment on the susceptor. The method ensures consistent epitaxial deposition by maintaining wafer stability throughout the process. This approach is particularly useful in semiconductor fabrication where precise layer deposition and wafer integrity are critical.
8. A method for producing a semiconductor wafer having an epitaxial layer, comprising: providing a device of claim 2 an epitaxy reactor; placing a semiconductor wafer on the wafer lifting pins; placing the semiconductor wafer on the susceptor by lowering the wafer lifting pins; depositing an epitaxial layer on the semiconductor wafer to form an epitaxially coated semiconductor wafer; raising the epitaxially coated semiconductor wafer from the susceptor by raising the wafer lifting pins; and removing the semiconductor wafer with the epitaxial layer from the epitaxy reactor.
This invention relates to semiconductor manufacturing, specifically a method for producing a semiconductor wafer with an epitaxial layer using an epitaxy reactor. The process addresses challenges in handling wafers during epitaxial growth, ensuring precise placement and removal to maintain wafer integrity and deposition quality. The method begins with an epitaxy reactor equipped with a susceptor and wafer lifting pins. A semiconductor wafer is initially placed on the lifting pins, which are then lowered to position the wafer onto the susceptor. The susceptor heats the wafer, and an epitaxial layer is deposited onto its surface. After deposition, the lifting pins raise the wafer from the susceptor, allowing it to be removed from the reactor. The lifting pins facilitate controlled wafer movement, preventing damage during transfer and ensuring proper alignment on the susceptor. This method improves efficiency and yield in epitaxial growth processes by minimizing handling errors and maintaining consistent deposition conditions. The technique is applicable to various semiconductor manufacturing applications requiring high-quality epitaxial layers.
9. A method for producing a semiconductor wafer having an epitaxial layer, comprising: providing a device of claim 3 in an epitaxy reactor; placing a semiconductor wafer on the wafer lifting pins; placing the semiconductor wafer on the susceptor by lowering the wafer lifting pins; depositing an epitaxial layer on the semiconductor wafer to form an epitaxially coated semiconductor wafer; raising the epitaxially coated semiconductor wafer from the susceptor by raising the wafer lifting pins; and removing the semiconductor wafer with the epitaxial layer from the epitaxy reactor.
This invention relates to semiconductor wafer processing, specifically a method for producing a semiconductor wafer with an epitaxial layer in an epitaxy reactor. The method addresses challenges in handling wafers during epitaxial growth, such as precise positioning and contamination control. The process begins by providing an epitaxy reactor equipped with a susceptor and wafer lifting pins. A semiconductor wafer is placed on the lifting pins, which then lower the wafer onto the susceptor. An epitaxial layer is deposited onto the wafer, forming an epitaxially coated semiconductor wafer. The lifting pins then raise the coated wafer from the susceptor, allowing it to be removed from the reactor. The susceptor is a rotating platform that holds the wafer during deposition, while the lifting pins ensure controlled placement and retrieval. This method improves wafer handling efficiency and reduces contamination risks during epitaxial growth. The invention is particularly useful in semiconductor manufacturing where precise layer deposition and minimal contamination are critical.
10. A method for producing a semiconductor wafer having an epitaxial layer, comprising: providing a device of claim 5 in an epitaxy reactor; placing a semiconductor wafer on the wafer lifting pins; placing the semiconductor wafer on the susceptor by lowering the wafer lifting pins; depositing an epitaxial layer on the semiconductor wafer to form an epitaxially coated semiconductor wafer; raising the epitaxially coated semiconductor wafer from the susceptor by raising the wafer lifting pins; and removing the semiconductor wafer with the epitaxial layer from the epitaxy reactor.
The invention relates to semiconductor wafer processing, specifically a method for producing a semiconductor wafer with an epitaxial layer in an epitaxy reactor. The method addresses challenges in handling and processing semiconductor wafers during epitaxial deposition, ensuring precise placement and removal to maintain wafer integrity and deposition quality. The process begins by providing an epitaxy reactor equipped with a susceptor and wafer lifting pins. The susceptor is a heated platform that supports the wafer during deposition, while the lifting pins are movable elements that facilitate wafer placement and removal. A semiconductor wafer is initially placed on the lifting pins, which are then lowered to position the wafer onto the susceptor. The epitaxial layer is then deposited onto the wafer, forming an epitaxially coated semiconductor wafer. After deposition, the lifting pins are raised to lift the coated wafer from the susceptor. The wafer is then removed from the reactor, completing the process. This method ensures controlled handling of the wafer throughout the epitaxial deposition, minimizing damage and maintaining process consistency. The lifting pins and susceptor work in tandem to enable efficient wafer transfer and deposition, improving yield and quality in semiconductor manufacturing.
11. The method of claim 7 , wherein the epitaxial layer is deposited on a semiconductor wafer of monocrystalline silicon.
This invention relates to semiconductor fabrication, specifically the deposition of epitaxial layers on semiconductor wafers. The problem addressed is improving the quality and uniformity of epitaxial growth on semiconductor substrates, particularly monocrystalline silicon wafers. The method involves depositing an epitaxial layer on a semiconductor wafer composed of monocrystalline silicon. The epitaxial deposition process ensures that the crystalline structure of the deposited layer matches the underlying substrate, enhancing electrical and structural properties. The semiconductor wafer serves as the base material, and the epitaxial layer is grown on its surface through controlled chemical vapor deposition (CVD) or other suitable techniques. The monocrystalline silicon substrate provides a defect-free lattice structure, enabling high-quality epitaxial growth with minimal dislocations or impurities. This process is critical for manufacturing advanced semiconductor devices, such as transistors and integrated circuits, where precise material properties are essential. The invention focuses on optimizing the deposition conditions to achieve uniform thickness, high purity, and defect-free epitaxial layers, which are necessary for high-performance electronic applications.
12. The device of claim 1 , wherein a portion of the wafer lifting pin which is inserted into the bore of the guide elements is cylindrical, and the bore of the guide element which receives the lifting pin is in the form of a cylindrical bore.
The invention relates to semiconductor wafer handling systems, specifically focusing on the design of wafer lifting pins and their interaction with guide elements. The problem addressed is ensuring precise and stable vertical movement of wafer lifting pins during semiconductor processing, particularly to prevent misalignment or binding that could damage wafers or processing equipment. The device includes a wafer lifting pin with a cylindrical portion that inserts into a corresponding cylindrical bore within a guide element. The cylindrical bore in the guide element is designed to receive and guide the lifting pin, ensuring smooth and accurate vertical motion. This design minimizes lateral movement and misalignment, improving the reliability of wafer transfer operations. The cylindrical interface between the lifting pin and guide element reduces friction and wear, enhancing the longevity of the system. The guide element may also include additional features, such as a tapered or stepped bore, to further refine the alignment and stability of the lifting pin during operation. The overall system ensures consistent wafer handling, reducing defects and improving yield in semiconductor manufacturing processes.
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July 3, 2017
April 12, 2022
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