A semiconductor package that effectively controls heat generated from a semiconductor chip is provided. A semiconductor device with improved product reliability and performance is provided. A semiconductor package comprises a substrate including a first surface and a second surface facing each other, a first semiconductor chip and a second semiconductor chip disposed on the first surface of the substrate, a first heat spreader formed on the first semiconductor chip and the second semiconductor chip, and a second heat spreader which protrudes from the first heat spreader and covers an upper part of the first semiconductor chip, wherein the first semiconductor chip includes a first side wall extending in a first direction, the second semiconductor chip includes a second side wall extending in the first direction and facing the first side wall of the first semiconductor chip in a second direction intersecting the first direction, and an area of the second heat spreader at a boundary between the first heat spreader and the second heat spreader is smaller than or equal to an area of an upper surface of the first semiconductor chip.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor package comprising: a substrate including a first surface and a second surface facing each other; a first semiconductor chip and a second semiconductor chip disposed on the first surface of the substrate; a first heat spreader formed on the first semiconductor chip and the second semiconductor chip; and a second heat spreader which protrudes from the first heat spreader and covers the first semiconductor chip, wherein the first semiconductor chip includes a first side wall extending in a first direction, the second semiconductor chip includes a second side wall extending in the first direction and facing the first side wall of the first semiconductor chip in a second direction intersecting the first direction, and an area of the second heat spreader at a boundary between the first heat spreader and the second heat spreader is smaller than or equal to an area of an upper surface of the first semiconductor chip.
This invention relates to semiconductor packaging, specifically addressing thermal management in multi-chip packages. The technology solves the problem of uneven heat dissipation in semiconductor packages containing multiple chips, where some chips generate more heat than others. The solution involves a substrate with two opposing surfaces, where a first and second semiconductor chip are mounted on one surface. A first heat spreader is formed over both chips to distribute heat. A second heat spreader protrudes from the first heat spreader and covers only the first semiconductor chip, which likely generates more heat. The second heat spreader's coverage area at the boundary with the first heat spreader is smaller than or equal to the upper surface area of the first semiconductor chip. The chips are arranged such that their side walls face each other in a direction perpendicular to their length. This design ensures targeted heat dissipation from the hotter chip while maintaining structural integrity and efficient thermal management. The invention improves thermal performance in multi-chip semiconductor packages by providing localized heat spreading without interfering with adjacent components.
2. The semiconductor package of claim 1 , wherein a side wall of the second heat spreader and the second side wall of the second semiconductor chip are spaced apart from each other.
This invention relates to semiconductor packaging, specifically addressing thermal management and structural integrity in multi-chip packages. The technology involves a semiconductor package with multiple heat spreaders and semiconductor chips, where the spacing between a side wall of a second heat spreader and a second side wall of a second semiconductor chip is controlled to improve heat dissipation and mechanical stability. The package includes a first semiconductor chip and a first heat spreader, with the second semiconductor chip and second heat spreader stacked or arranged in a way that minimizes thermal interference while maintaining structural support. The spacing between the side walls prevents direct contact, reducing thermal resistance and potential stress concentrations that could lead to failure. This design enhances heat transfer efficiency by allowing better airflow or thermal interface material placement between the components. The invention is particularly useful in high-performance computing and power electronics, where effective heat management is critical for reliability and performance. The controlled spacing also simplifies manufacturing by reducing alignment tolerances and assembly complexity. Overall, the invention provides a robust solution for thermal and mechanical challenges in advanced semiconductor packaging.
3. The semiconductor package of claim 1 , wherein the first semiconductor chip includes a logic chip, and the second semiconductor chip includes a high bandwidth memory in which a plurality of chips are stacked.
A semiconductor package integrates multiple semiconductor chips to enhance performance and efficiency. The package includes a first semiconductor chip, which is a logic chip, and a second semiconductor chip, which is a high bandwidth memory (HBM) module. The HBM module consists of multiple memory chips stacked vertically to achieve high data bandwidth and density. The logic chip and the HBM module are interconnected within the package to enable fast data transfer between them. This configuration is particularly useful in high-performance computing applications, such as data centers, artificial intelligence, and graphics processing, where low latency and high throughput are critical. The stacked memory design reduces the physical footprint while increasing memory capacity and bandwidth compared to traditional memory architectures. The integration of the logic chip and HBM module in a single package minimizes signal delays and power consumption, improving overall system efficiency. This approach addresses the limitations of conventional memory architectures by providing a compact, high-performance solution for demanding computational tasks.
4. The semiconductor package of claim 3 , wherein the second semiconductor chip includes twelve or more stacked sub-semiconductor memory chips.
The invention relates to a semiconductor package designed to enhance memory capacity and performance in electronic devices. The package addresses the challenge of integrating high-density memory solutions within compact form factors while maintaining reliable electrical connections and thermal management. The semiconductor package includes a first semiconductor chip, such as a logic chip, and a second semiconductor chip, which is a memory chip. The second semiconductor chip is specifically configured with twelve or more stacked sub-semiconductor memory chips, significantly increasing memory density without expanding the package footprint. This stacked arrangement allows for efficient vertical integration, reducing the need for additional horizontal space while improving data access speeds and overall system performance. The package may also include interconnect structures to facilitate communication between the logic chip and the stacked memory chips, ensuring low-latency data transfer. The design is particularly useful in high-performance computing, mobile devices, and embedded systems where space constraints and memory demands are critical. The stacked memory configuration enables scalable memory solutions, accommodating future advancements in semiconductor technology while maintaining compatibility with existing system architectures.
5. The semiconductor package of claim 1 , wherein a distance between the first side wall of the first semiconductor chip and the second side wall of the second semiconductor chip is 150 μm or less.
The invention relates to semiconductor packaging, specifically addressing the challenge of minimizing the spacing between adjacent semiconductor chips to improve integration density and performance. The semiconductor package includes at least two semiconductor chips, each with a first side wall and a second side wall. The key innovation is that the distance between the first side wall of the first semiconductor chip and the second side wall of the second semiconductor chip is 150 micrometers or less. This tight spacing reduces the overall footprint of the package, enabling higher integration density and improved electrical performance by shortening signal paths. The package may also include a substrate with conductive pads and a molding compound encapsulating the chips. The chips are electrically connected to the substrate via bonding wires or other interconnects. The tight spacing between the chips is achieved through precise alignment and assembly techniques, ensuring reliable operation while maintaining structural integrity. This design is particularly useful in applications requiring compact, high-performance semiconductor packages, such as advanced computing, memory modules, and integrated circuits.
6. The semiconductor package of claim 1 , wherein the second heat spreader covers the upper surface of the first semiconductor chip, and an area of the second heat spreader which covers the upper surface of the first semiconductor chip is greater than the area of the second heat spreader at the boundary between the first heat spreader and the second heat spreader.
A semiconductor package is designed to improve heat dissipation in electronic devices. The package includes a first semiconductor chip mounted on a substrate, a first heat spreader thermally coupled to the first semiconductor chip, and a second heat spreader thermally coupled to the first heat spreader. The second heat spreader extends over the upper surface of the first semiconductor chip, providing additional cooling. The area of the second heat spreader covering the first semiconductor chip is larger than the area at the boundary where the second heat spreader connects to the first heat spreader. This design ensures efficient heat transfer from the semiconductor chip to the heat spreaders, reducing thermal resistance and improving overall thermal performance. The second heat spreader may be made of a material with high thermal conductivity, such as copper or aluminum, to further enhance heat dissipation. The package may also include additional components, such as a second semiconductor chip stacked on the first semiconductor chip, with the second heat spreader covering both chips to provide uniform cooling. The substrate may be a printed circuit board or another insulating material, and the heat spreaders may be attached using thermal interface materials to minimize thermal resistance. This configuration is particularly useful in high-performance computing and power electronics, where effective heat management is critical.
7. The semiconductor package of claim 1 , wherein the second heat spreader covers the upper surface of the first semiconductor chip, and an area of the second heat spreader which covers the upper surface of the first semiconductor chip is smaller than the area of the second heat spreader at the boundary between the first heat spreader and the second heat spreader.
A semiconductor package design addresses thermal management challenges in high-performance integrated circuits. The package includes a first semiconductor chip mounted on a substrate, a first heat spreader attached to the substrate, and a second heat spreader positioned above the first chip. The second heat spreader covers the upper surface of the first semiconductor chip but has a smaller coverage area directly above the chip compared to its boundary area where it connects to the first heat spreader. This tapered design improves heat dissipation by increasing the surface area for heat transfer at the interface between the two heat spreaders while minimizing thermal resistance over the active regions of the chip. The first heat spreader provides structural support and additional heat spreading, while the second heat spreader enhances localized cooling for the semiconductor chip. The configuration ensures efficient heat flow from the chip to the surrounding environment, reducing thermal hotspots and improving overall device reliability. The package is particularly useful in applications requiring high thermal performance, such as advanced computing and power electronics.
8. The semiconductor package of claim 1 , wherein the second heat spreader covers the upper surface of the first semiconductor chip, and an area of the second heat spreader which covers the upper surface of the first semiconductor chip is smaller than or equal to the area of the upper surface of the first semiconductor chip.
A semiconductor package includes a first semiconductor chip and a second heat spreader. The second heat spreader is positioned to cover the upper surface of the first semiconductor chip, with its coverage area being smaller than or equal to the area of the upper surface of the first semiconductor chip. This configuration ensures efficient heat dissipation while maintaining structural integrity. The second heat spreader may be thermally coupled to the first semiconductor chip to facilitate heat transfer. The package may also include additional components such as a first heat spreader, a second semiconductor chip, and an interposer, which collectively enhance electrical and thermal performance. The first heat spreader may be attached to the lower surface of the first semiconductor chip, while the second semiconductor chip may be mounted on the interposer. The interposer electrically connects the first and second semiconductor chips, enabling signal transmission between them. The second heat spreader's design ensures optimal heat dissipation without excessive material usage, improving overall package efficiency. This structure is particularly useful in high-performance semiconductor applications where thermal management is critical.
9. The semiconductor package of claim 8 , wherein the area of the second heat spreader at the boundary between the first heat spreader and the second heat spreader is a same area as the area of the second heat spreader which covers the upper surface of the first semiconductor chip.
A semiconductor package includes a first heat spreader and a second heat spreader, where the second heat spreader is positioned to cover an upper surface of a first semiconductor chip and extends to a boundary with the first heat spreader. The second heat spreader has a consistent cross-sectional area at the boundary between the first and second heat spreaders, matching the area where it covers the first semiconductor chip. This design ensures uniform heat dissipation and structural integrity by maintaining a constant material distribution across the interface. The first heat spreader may be thermally coupled to a second semiconductor chip, while the second heat spreader provides additional cooling for the first semiconductor chip. The package may also include an interposer or substrate for electrical connections. The consistent area at the boundary prevents thermal stress concentrations and improves reliability. This configuration is particularly useful in high-performance semiconductor packages where efficient heat management is critical.
10. The semiconductor package of claim 1 , further comprising: a first heat transfer component disposed between the second semiconductor chip and the first heat spreader; and a second heat transfer component disposed between the first semiconductor chip and the second heat spreader.
This invention relates to semiconductor packaging, specifically addressing thermal management in multi-chip packages. The problem solved is inefficient heat dissipation in semiconductor packages containing multiple chips, which can lead to overheating and reduced performance. The invention improves heat transfer by incorporating additional heat transfer components between the chips and heat spreaders. The semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked or arranged in proximity. A first heat spreader is thermally coupled to the second semiconductor chip, and a second heat spreader is thermally coupled to the first semiconductor chip. To enhance heat dissipation, a first heat transfer component is disposed between the second semiconductor chip and the first heat spreader, and a second heat transfer component is disposed between the first semiconductor chip and the second heat spreader. These heat transfer components facilitate more efficient heat conduction from the chips to the respective heat spreaders, improving overall thermal performance. The heat transfer components may include materials with high thermal conductivity, such as thermal interface materials (TIMs), thermal grease, or metallic interfaces. The heat spreaders are typically made of materials like copper or aluminum, which distribute heat away from the chips. This configuration ensures that both chips receive adequate cooling, preventing thermal bottlenecks and maintaining optimal operating conditions. The invention is particularly useful in high-performance computing, power electronics, and other applications where thermal management is critical.
11. The semiconductor package of claim 1 , wherein the substrate is an interposer substrate.
The semiconductor package includes a substrate, a semiconductor die, and a thermal interface material. The substrate provides mechanical support and electrical connections for the semiconductor die, which is mounted on the substrate. The thermal interface material is positioned between the semiconductor die and a heat spreader, facilitating heat dissipation from the die to the heat spreader. The substrate is an interposer substrate, which serves as an intermediate layer between the semiconductor die and a larger circuit board or package substrate. Interposer substrates are used to redistribute electrical connections, improve signal integrity, and enable advanced packaging techniques such as fan-out wafer-level packaging or 2.5D/3D integration. The interposer may include through-silicon vias (TSVs) or other conductive pathways to route signals between the semiconductor die and the underlying substrate or circuit board. This configuration enhances thermal management and electrical performance while allowing for higher-density interconnects in compact semiconductor packages. The thermal interface material ensures efficient heat transfer from the die to the heat spreader, preventing overheating and maintaining reliable operation.
12. The semiconductor package of claim 1 , further comprising: a plurality of external terminals disposed on the second surface of the substrate; a plurality of connection terminals disposed between the first semiconductor chip and the substrate, and between the second semiconductor chip and the substrate; and a bridge disposed on the first surface of the substrate, wherein a first group of the plurality of connection terminals is disposed between the second semiconductor chip and the bridge, and a second group of the plurality of connection terminals is disposed between the first semiconductor chip and the bridge, and a remainder of the plurality of connection terminals other than the first group and the second group are connected to a portion of the plurality of external terminals.
This invention relates to semiconductor packaging, specifically addressing the challenge of integrating multiple semiconductor chips into a compact, high-performance package with efficient electrical connections. The package includes a substrate with a first surface and a second surface, where the first surface supports at least two semiconductor chips. A bridge is positioned on the first surface of the substrate, facilitating electrical communication between the chips. Connection terminals are arranged between the chips and the substrate, with a first subset connecting the second semiconductor chip to the bridge and a second subset connecting the first semiconductor chip to the bridge. The remaining connection terminals link the chips to external terminals on the second surface of the substrate, enabling external connectivity. This design optimizes signal routing and reduces package size while maintaining high-speed data transfer between the chips and external devices. The bridge and connection terminals ensure reliable inter-chip communication, while the external terminals provide a standardized interface for integration into larger systems. The invention is particularly useful in applications requiring high-density, multi-chip modules such as advanced computing, memory systems, and high-performance electronics.
13. A semiconductor package comprising: a substrate including a first surface and a second surface facing each other; a first semiconductor chip disposed on the first surface of the substrate; a second semiconductor chip and a third semiconductor chip disposed on the first surface of the substrate with the first semiconductor chip interposed therebetween; a first heat spreader formed on the first semiconductor chip, the second semiconductor chip and the third semiconductor chip; and a second heat spreader which protrudes from the first heat spreader and covers an upper surface of the first semiconductor chip, wherein the first semiconductor chip includes a first side wall and a second side wall extending in a first direction, the first side wall and the second side wall being on opposite sides of the first semiconductor chip in a second direction intersecting the first direction, the second semiconductor chip includes a third side wall facing the first side wall of the first semiconductor chip, the third semiconductor chip includes a fourth side wall facing the second side wall of the first semiconductor chip, and at a boundary between the first heat spreader and the second heat spreader, a width of the second heat spreader in the second direction is smaller than a distance between the third side wall of the second semiconductor chip and the fourth side wall of the third semiconductor chip.
A semiconductor package is designed to improve heat dissipation in multi-chip configurations. The package includes a substrate with opposing first and second surfaces. A first semiconductor chip is mounted on the first surface, flanked by second and third semiconductor chips on either side. A first heat spreader is formed over all three chips, while a second heat spreader protrudes from the first heat spreader and specifically covers the upper surface of the first semiconductor chip. The first semiconductor chip has side walls extending in a first direction, with the second and third chips positioned such that their respective side walls face the opposing side walls of the first chip. At the boundary between the first and second heat spreaders, the width of the second heat spreader in a second direction (perpendicular to the first direction) is narrower than the distance between the side walls of the second and third chips. This configuration ensures targeted heat dissipation from the central first chip while maintaining structural integrity and thermal management in a compact multi-chip package. The design optimizes cooling efficiency without interfering with adjacent chips, addressing thermal challenges in high-density semiconductor packaging.
14. The semiconductor package of claim 13 , wherein the width of the second heat spreader in the second direction at the boundary between the first heat spreader and the second heat spreader is smaller than or equal to a width of the second heat spreader in the second direction at an interface between the first semiconductor chip and the second heat spreader.
The semiconductor package relates to thermal management in integrated circuit packaging, specifically addressing heat dissipation challenges in multi-chip modules. The invention involves a structure where a first semiconductor chip is mounted on a first heat spreader, and a second semiconductor chip is mounted on a second heat spreader. The second heat spreader is positioned adjacent to the first heat spreader, forming a boundary between them. The second heat spreader has a width in a second direction (likely perpendicular to the boundary) that is smaller or equal at the boundary compared to its width at the interface with the second semiconductor chip. This design ensures efficient heat transfer from the second semiconductor chip to the second heat spreader while maintaining structural integrity and minimizing thermal resistance. The varying width of the second heat spreader optimizes heat spreading and reduces thermal gradients, improving overall thermal performance in high-power semiconductor packages. The package may also include additional features such as thermal interface materials or conductive pathways to further enhance heat dissipation. This configuration is particularly useful in applications requiring compact, high-performance semiconductor packages with effective thermal management.
15. The semiconductor package of claim 13 , wherein the width of the second heat spreader in the second direction at the boundary between the first heat spreader and the second heat spreader is greater than a width of the second heat spreader in the second direction at an interface between the first semiconductor chip and the second heat spreader.
The invention relates to semiconductor packaging, specifically addressing thermal management in multi-chip packages. The problem being solved is inefficient heat dissipation in semiconductor packages containing multiple chips, which can lead to overheating and reduced performance. The solution involves a semiconductor package with a first heat spreader and a second heat spreader, where the second heat spreader has a varying width in a second direction. The width of the second heat spreader at the boundary between the first and second heat spreaders is greater than its width at the interface with a first semiconductor chip. This design allows for improved heat dissipation by optimizing the thermal path between the chips and the heat spreaders. The first heat spreader is thermally coupled to a second semiconductor chip, while the second heat spreader is thermally coupled to the first semiconductor chip. The varying width of the second heat spreader ensures efficient heat transfer from the chip to the heat spreader and then to the first heat spreader, enhancing overall thermal performance. The package structure is designed to minimize thermal resistance and improve heat spreading efficiency, particularly in high-power applications where multiple chips generate significant heat.
16. The semiconductor package of claim 13 , wherein a width between the first side wall of the first semiconductor chip and the third side wall of the second semiconductor chip in the second direction, and a width between the second side wall of the first semiconductor chip and the fourth side wall of the third semiconductor chip in the second direction is 150 um or less.
A semiconductor package includes multiple semiconductor chips arranged in a stacked configuration. The package addresses challenges in miniaturization and efficient heat dissipation by optimizing the spacing between adjacent semiconductor chips. The first semiconductor chip has a first side wall and a second side wall, while the second semiconductor chip has a third side wall, and the third semiconductor chip has a fourth side wall. The spacing between the first side wall of the first semiconductor chip and the third side wall of the second semiconductor chip, as well as the spacing between the second side wall of the first semiconductor chip and the fourth side wall of the third semiconductor chip, is minimized to 150 micrometers or less in a specified direction. This tight spacing reduces the overall footprint of the package while maintaining thermal and electrical performance. The arrangement ensures efficient heat transfer and signal integrity, making the package suitable for high-density applications. The design also facilitates improved manufacturing yield by reducing alignment tolerances and minimizing parasitic effects. The semiconductor package is particularly useful in advanced computing, memory, and power electronics where compactness and performance are critical.
17. The semiconductor package of claim 13 , further comprising: a third heat spreader that extends from the first heat spreader in a direction toward the substrate; and a fourth heat spreader that extends from the first heat spreader in the direction toward the substrate, wherein the first heat spreader, the third heat spreader and the fourth heat spreader surround the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip and an outer surface of the substrate.
This invention relates to semiconductor packaging, specifically addressing thermal management in multi-chip packages. The design includes a first heat spreader thermally coupled to multiple semiconductor chips and a substrate, with additional heat spreaders extending from the first heat spreader toward the substrate. A third and fourth heat spreader extend from the first heat spreader, surrounding the semiconductor chips and the substrate's outer surface. The configuration enhances heat dissipation by increasing the surface area for heat transfer and improving thermal conductivity paths. The heat spreaders are arranged to form a protective and thermally efficient enclosure around the chips and substrate, reducing localized hot spots and improving overall package performance. This design is particularly useful in high-power applications where efficient heat removal is critical to maintaining device reliability and performance. The interconnected heat spreaders create a continuous thermal conduction path, ensuring uniform heat distribution and minimizing thermal resistance between the chips and the external environment. The structure also provides mechanical support and protection for the semiconductor components while optimizing thermal management.
18. The semiconductor package of claim 13 , wherein the first semiconductor chip includes a logic chip, and the second semiconductor chip and the third semiconductor chip each includes a high bandwidth memory in which a plurality of chips are stacked.
This invention relates to semiconductor packaging, specifically addressing the challenge of integrating high-performance logic and memory components in a compact, efficient package. The semiconductor package includes a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip, all mounted on a substrate. The first semiconductor chip is a logic chip designed for processing tasks, while the second and third semiconductor chips are high bandwidth memory (HBM) modules. Each HBM module consists of multiple memory chips stacked vertically to maximize memory density and bandwidth while minimizing footprint. The logic chip is electrically connected to the HBM modules via interconnects, enabling high-speed data transfer between the processor and memory. The package may also include a heat spreader or thermal interface material to manage heat dissipation from the stacked memory chips. This design improves performance by reducing latency and increasing bandwidth between the logic and memory components, making it suitable for applications requiring high computational power, such as data centers, AI processing, and high-performance computing.
19. The semiconductor package of claim 13 , wherein the second heat spreader is spaced apart from the third side wall of the second semiconductor chip and the fourth side wall of the third semiconductor chip.
The invention relates to semiconductor packaging, specifically addressing thermal management and structural integrity in multi-chip packages. The problem solved involves efficiently dissipating heat from multiple semiconductor chips while maintaining mechanical stability and electrical isolation. The package includes a first semiconductor chip with a first heat spreader attached to its top surface, and a second semiconductor chip stacked adjacent to the first chip. A second heat spreader is positioned above the second semiconductor chip but is spaced apart from the second chip's side walls and the side walls of a third semiconductor chip, which is also part of the package. This spacing prevents direct contact between the heat spreader and the chips, reducing thermal stress and potential short circuits. The heat spreader is thermally coupled to the chips to facilitate heat dissipation while allowing for thermal expansion without mechanical interference. The design ensures reliable operation by minimizing thermal resistance and mechanical strain in high-performance semiconductor packages.
20. A semiconductor package comprising: a substrate; a heat spreader on the substrate, a packaging space being defined between the substrate and the heat spreader; a first connection terminal disposed on the substrate inside the packaging space; an interposer substrate disposed on the first connection terminal inside the packaging space; a second connection terminal disposed on the interposer substrate; a first semiconductor chip disposed on the second connection terminal; a second semiconductor chip and a third semiconductor chip disposed on the second connection terminal with the first semiconductor chip interposed therebetween; a first heat transfer component disposed on the first semiconductor chip; a second heat transfer component disposed on the second semiconductor chip; and a third heat transfer component disposed on the third semiconductor chip, wherein the first semiconductor chip includes a first side wall and a second side wall extending in a first direction and on opposite sides of the first semiconductor chip in a second direction intersecting the first direction, the second semiconductor chip includes a third side wall facing the first side wall of the first semiconductor chip, the third semiconductor chip includes a fourth side wall facing the second side wall of the first semiconductor chip, the first side wall and the third side wall are spaced apart from each other, the second side wall and the fourth side wall are spaced apart from each other, the heat spreader surrounding the packaging space, and including a first heat spreader formed on the first heat transfer component, the second heat transfer component, and the third heat transfer component, a second heat spreader protruding from the first heat spreader and covering an upper part of the first heat transfer component, and a third heat spreader and a fourth heat spreader each extending from the first heat spreader to a surface of the substrate, a width of the second heat spreader in the second direction at a boundary between the first heat spreader and the second heat spreader is smaller than a distance between the third side wall of the second semiconductor chip and the fourth side wall of the third semiconductor chip, and the third heat spreader and the fourth heat spreader are each spaced apart from the first to third semiconductor chips and an outer wall of the interposer substrate.
This invention relates to semiconductor packaging, specifically addressing thermal management and space efficiency in multi-chip modules. The package includes a substrate with a heat spreader defining an enclosed packaging space. Inside this space, a first connection terminal is mounted on the substrate, supporting an interposer substrate. The interposer substrate has a second connection terminal, which supports three semiconductor chips: a central first semiconductor chip flanked by second and third semiconductor chips. Each chip has a dedicated heat transfer component (e.g., heat sinks or thermal interface materials) to dissipate heat. The heat spreader is structured in multiple parts: a base layer covering all heat transfer components, a protruding section over the central chip's heat transfer component, and two side extensions reaching the substrate. The side extensions are spaced from the chips and interposer edges to avoid interference. The design ensures efficient heat dissipation while maintaining compact packaging, with the protruding heat spreader section narrower than the gap between the outer chips to prevent thermal interference. This configuration optimizes thermal performance in high-density semiconductor packages.
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September 28, 2020
April 12, 2022
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