The present disclosure provides for a semiconductor device package and a method for manufacturing the same. The semiconductor device package includes a substrate, a conductive element and conductive layers. The substrate has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The conductive element is disposed on the first surface of the substrate. The conductive layers have a first portion on the conductive element and a second portion on the lateral surface of the substrate. A number of layers of the first portion of the conductive layers is different from a number of layers of the second portion of the conductive layers.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A semiconductor device package, comprising a substrate having a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface; a conductive element disposed on the first surface of the substrate; a first package body disposed over the first surface of the substrate, an anti-oxidation protective layer in contact with a top surface of the first package body and the conductive element, wherein the anti-oxidation protection layer has a plurality of openings; and a first conductive layer in contact with a lateral surface of the first package body, wherein the first conductive layer comprises a plurality of protrusions filled in the plurality of openings of the anti-oxidation protection layer.
A semiconductor device package addresses the challenge of protecting conductive elements from oxidation while maintaining electrical connectivity. The package includes a substrate with opposing first and second surfaces and a lateral surface connecting them. A conductive element is positioned on the first surface of the substrate. A first package body is formed over the first surface, covering the conductive element and substrate. An anti-oxidation protective layer is applied over the top surface of the first package body and the conductive element, featuring multiple openings to allow selective exposure of underlying conductive regions. A first conductive layer is deposited on the lateral surface of the package body, extending inward through the openings in the protective layer. This conductive layer includes protrusions that fill the openings, ensuring electrical contact with the conductive element while shielding it from oxidation. The design enables reliable electrical connections while preventing degradation of exposed conductive surfaces. The protective layer and conductive layer combination ensures long-term performance in semiconductor applications.
2. The semiconductor device package of claim 1 , wherein the first conductive layer is a seed layer and disposed on the anti-oxidation protective layer and on the lateral surface of the substrate, the anti-oxidation protective layer and the first conductive layer define an interface, and the first conductive layer is spaced apart from the conductive element by the anti-oxidation protective layer.
This invention relates to semiconductor device packaging, specifically addressing issues related to oxidation and electrical connectivity in packaged semiconductor devices. The device includes a substrate with a conductive element embedded within it, an anti-oxidation protective layer covering the substrate, and a first conductive layer serving as a seed layer. The seed layer is deposited on the anti-oxidation protective layer and extends onto the lateral surface of the substrate. The interface between the anti-oxidation protective layer and the seed layer ensures electrical insulation while maintaining structural integrity. The seed layer is spaced apart from the conductive element by the anti-oxidation protective layer, preventing direct contact and potential short circuits. This configuration enhances reliability by protecting the substrate from oxidation while enabling precise conductive layer deposition for subsequent processing steps. The design is particularly useful in advanced packaging where oxidation resistance and controlled conductivity are critical. The protective layer and seed layer combination ensures long-term performance without compromising electrical functionality.
3. The semiconductor device package of claim 1 , wherein the first conductive layer is in contact with a top surface and a lateral surface of the anti-oxidation protective layer.
A semiconductor device package includes a first conductive layer that is in direct contact with both a top surface and a lateral surface of an anti-oxidation protective layer. The anti-oxidation protective layer is designed to prevent oxidation of underlying conductive structures, ensuring reliable electrical performance. The first conductive layer, which may be part of a redistribution layer (RDL) or other interconnect structure, extends over the protective layer to form electrical connections. This configuration enhances adhesion and reduces the risk of delamination while maintaining electrical conductivity. The protective layer is typically composed of a material such as silicon nitride, silicon oxide, or a polymer, chosen for its barrier properties against moisture and oxygen. The first conductive layer may be formed from copper, aluminum, or other conductive metals, deposited using processes like electroplating or sputtering. The package may further include additional conductive layers, insulating layers, and semiconductor components, all integrated to form a compact, high-performance electronic device. This design is particularly useful in advanced packaging applications where oxidation resistance and structural integrity are critical.
4. The semiconductor device package of claim 1 , further comprising: a first electronic component disposed on the first surface of the substrate; and a second electronic component disposed on the first surface of the substrate and separated from the first electronic component by the conductive element.
A semiconductor device package includes a substrate with a first surface and a second surface opposite the first surface. The substrate has a conductive element embedded within it, extending from the first surface to the second surface. The conductive element is electrically isolated from other conductive features of the substrate. The package also includes a first electronic component mounted on the first surface of the substrate and a second electronic component also mounted on the first surface. The second electronic component is positioned such that the conductive element physically separates it from the first electronic component. This separation ensures electrical isolation between the two components while maintaining their proximity on the same substrate surface. The conductive element may serve as a ground plane, power distribution path, or signal routing feature, depending on the design requirements. The package structure allows for compact integration of multiple components while managing electrical interference and signal integrity. The substrate may be a printed circuit board, interposer, or other semiconductor packaging material, and the electronic components can include integrated circuits, passive devices, or other semiconductor elements. The design is particularly useful in high-density applications where space constraints and electrical isolation are critical.
5. The semiconductor device package of claim 4 , wherein the first package body covers the first electronic component, the second electronic component and a portion of the conductive element, and a top surface of the conductive element is exposed from the first package body to contact the anti-oxidation protective layer.
This invention relates to semiconductor device packaging, specifically addressing the challenge of protecting conductive elements from oxidation while maintaining electrical connectivity. The device includes a first electronic component and a second electronic component mounted on a substrate, with a conductive element electrically connecting the two components. A first package body encapsulates the electronic components and partially covers the conductive element, leaving a top surface of the conductive element exposed. An anti-oxidation protective layer is applied to the exposed portion of the conductive element to prevent oxidation while allowing electrical contact. The protective layer may be a metal or conductive polymer that resists oxidation and maintains conductivity. The packaging structure ensures reliable electrical connections while protecting sensitive components from environmental degradation. This design is particularly useful in high-reliability applications where oxidation resistance is critical, such as in automotive or industrial electronics. The partial encapsulation of the conductive element balances protection with accessibility for further assembly or testing.
6. The semiconductor device package of claim 5 , wherein a lateral surface of the anti-oxidation protective layer is substantially coplanar with the lateral surface of the first package body.
A semiconductor device package includes a first package body with an anti-oxidation protective layer applied to a surface of the first package body. The anti-oxidation protective layer is designed to prevent oxidation of underlying materials, such as metal interconnects or conductive traces, within the package. The lateral surface of the anti-oxidation protective layer is aligned to be substantially coplanar with the lateral surface of the first package body, ensuring a uniform and smooth outer profile. This alignment helps maintain structural integrity and facilitates subsequent packaging processes, such as stacking or encapsulation. The protective layer may be formed using materials like silicon nitride, silicon oxide, or other dielectric compounds, applied through deposition techniques such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The coplanar alignment minimizes stress concentrations and reduces the risk of delamination or cracking during thermal cycling or mechanical handling. This design is particularly useful in advanced semiconductor packaging, where multiple layers or components are integrated into a compact form factor while maintaining reliability and performance. The protective layer also acts as a barrier against moisture and contaminants, further enhancing the device's longevity.
7. The semiconductor device package of claim 4 , further comprising: a third electronic component disposed on the second surface of the substrate; and a second package body disposed on the second surface of the substrate and at least partially covering the third electronic component.
A semiconductor device package includes a substrate with a first surface and a second surface. The package contains a first electronic component mounted on the first surface and a first package body covering the first electronic component. The substrate has a conductive structure, such as a through-hole or via, electrically connecting the first and second surfaces. The package also includes a second electronic component mounted on the second surface and a second package body covering the second electronic component. Additionally, a third electronic component is mounted on the second surface, and a third package body is disposed on the second surface, at least partially covering the third electronic component. The conductive structure enables electrical connections between components on both surfaces, while the package bodies provide protection and structural support. This configuration allows for a compact, multi-component semiconductor package with enhanced functionality and integration. The design is particularly useful in applications requiring high-density packaging, such as advanced computing, telecommunications, and power electronics.
8. The semiconductor device package of claim 4 , wherein the conductive element is adjacent to at least two lateral surfaces of the first electronic component and the second electronic component.
A semiconductor device package includes a first electronic component and a second electronic component, each having lateral surfaces. The package also includes a conductive element positioned adjacent to at least two lateral surfaces of both the first and second electronic components. This conductive element may serve as an electrical connection, thermal dissipation path, or structural support between the components. The arrangement ensures efficient signal transmission, heat dissipation, or mechanical stability within the package. The conductive element may be a metal trace, a conductive adhesive, or a solder connection, depending on the application. The package is designed to improve performance, reliability, or integration density in electronic devices by optimizing the interaction between the conductive element and the lateral surfaces of the components. This configuration is particularly useful in high-performance or compact semiconductor packages where efficient electrical and thermal management is critical.
9. The semiconductor device package of claim 1 , wherein the plurality of protrusions of the first conductive layer extend into a plurality of recesses of the first package body.
A semiconductor device package includes a first conductive layer with a plurality of protrusions and a first package body with a plurality of recesses. The protrusions of the first conductive layer extend into the recesses of the first package body, creating an interlocking structure that enhances mechanical stability and electrical connectivity. This design improves the reliability of the package by preventing delamination and ensuring robust electrical connections between the conductive layer and the package body. The protrusions and recesses may be formed through etching, molding, or other fabrication techniques to achieve precise alignment and engagement. The package may also include additional conductive layers, insulating layers, and semiconductor components, depending on the specific application. The interlocking mechanism is particularly useful in high-performance electronic devices where mechanical stress and thermal cycling can degrade performance over time. By integrating the protrusions into the recesses, the package maintains structural integrity and electrical performance under demanding operating conditions. This approach is applicable to various semiconductor packaging technologies, including fan-out wafer-level packaging, flip-chip packaging, and system-in-package designs. The interlocking structure can be customized based on the material properties and dimensions of the conductive layer and package body to optimize performance and manufacturing efficiency.
10. A semiconductor device package, comprising a substrate having a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface; a conductive element disposed on the first surface of the substrate; conductive layers disposed on the conductive element and the lateral surface of the substrate, the conductive layers comprising an anti-oxidation protective layer disposed on the conductive element and spaced apart from the lateral surface of the substrate, wherein the anti-oxidation protection layer has a plurality of openings; and a first package body disposed over the first surface of the substrate, wherein the conductive layers further comprise a first conductive layer in contact with a lateral surface of the first package body, and the anti-oxidation protective layer is in contact with a top surface of the first package body and the conductive element, wherein a resistance between the second surface of the substrate and the conductive layers is in a range from 0.0080 hm to 0.080 hm, and wherein the first conductive layer comprises a plurality of protrusions filled in the plurality of openings of the anti-oxidation protection layer.
This invention relates to a semiconductor device package designed to improve electrical conductivity and oxidation resistance. The package includes a substrate with opposing first and second surfaces and a lateral surface connecting them. A conductive element is placed on the first surface, and conductive layers are applied over both the conductive element and the substrate's lateral surface. A key feature is an anti-oxidation protective layer covering the conductive element but spaced from the lateral surface, with multiple openings to allow electrical contact. A first package body is formed over the first surface, and the conductive layers include a first conductive layer that contacts the package body's lateral surface. The anti-oxidation layer also contacts the package body's top surface and the conductive element. The design ensures a resistance between the substrate's second surface and the conductive layers ranges from 0.0080 hm to 0.080 hm. The first conductive layer has protrusions that fill the openings in the anti-oxidation layer, enhancing electrical connectivity while maintaining protection against oxidation. This structure improves reliability and performance in semiconductor packaging by balancing conductivity and corrosion resistance.
11. The semiconductor device package of claim 10 , wherein the first conductive layer is disposed on the anti-oxidation protective layer and on the lateral surface of the substrate, and the anti-oxidation protective layer and the first conductive layer define an interface.
The semiconductor device package relates to an improved structure for protecting semiconductor devices from oxidation while maintaining electrical conductivity. The problem addressed is the degradation of semiconductor performance due to oxidation of exposed conductive surfaces, which can lead to increased resistance, reduced reliability, and failure over time. Traditional solutions often involve bulky or complex protective layers that may interfere with device functionality or manufacturing processes. The invention provides a semiconductor device package with an anti-oxidation protective layer applied to a substrate, particularly covering exposed surfaces prone to oxidation. A first conductive layer is then deposited on the anti-oxidation protective layer and extends onto the lateral surface of the substrate. The interface between the anti-oxidation protective layer and the first conductive layer ensures a stable, oxidation-resistant connection while maintaining electrical conductivity. This design prevents oxidation of the underlying conductive structures without compromising the device's electrical performance or increasing its footprint. The protective layer may consist of materials such as silicon nitride, silicon oxide, or other dielectric compounds, while the conductive layer may be formed from metals like copper, aluminum, or conductive polymers. The invention is particularly useful in high-reliability applications where long-term stability is critical, such as in automotive electronics, aerospace systems, or medical devices. The structure allows for efficient manufacturing while ensuring robust protection against environmental degradation.
12. The semiconductor device package of claim 11 , wherein the first package body covers a portion of the conductive element, and a top surface of the conductive element is exposed from the first package body to contact with the anti-oxidation protective layer.
The semiconductor device package relates to integrated circuit packaging, specifically addressing the challenge of protecting conductive elements from oxidation while maintaining electrical connectivity. The package includes a first package body that encapsulates a portion of a conductive element, such as a metal pad or interconnect, while leaving a top surface of the conductive element exposed. This exposed surface is directly contacted by an anti-oxidation protective layer, which prevents oxidation of the conductive element while allowing electrical connections to be made to the exposed portion. The protective layer may be a conductive or non-conductive material, such as a metal, polymer, or composite, designed to shield the underlying conductive element from environmental degradation. The package may also include additional components, such as a second package body or a substrate, to support the conductive element and provide structural integrity. The design ensures reliable electrical performance by maintaining the integrity of the conductive element while protecting it from oxidation, which is critical for long-term reliability in semiconductor devices.
13. The semiconductor device package of claim 12 , wherein the first conductive layer comprises a portion penetrating through the anti-oxidation protective layer and extending within a recess of the first package body.
The semiconductor device package relates to advanced packaging technologies for integrated circuits, addressing challenges in electrical connectivity and oxidation protection. The invention involves a semiconductor device package with a first conductive layer that includes a portion penetrating through an anti-oxidation protective layer and extending into a recess within a first package body. This design enhances electrical connections while maintaining protection against oxidation. The first package body provides structural support and encapsulation for the semiconductor components, while the anti-oxidation protective layer prevents degradation of conductive elements. The first conductive layer, which may include metal traces or vias, ensures reliable signal transmission or power distribution. The recess in the first package body accommodates the conductive layer, optimizing space utilization and mechanical stability. This configuration is particularly useful in high-density packaging applications where both electrical performance and long-term reliability are critical. The invention improves upon existing solutions by integrating oxidation protection with efficient conductive pathways, reducing the risk of failure due to environmental exposure.
14. The semiconductor device package of claim 10 , wherein the resistance between the second surface of the substrate and the conductive layers is equal to or smaller than 0.068 Ohm.
This invention relates to semiconductor device packaging, specifically addressing the challenge of minimizing electrical resistance in packaged semiconductor devices to improve performance and efficiency. The semiconductor device package includes a substrate with a first surface and a second surface, where the second surface is electrically connected to conductive layers within the package. The key innovation is the precise control of electrical resistance between the second surface of the substrate and the conductive layers, ensuring it is equal to or less than 0.068 ohms. This low resistance is achieved through optimized material selection, structural design, and manufacturing processes, which enhance current flow and reduce power loss. The conductive layers may include metal traces, vias, or other conductive elements that facilitate electrical connections within the package. The substrate may be a printed circuit board, ceramic, or other insulating material with embedded conductive pathways. The low-resistance connection is critical for high-power applications, such as power electronics, where minimizing resistive losses is essential for efficiency and thermal management. The invention ensures reliable electrical performance while maintaining compact packaging dimensions.
15. The semiconductor device package of claim 14 , wherein the resistance between the second surface of the substrate and the conductive layers is equal to or greater than about 0.021 Ohm.
The semiconductor device package relates to an electronic packaging technology designed to improve electrical performance and reliability in integrated circuits. The package includes a substrate with a first surface and a second surface, where the second surface is configured to mount a semiconductor die. The substrate has conductive layers embedded within it, and these layers are electrically connected to the semiconductor die. The package also includes a heat spreader attached to the second surface of the substrate, which helps dissipate heat generated by the semiconductor die during operation. The heat spreader is electrically insulated from the conductive layers to prevent short circuits or interference. A key feature of this package is the controlled electrical resistance between the second surface of the substrate and the conductive layers. This resistance is set to be equal to or greater than approximately 0.021 ohms, ensuring proper electrical isolation while maintaining efficient signal transmission. The resistance value is carefully selected to balance thermal conductivity and electrical insulation, optimizing both performance and reliability. This design is particularly useful in high-power or high-frequency applications where thermal management and signal integrity are critical. The package structure ensures that heat is effectively dissipated while preventing unwanted electrical interactions between the conductive layers and the heat spreader.
16. The semiconductor device package of claim 10 , further comprising: a first electronic component disposed on the first surface of the substrate; a second electronic component disposed on the first surface of the substrate and separated from the first electronic component by the conductive element; a third electronic component disposed on the second surface of the substrate; and a second package body disposed on the second surface of the substrate and at least partially covering the third electronic component.
A semiconductor device package includes a substrate with a first surface and a second surface. The substrate has a conductive element, such as a conductive via or trace, embedded within it. A first electronic component is mounted on the first surface of the substrate, and a second electronic component is also mounted on the first surface but is electrically isolated from the first electronic component by the conductive element. A third electronic component is mounted on the second surface of the substrate. A second package body is disposed on the second surface, encapsulating and protecting the third electronic component. The conductive element ensures electrical isolation between the first and second electronic components on the first surface while allowing independent electrical connections. The package structure enables high-density integration of multiple components on both surfaces of the substrate, improving space efficiency and functionality in semiconductor devices. The second package body provides mechanical and environmental protection for the third electronic component. This design is useful in applications requiring compact, multi-component semiconductor packages with reliable electrical isolation and protection.
17. A method of manufacturing a semiconductor device package, comprising: (a) forming a conductive element on a first surface of a substrate; (b) forming an anti-oxidation protective layer in contact with a top surface of the conductive element, wherein the anti-oxidation protection layer has a plurality of openings; (c) forming a first electronic component on a second surface of the substrate opposite to the first surface of the substrate; and (d) forming a conductive layer on the anti-oxidation protective layer, and wherein the conductive layer comprises a plurality of protrusions filled in the plurality of openings of the anti-oxidation protection layer.
The semiconductor device packaging industry faces challenges in protecting conductive elements from oxidation while ensuring reliable electrical connections. This invention addresses these issues by providing a method to manufacture a semiconductor device package with enhanced oxidation resistance and improved conductivity. The method involves forming a conductive element on a first surface of a substrate. An anti-oxidation protective layer is then deposited over the conductive element, featuring multiple openings to allow selective exposure of the conductive element. A first electronic component is mounted on the opposite surface of the substrate. Finally, a conductive layer is applied over the anti-oxidation protective layer, with protrusions extending through the openings to directly contact the conductive element. This design ensures the conductive element remains protected from oxidation while maintaining strong electrical connectivity. The anti-oxidation protective layer prevents oxidation of the underlying conductive element, while the conductive layer's protrusions ensure reliable electrical pathways. This approach improves the durability and performance of semiconductor packages, particularly in applications where oxidation resistance is critical. The method is applicable to various semiconductor packaging processes, enhancing both functionality and longevity.
18. The method of claim 17 , further comprising: prior to operation (b), forming a first package body to cover a portion of the conductive element and to expose the top surface of the conductive element.
The invention relates to semiconductor packaging, specifically addressing the challenge of protecting conductive elements while maintaining accessibility for subsequent processing steps. The method involves forming a package body around a conductive element, such as a metal pad or interconnect, to provide structural support and environmental protection. The package body is applied in a way that covers only a portion of the conductive element, leaving its top surface exposed. This ensures the conductive element remains accessible for further electrical connections, bonding, or testing. The exposed top surface allows for direct contact with other components or conductive layers without requiring additional exposure steps. The package body may be formed using materials like mold compounds, underfill materials, or encapsulation resins, which are applied through techniques such as molding, dispensing, or spin-coating. This approach improves reliability by protecting the conductive element from mechanical damage and contamination while enabling efficient integration into larger semiconductor devices or modules. The method is particularly useful in advanced packaging applications where multiple layers of interconnects and components are stacked or integrated.
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May 14, 2020
April 12, 2022
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