To suppress deterioration of image quality. A solid-state imaging device (1) according to an embodiment includes a plurality of unit pixels (100) each of which includes a photoelectric conversion element (PD) configured to generate an electric charge corresponding to an incident light quantity, a transfer transistor (102) configured to transfer the electric charge generated in the photoelectric conversion element, a charge accumulation unit (FD) configured to accumulate the electric charge transferred by the transfer transistor, an amplification transistor (1051, 1052) including at least two fingers that are connected to the charge accumulation unit in parallel, and a selection transistor (106) that is disposed corresponding to each of the fingers of the amplification transistor on a one-to-one basis.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A solid-state imaging device comprising a plurality of unit pixels, each of the unit pixels comprising: a photoelectric conversion element configured to generate an electric charge corresponding to an incident light quantity; a transfer transistor configured to transfer the electric charge generated in the photoelectric conversion element; a charge accumulation unit configured to accumulate the electric charge transferred by the transfer transistor; an amplification transistor including at least two fingers that are connected to the charge accumulation unit in parallel; and a selection transistor that is disposed corresponding to each of the fingers of the amplification transistor on a one-to-one basis.
A solid-state imaging device includes an array of unit pixels, each designed to capture and process light. Each unit pixel contains a photoelectric conversion element that generates an electric charge proportional to the incident light intensity. A transfer transistor moves this charge from the photoelectric conversion element to a charge accumulation unit, where it is stored. The stored charge is then amplified by an amplification transistor, which features at least two parallel-connected fingers to enhance signal strength and reduce noise. Each finger of the amplification transistor is paired with a dedicated selection transistor, ensuring independent control and readout of the amplified signal from each finger. This configuration improves signal integrity and reduces interference between adjacent pixels, leading to higher image quality in applications such as digital cameras and sensors. The parallel amplification structure and one-to-one selection transistor arrangement optimize performance by minimizing signal loss and cross-talk while maintaining compact pixel design.
2. The solid-state imaging device according to claim 1 , wherein the amplification transistor includes a first amplification transistor corresponding to one of the at least two fingers, and a second amplification transistor corresponding to another of the fingers, and the selection transistor includes a first selection transistor that is connected to the first amplification transistor in series, and a second selection transistor that is connected to the second amplification transistor in series.
A solid-state imaging device includes an array of pixels, each pixel containing a photodiode for converting light into an electrical signal, a transfer transistor for transferring the signal, and an amplification transistor for amplifying the signal. The amplification transistor is divided into multiple fingers, each finger corresponding to a separate amplification transistor. For example, a first amplification transistor corresponds to one finger, and a second amplification transistor corresponds to another finger. Each amplification transistor is connected in series to a selection transistor. Specifically, a first selection transistor is connected to the first amplification transistor, and a second selection transistor is connected to the second amplification transistor. This configuration allows for independent control of each amplification transistor and selection transistor pair, improving signal processing flexibility and reducing noise. The device may also include a reset transistor for resetting the pixel and a floating diffusion node for temporarily storing the amplified signal. The structure enhances performance by optimizing signal amplification and selection in a compact pixel design.
3. The solid-state imaging device according to claim 2 , further comprising: a first signal line, a second signal line, a third signal line, and a fourth signal line, wherein the unit pixels include a first unit pixel and a second unit pixel, in the first unit pixel, a gate of the first amplification transistor and a gate of the second amplification transistor are connected to the charge accumulation unit, a source of the first amplification transistor and a source of the second amplification transistor are connected to the third signal line, a drain of the first amplification transistor is connected to the first signal line via the first selection transistor, and a drain of the second amplification transistor is connected to the first signal line via the second selection transistor, and in the second unit pixel, a gate of the first amplification transistor and a gate of the second amplification transistor are connected to the charge accumulation unit, a source of the first amplification transistor and a source of the second amplification transistor are connected to the fourth signal line, a drain of the first amplification transistor is connected to the second signal line via the first selection transistor, and a drain of the second amplification transistor is connected to the second signal line via the second selection transistor.
The invention relates to solid-state imaging devices, specifically a pixel architecture for CMOS image sensors that enhances signal readout efficiency and reduces noise. The device comprises unit pixels arranged in a matrix, each containing a charge accumulation unit, first and second amplification transistors, and first and second selection transistors. The key innovation involves a dual-signal-line configuration where adjacent unit pixels share signal lines in a structured manner to optimize signal routing. In the first unit pixel, the gates of both amplification transistors connect to the charge accumulation unit, while their sources connect to a third signal line. The drains of these transistors link to a first signal line via their respective selection transistors. In the second unit pixel, the same gate and source connections apply, but the drains connect to a second signal line through their selection transistors. The third and fourth signal lines serve as source lines for their respective pixels, enabling parallel signal paths. This arrangement allows for differential or separate readout of signals from adjacent pixels, improving signal integrity and reducing crosstalk. The configuration supports high-speed imaging and enhances dynamic range by enabling flexible signal processing strategies.
4. The solid-state imaging device according to claim 3 , further comprising: a current mirror circuit connected to the first signal line and the second signal line; and a constant current circuit connected to the third signal line and the fourth signal line.
A solid-state imaging device includes a pixel array with multiple pixels, each having a photoelectric conversion element and a transfer transistor. The device further includes a first signal line and a second signal line connected to a first pixel, and a third signal line and a fourth signal line connected to a second pixel. A current mirror circuit is connected to the first and second signal lines, while a constant current circuit is connected to the third and fourth signal lines. The current mirror circuit ensures that the current flowing through the first signal line matches the current flowing through the second signal line, maintaining signal integrity during readout. The constant current circuit provides a stable reference current to the third and fourth signal lines, ensuring consistent operating conditions for the pixels. This configuration improves signal accuracy and reduces noise in the imaging device, particularly in applications requiring high sensitivity and low power consumption, such as digital cameras and medical imaging systems. The device may also include a reset transistor and an amplifier transistor in each pixel to further enhance signal processing efficiency.
5. The solid-state imaging device according to claim 3 , further comprising: a constant current circuit; a first switch configured to switch connection between the first signal line or the second signal line and the constant current circuit; and a second switch configured to switch connection between the third signal line or the fourth signal line and a predetermined power supply voltage.
A solid-state imaging device includes a pixel array with multiple pixels, each having a photoelectric conversion element and a transfer transistor to transfer charge from the element to a floating diffusion node. The device also has a first signal line connected to the floating diffusion node and a second signal line connected to a reset transistor. A third signal line is connected to a selection transistor, and a fourth signal line is connected to a power supply line. The device further includes a constant current circuit and a first switch that selectively connects either the first or second signal line to the constant current circuit. Additionally, a second switch selectively connects either the third or fourth signal line to a predetermined power supply voltage. This configuration allows for controlled signal readout and reset operations, improving the imaging device's performance by stabilizing current flow and voltage levels during operation. The design ensures efficient charge transfer and signal processing, addressing issues related to noise and signal integrity in solid-state imaging devices.
6. The solid-state imaging device according to claim 5 , further comprising: a current mirror circuit including a first transistor connected to the first signal line and a second transistor connected to the second signal line; a third switch configured to switch connection between the third signal line and the constant current circuit; a fourth switch configured to switch connection between the fourth signal line and the constant current circuit; a fifth switch configured to switch connection between the gate of each of the first amplification transistor and the second amplification transistor and the first signal line in the first unit pixel; a sixth switch configured to switch connection between the gate of each of the first amplification transistor and the second amplification transistor and the second signal line in the second unit pixel; a seventh switch configured to switch connection between a gate of each of the first transistor and the second transistor and a drain of the first transistor; and an eighth switch configured to switch connection between the gate of each of the first transistor and the second transistor and a drain of the second transistor.
Solid-state imaging devices. This invention addresses limitations in signal amplification within solid-state imaging devices. The described solid-state imaging device includes a unit pixel. This device incorporates a current mirror circuit comprised of a first transistor connected to a first signal line and a second transistor connected to a second signal line. Additional components include a third switch for connecting a third signal line to a constant current circuit and a fourth switch for connecting a fourth signal line to the constant current circuit. Further, a fifth switch is provided to connect the gates of amplification transistors within a first unit pixel to the first signal line. A sixth switch connects the gates of amplification transistors within a second unit pixel to the second signal line. A seventh switch facilitates connection between the gates of the first and second transistors of the current mirror circuit and the drain of the first transistor. An eighth switch enables connection between the gates of the first and second transistors of the current mirror circuit and the drain of the second transistor.
7. The solid-state imaging device according to claim 6 , further comprising: a control unit configured to switch connection states of the first switch to the eighth switch, wherein in a case of performing source follower read-out on the unit pixels, the control unit causes the first switch and the second switch to be in an ON state and causes the third switch to the eighth switch to be in an OFF state to configure a source follower circuit.
A solid-state imaging device includes an array of unit pixels, each containing a photodiode, a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor. The device also features a first to eighth switch connected to the unit pixels to control signal readout. A control unit dynamically adjusts the connection states of these switches. During source follower readout, the control unit activates the first and second switches while deactivating the third through eighth switches, forming a source follower circuit. This configuration isolates the pixel signal path, ensuring accurate signal amplification and readout. The control unit's switching logic optimizes signal integrity by selectively enabling or disabling signal pathways, reducing noise and interference during operation. The device enhances imaging performance by precisely controlling signal flow through the pixel array, improving sensitivity and dynamic range. The switching mechanism allows flexible readout modes, supporting various imaging applications while maintaining low power consumption and high reliability.
8. The solid-state imaging device according to claim 7 , wherein in a case of performing differential amplification read-out to read out a pixel signal from the first unit pixel, the control unit causes the first switch, the second switch, and the eighth switch to be in the OFF state, and causes the third switch to the seventh switch to be in the ON state to configure a first differential amplifier circuit, and in a case of performing differential amplification read-out to read out a pixel signal from the second unit pixel, the control unit causes the first switch, the second switch, and the seventh switch to be in the OFF state, and causes the third switch to the sixth switch and the eighth switch to be in the ON state to configure a second differential amplifier circuit.
This invention relates to solid-state imaging devices, specifically addressing the challenge of efficiently reading out pixel signals from multiple unit pixels in a differential amplification mode. The device includes a first and second unit pixel, each configured to output a pixel signal, and a control unit that manages the readout process. The control unit selectively activates or deactivates a set of switches to configure different differential amplifier circuits for reading signals from each unit pixel. For the first unit pixel, the control unit turns off the first, second, and eighth switches while turning on the third through seventh switches, forming a first differential amplifier circuit. For the second unit pixel, the control unit turns off the first, second, and seventh switches while turning on the third through sixth and eighth switches, forming a second differential amplifier circuit. This selective switching ensures accurate and efficient signal readout from each unit pixel, improving the overall performance of the imaging device. The invention enhances signal processing by dynamically configuring the amplifier circuit based on the pixel being read, reducing noise and improving signal integrity.
9. The solid-state imaging device according to claim 3 , wherein the first amplification transistor and the second amplification transistor have a same structure.
A solid-state imaging device includes an array of pixels, each containing a photoelectric conversion element, a transfer transistor, a reset transistor, a selection transistor, and two amplification transistors. The photoelectric conversion element converts incident light into an electrical signal. The transfer transistor transfers the electrical signal to a floating diffusion node. The reset transistor resets the potential of the floating diffusion node. The selection transistor selectively outputs the signal from the pixel. The two amplification transistors amplify the signal from the floating diffusion node. The first and second amplification transistors have identical structures, ensuring consistent amplification characteristics across the device. This design improves signal uniformity and reduces noise, enhancing image quality in applications such as digital cameras and medical imaging systems. The identical structure of the amplification transistors simplifies manufacturing and ensures reliable performance. The device may also include a charge accumulation section to accumulate charge from the photoelectric conversion element, further improving sensitivity and dynamic range. The overall configuration optimizes signal processing efficiency while maintaining high precision in image capture.
10. The solid-state imaging device according to claim 3 , wherein a gate insulating film of the second amplification transistor is thinner than a gate insulating film of the first amplification transistor.
A solid-state imaging device includes multiple amplification transistors to improve signal processing efficiency. The device addresses the challenge of balancing signal amplification and noise reduction in imaging sensors. The first amplification transistor has a thicker gate insulating film, which provides robustness and stability in signal amplification. The second amplification transistor has a thinner gate insulating film, enhancing its sensitivity and responsiveness to input signals. By using different gate insulating film thicknesses, the device optimizes performance for different stages of signal processing. The first amplification transistor ensures reliable amplification with reduced leakage, while the second amplification transistor improves signal fidelity and speed. This configuration allows the imaging device to achieve higher dynamic range and lower noise levels, making it suitable for high-performance imaging applications. The design leverages the distinct advantages of each transistor type to enhance overall imaging quality.
11. The solid-state imaging device according to claim 3 , wherein a gate length of the second amplification transistor is longer than a gate length of the first amplification transistor.
A solid-state imaging device includes a pixel array with multiple pixels, each containing a photodiode, a transfer transistor, a reset transistor, a first amplification transistor, and a second amplification transistor. The photodiode converts incident light into an electrical signal, which the transfer transistor transfers to a floating diffusion node. The reset transistor resets the floating diffusion node to a reference voltage. The first amplification transistor amplifies the signal from the floating diffusion node, while the second amplification transistor further amplifies the output of the first amplification transistor. The second amplification transistor has a longer gate length than the first amplification transistor, which improves signal stability and reduces noise in the amplified output. This configuration enhances the dynamic range and sensitivity of the imaging device, making it suitable for high-performance applications such as digital cameras and medical imaging systems. The longer gate length of the second amplification transistor helps maintain linearity and reduces distortion in the amplified signal, ensuring accurate image capture. The device may also include additional transistors for readout and control functions, optimizing power efficiency and performance.
12. The solid-state imaging device according to claim 2 , further comprising: a drive circuit configured to drive a unit pixel to be read out among the unit pixels, wherein in a case of reading out a pixel signal from the unit pixel to be read out with first conversion efficiency, the drive circuit gives a first selection control signal of High level to a gate of the first selection transistor while maintaining a second selection control signal to be given to a gate of the second selection transistor at Low level, and in a case of reading out a pixel signal from the unit pixel to be read out with second conversion efficiency lower than the first conversion efficiency, the drive circuit gives the first selection control signal of High level to the gate of the first selection transistor, and gives the second selection control signal of High level to the gate of the second selection transistor.
Solid-state imaging devices capture images by converting light into electrical signals using an array of unit pixels. Each unit pixel typically includes a photodiode for light detection and transistors for signal processing. A common challenge is achieving high dynamic range, where the device can accurately capture both bright and dim scenes. One approach involves adjusting the conversion efficiency of the pixel signal to optimize sensitivity and saturation limits. This invention describes a solid-state imaging device with a drive circuit that controls the readout of pixel signals using two selection transistors per unit pixel. The first selection transistor is used for standard readout, while the second selection transistor is activated to reduce the conversion efficiency when needed. The drive circuit selectively enables these transistors by applying control signals. For high-efficiency readout, only the first selection transistor is activated by setting its gate signal to High while keeping the second transistor's gate signal Low. For lower efficiency, both transistors are activated by setting both gate signals to High, effectively reducing the signal conversion efficiency. This dual-transistor control allows dynamic adjustment of the pixel's sensitivity, improving the device's dynamic range without requiring additional complex circuitry. The invention enhances image quality by adapting to varying light conditions while maintaining simplicity in design.
13. The solid-state imaging device according to claim 10 , further comprising: a drive circuit configured to drive a unit pixel to be read out among the unit pixels, wherein in a case of reading out a pixel signal from the unit pixel to be read out with first conversion efficiency, the drive circuit gives a first selection control signal of High level to a gate of the first selection transistor while maintaining a second selection control signal to be given to a gate of the second selection transistor at Low level, and in a case of reading out a pixel signal from the unit pixel to be read out with second conversion efficiency lower than the first conversion efficiency, the drive circuit maintains the first selection control signal to be given to the gate of the first selection transistor at Low level, and gives the second selection control signal of High level to the gate of the second selection transistor.
A solid-state imaging device includes a pixel array with unit pixels, each containing a photodiode, a transfer transistor, an amplification transistor, a reset transistor, a first selection transistor, and a second selection transistor. The device also includes a drive circuit that controls the readout of pixel signals from selected unit pixels. The drive circuit can adjust the conversion efficiency of the pixel signal readout by selectively activating either the first or second selection transistor. For high conversion efficiency, the drive circuit sets the first selection control signal to High level while keeping the second selection control signal at Low level. For lower conversion efficiency, the drive circuit sets the second selection control signal to High level while keeping the first selection control signal at Low level. This allows the device to dynamically switch between different signal conversion efficiencies based on the readout requirements, improving flexibility and performance in imaging applications. The amplification transistor amplifies the pixel signal, and the reset transistor resets the pixel signal level. The transfer transistor controls the transfer of charge from the photodiode to a floating diffusion node, which is connected to the amplification transistor. The selection transistors determine the signal path for readout, enabling efficient signal processing.
14. The solid-state imaging device according to claim 3 , wherein the first amplification transistor and the first selection transistor, and the second amplification transistor and the second selection transistor are laid out in a line symmetric manner about the third signal line or the fourth signal line as a center axis in each of the first unit pixel and the second unit pixel.
This invention relates to a solid-state imaging device with an improved pixel layout for enhancing signal integrity and reducing noise. The device includes multiple unit pixels, each containing at least two amplification transistors and two selection transistors. The key innovation involves arranging these transistors in a line-symmetric layout about a central signal line within each unit pixel. This symmetric arrangement ensures balanced electrical characteristics and minimizes signal distortion during readout. The first amplification transistor and first selection transistor are positioned symmetrically to the second amplification transistor and second selection transistor, with the signal line acting as the axis of symmetry. This layout reduces parasitic capacitance and improves signal-to-noise ratio by maintaining consistent electrical paths for both amplification and selection functions. The symmetric design also facilitates efficient routing of signal lines, reducing crosstalk between adjacent pixels. The invention is particularly useful in high-resolution imaging applications where precise signal integrity is critical. The symmetric transistor arrangement ensures uniform performance across the pixel array, enhancing overall image quality.
15. The solid-state imaging device according to claim 1 , wherein each of the unit pixels further includes a reset transistor configured to cause an electric charge in the charge accumulation unit to be discharged.
A solid-state imaging device captures images by converting light into electrical signals using an array of unit pixels. Each unit pixel includes a photoelectric conversion element, such as a photodiode, that generates an electric charge proportional to incident light. The charge is accumulated in a charge accumulation unit, typically a floating diffusion node, and then read out as a voltage signal. However, residual charge in the charge accumulation unit can introduce noise and degrade image quality, particularly in low-light conditions. To address this, the imaging device includes a reset transistor in each unit pixel. The reset transistor is connected to the charge accumulation unit and a power supply voltage. When activated, the reset transistor discharges the accumulated charge, resetting the charge accumulation unit to a known state. This ensures accurate signal readout by eliminating residual charge, reducing noise, and improving image quality. The reset transistor operates in synchronization with other pixel control signals, such as a transfer transistor that transfers charge from the photoelectric conversion element to the charge accumulation unit. This reset mechanism is essential for maintaining signal integrity in solid-state imaging devices, including CMOS image sensors, and is widely used in digital cameras, smartphones, and other imaging applications.
16. An electronic apparatus, comprising: a pixel array unit in which a plurality of unit pixels are arranged in a matrix direction; a drive circuit configured to drive a unit pixel to be read out among the unit pixels; a read-out circuit configured to read out an analog pixel signal from the unit pixel to be read out that is driven by the drive circuit; a signal processing circuit configured to convert the analog pixel signal read out by the read-out circuit into a digital value; and a control unit configured to control the drive circuit, the read-out circuit, and the signal processing circuit, wherein each of the unit pixels comprises: a photoelectric conversion element configured to generate an electric charge corresponding to an incident light quantity; a transfer transistor configured to transfer the electric charge generated in the photoelectric conversion element; a charge accumulation unit configured to accumulate the electric charge transferred by the transfer transistor; an amplification transistor including at least two fingers that are connected to the charge accumulation unit in parallel; and a selection transistor that is disposed corresponding to each of the fingers of the amplification transistor on a one-to-one basis.
This invention relates to an electronic apparatus, specifically an image sensor, designed to improve signal readout efficiency and reduce noise in pixel arrays. The apparatus includes a pixel array unit with multiple unit pixels arranged in a matrix, each containing a photoelectric conversion element that generates electric charge proportional to incident light. A transfer transistor moves this charge to a charge accumulation unit, which is connected to an amplification transistor. The amplification transistor features at least two fingers connected in parallel to the charge accumulation unit, enhancing signal amplification. Each finger of the amplification transistor is paired with a dedicated selection transistor, allowing independent readout paths. A drive circuit selects and drives the unit pixel to be read, while a read-out circuit captures the analog pixel signal. A signal processing circuit converts this analog signal into a digital value, and a control unit coordinates the operations of these components. The parallel amplification fingers and dedicated selection transistors improve signal integrity and reduce noise, particularly in high-resolution or low-light imaging applications. This design optimizes charge handling and readout efficiency in image sensors.
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September 11, 2019
April 12, 2022
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