Semiconductor device containing tubular liner spacer for lateral confinement of self-aligned silicide portions and methods of forming the same

1. A semiconductor structure comprising: a semiconductor channel of a first conductivity type located between a first active region and a second active region having a doping of a second conductivity type that is opposite of the first conductivity type; a gate stack structure that overlies the semiconductor channel, and comprises a gate dielectric and a gate electrode; a first metal-semiconductor alloy portion embedded in the first active region and comprising a metal-semiconductor alloy material comprising a first elemental metal and a semiconductor material in the first active region; and a first composite contact via structure in contact with the first active region and the first metal-semiconductor alloy portion and comprising: a first tubular liner spacer including a first annular bottom surface; a first metallic nitride liner comprising a metallic nitride material including a second elemental metal and nitrogen atoms, and contacting an inner sidewall of the first tubular liner spacer and having a bottom surface that is located above a horizontal plane including the first annular bottom surface of the first tubular liner spacer, wherein the second elemental metal is different from the first elemental metal; and a first metallic fill material portion embedded in the first metallic nitride liner.

2. The semiconductor structure of claim 1 , wherein: an entirety of the bottom surface of the first metallic nitride liner contacts a top surface of the first metal-semiconductor alloy portion; and the first annular bottom surface of the first tubular liner spacer contacts a recessed annular top surface of the first metal-semiconductor alloy portion.

3. The semiconductor structure of claim 2 , wherein a cylindrical bottom segment of an inner sidewall of the first tubular liner spacer contacts a cylindrical sidewall of the first metal-semiconductor alloy portion.

4. The semiconductor structure of claim 2 , wherein a cylindrical bottom segment of an outer sidewall of the first tubular liner spacer contacts a cylindrical surface of the first active region.

5. The semiconductor structure of claim 1 , wherein: the semiconductor channel is located in a substrate semiconductor layer which is located in or on a substrate; and the first annular bottom surface of the first tubular liner spacer is located below a horizontal plane including an interface between the substrate semiconductor layer and the gate dielectric.

6. The semiconductor structure of claim 5 , wherein the first annular bottom surface of the first tubular liner spacer is vertically offset from the horizontal plane including the interface between the substrate semiconductor layer and the gate dielectric by a vertical offset distance in a range from 3 nm to 60 nm.

7. The semiconductor structure of claim 5 , wherein the first metal-semiconductor alloy portion is not in direct contact with a topmost surface of the first active region.

8. The semiconductor structure of claim 5 , further comprising a contact-level dielectric layer overlying the substrate and overlying, and laterally surrounding, the gate stack structure, wherein the first composite contact via structure vertically extends through the contact-level dielectric layer.

9. The semiconductor structure of claim 1 , wherein the first metal-semiconductor alloy portion comprises a metal silicide portion.

10. The semiconductor structure of claim 1 , further comprising: a second metal-semiconductor alloy portion embedded in the second active region; and a second composite contact via structure in contact with the second active region and the second metal-semiconductor alloy portion and comprising: a second tubular liner spacer including a second annular bottom surface, a second metallic nitride liner contacting an inner sidewall of the second tubular liner spacer and having a bottom surface that is located above the horizontal plane including the second annular bottom surface of the second tubular liner spacer, and a second metallic fill material portion embedded in the second metallic nitride liner.

11. The semiconductor structure of claim 1 , wherein the first tubular liner spacer consists essentially of at least one dielectric material.

12. The semiconductor structure of claim 1 , wherein the first tubular liner spacer consists essentially of a conductive metallic nitride material having a different material composition than the first metallic nitride liner.

13. The semiconductor structure of claim 1 , further comprising: a gate cap dielectric that overlies the gate electrode; an additional metal-semiconductor alloy portion embedded in an upper portion of the gate electrode; and a gate composite contact via structure comprising: a gate tubular liner spacer vertically extending through the gate cap dielectric and into an upper portion of the gate electrode and contacting an annular surface of the additional metal-semiconductor alloy portion and contacting a sidewall of a protruding portion of the additional metal-semiconductor alloy portion, a gate metallic nitride liner contacting an inner sidewall of the gate tubular liner spacer and having a bottom surface that is located above a horizontal plane including the annular surface of the additional metal-semiconductor alloy portion, and a gate metallic fill material portion embedded in the gate metallic nitride liner and having a bottom surface located below a horizontal plane including a top surface of the gate cap dielectric.

14. A method of forming a semiconductor structure, comprising: forming a first active region in a substrate semiconductor layer located on or in a substrate, wherein the first active region has a doping of an opposite conductivity type than the substrate semiconductor layer; forming a contact-level dielectric layer above the substrate; forming a first contact via cavity extending into the first active region through the contact-level dielectric layer; forming a first tubular liner spacer at a periphery of the first contact via cavity; forming a first metal-semiconductor alloy portion on the first active region at a bottom region of the first contact via cavity by depositing a metal layer comprising a first elemental metal on the substrate semiconductor layer, and by inducing formation of a metal-semiconductor alloy material through reaction of the first metal with a semiconductor material in the first active region; removing unreacted portion of the metal layer selective to the first metal-semiconductor alloy portion from inside the first contact via cavity, whereby a top surface of the first metal-semiconductor alloy portion is physically exposed; forming a first metallic nitride liner comprising a metallic nitride material including nitrogen atoms and a second elemental metal different from the first elemental metal directly on the first tubular liner spacer and the first metal-semiconductor alloy portion; and forming a first metallic fill material portion in the first metallic nitride liner, wherein the first contact via cavity is filled with a first composite contact via structure including the first tubular liner spacer, the first metallic nitride liner, and the first metallic fill material portion.

15. The method of claim 14 , further comprising: forming a gate stack structure over a portion of the substrate semiconductor layer; and forming a second active region in the substrate semiconductor layer, wherein: the gate stack structure comprises a gate dielectric, a gate electrode, and a gate cap dielectric; and the contact-level dielectric layer is formed above, and around, the gate stack structure, above the first active region, and above the second active region.

16. The method of claim 14 , further comprising: depositing a metal on the first active region after formation of the first active region; and forming the first metal-semiconductor alloy portion by reacting the metal with a surface portion of the first active region.

17. The method of claim 14 , wherein: a bottom surface of the first contact via cavity is vertically recessed below a horizontal plane including a top surface of the first active region; and the first tubular liner spacer is formed on the top surface of the first active region; the first metal-semiconductor alloy portion has a bottom surface located below a horizontal plane including an annular bottom surface of the first tubular liner spacer and a top surface located above the horizontal plane including the annular bottom surface of the first tubular liner spacer; and the first metallic nitride liner is formed on the top surface of the first metal-semiconductor alloy portion.

18. The method of claim 14 , further comprising: forming a liner spacer material layer on a top surface of the first active region, on a sidewall of the first via cavity, and over the contact-level dielectric layer; and anisotropically etching horizontal portions of the liner spacer material layer, wherein a remaining vertical portion of the liner spacer material layer comprises the first tubular liner spacer.

19. The method of claim 14 , wherein the first tubular liner spacer consists essentially of a conductive metallic nitride material having a different material composition than the first metallic nitride liner.

20. The method of claim 15 , further comprising: forming a gate contact via cavity through the contact-level dielectric layer, the gate cap dielectric, and an upper portion of the gate electrode; forming a gate tubular liner spacer at a periphery of the gate contact via cavity, wherein a portion of the gate tubular liner spacer contacts a sidewall of the gate electrode around the gate contact via cavity; and forming a gate metal-semiconductor alloy portion on the gate electrode at a bottom of the gate contact via cavity by depositing the metal layer and by inducing formation of an additional metal-semiconductor alloy material through reaction of the first metal with a semiconductor material in the gate electrode, wherein gate metal-semiconductor alloy portion contacts a lower portion of an inner sidewall of the gate tubular liner spacer.