A device includes an operation control circuit and a drive control signal generation circuit. The operation control circuit generates an internal refresh signal that is activated to perform an active operation for a cell array, the cell array being coupled to a word line that is selected by a row address based on a refresh signal that is activated to perform a refresh operation. In addition, the operation control circuit generates a pre-refresh pulse based on the refresh signal and generates a refresh end pulse based on the internal refresh signal. The drive control signal generation circuit generates a drive control signal to control a drive of an active voltage that is supplied to the word line that is selected by the row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A device comprising: an operation control circuit configured to generate an internal refresh signal that is activated to perform an active operation for a cell array, the cell array being coupled to a word line that is selected by a row address based on a refresh signal that is activated to perform a refresh operation, configured to generate a pre-refresh pulse based on the refresh signal, and configured to generate a refresh end pulse based on the internal refresh signal; a drive control signal generation circuit configured to generate a drive control signal to control a drive of an active voltage that is supplied to the word line that is selected by the row address, based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse; and an active voltage generation circuit that is configured to drive the active voltage to the first internal voltage when the drive control signal has a first logic level and configured to drive the active voltage to the second internal voltage when the drive control signal has a second logic level.
2. The device of claim 1 , wherein the operation control circuit includes a start pulse generation circuit that is configured to generate a start pulse when the refresh signal is activated.
3. The device of claim 2 , wherein the operation control circuit further includes a refresh pulse generation circuit that is configured to generate a refresh pulse during each internal refresh cycle that is set based on a refresh clock signal that is generated when the refresh signal is activated and configured to generate the pre-refresh pulse before the refresh pulse is generated.
4. The device of claim 3 , wherein a cycle of the refresh clock signal is set to be constant.
5. The device of claim 3 , wherein a cycle of the refresh clock signal is adjusted based on an internal temperature of the device.
6. The device of claim 3 , wherein the operation control circuit further includes an internal refresh signal generation circuit that is configured to generate the internal refresh signal that is activated when the start pulse or the refresh pulse is generated.
7. The device of claim 6 , wherein the operation control circuit further includes a refresh end pulse generation circuit that is configured to generate the refresh end pulse in synchronization with a point in time in which the internal refresh signal is deactivated.
8. The device of claim 1 , wherein the drive control signal generation circuit is configured to generate the drive control signal to boost a level of the active voltage when the refresh signal is deactivated or both of the refresh signal and the internal refresh signal are activated.
9. The device of claim 1 , wherein the drive control signal generation circuit is configured to generate the drive control signal to boost a level of the active voltage during a period from a point in time in which the pre-refresh pulse is generated until a point in time in which the refresh end pulse is generated while the refresh signal is activated.
10. The device of claim 1 , wherein the first internal voltage is set to be higher than the second internal voltage.
11. The device of claim 1 , wherein the drive control signal generation circuit is configured to generate the drive control signal with the first logic level when the refresh signal is deactivated, configured to generate the drive control signal with the first logic level when both of the refresh signal and the internal refresh signal are activated, and configured to generate the drive control signal with the first logic level during a period from a point in time in which the pre-refresh pulse is generated until a point in time in which the refresh end pulse is generated while the refresh signal is activated.
12. The device of claim 1 , further comprising: a row address generation circuit configured to generate the row address based on the internal refresh signal; and a word line drive circuit configured to supply the active voltage to the word line that is selected by the row address.
13. A device comprising: a refresh pulse generation circuit configured to generate a refresh pulse during each internal refresh cycle that is set based on a refresh clock signal that is generated when a refresh signal is activated and configured to generate a pre-refresh pulse before the refresh pulse is generated; an internal refresh signal generation circuit configured to generate an internal refresh signal based on a start pulse that is generated when the refresh signal is activated and the refresh pulse; a refresh end pulse generation circuit configured to generate a refresh end pulse based on the internal refresh signal; and a drive control signal generation circuit configured to generate a drive control signal to control a drive of an active voltage that is supplied to a word line that is selected by a row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.
14. The device of claim 13 , wherein a cycle of the refresh clock signal is adjusted based on an internal temperature of the device.
15. The device of claim 13 , wherein the refresh end pulse is generated in synchronization with a point in time in which the internal refresh signal is deactivated.
16. The device of claim 13 , further comprising an active voltage generation circuit that is configured to drive the active voltage to a first internal voltage when the drive control signal has a first logic level and configured to drive the active voltage to a second internal voltage when the drive control signal has a second logic level.
17. The device of claim 16 , wherein the first internal voltage is set to be higher than the second internal voltage.
18. The device of claim 16 , wherein the drive control signal generation circuit is configured to generate the drive control signal with the first logic level when the refresh signal is deactivated, configured to generate the drive control signal with the first logic level when both of the refresh signal and the internal refresh signal are activated, and configured to generate the drive control signal with the first logic level during a period from a point in time in which the pre-refresh pulse is generated until a point in time in which the refresh end pulse is generated while the refresh signal is activated.
19. A device comprising: a refresh clock generation circuit configured to generate a refresh clock signal, whose cycle is adjusted based on a temperature code when a refresh signal is activated; a refresh pulse generation circuit configured to generate a refresh pulse during each internal refresh cycle that is set based on the refresh clock signal and configured to generate a pre-refresh pulse before the refresh pulse is generated; an internal refresh signal generation circuit configured to generate an internal refresh signal based on a start pulse that is generated when the refresh signal is activated and the refresh pulse; a refresh end pulse generation circuit configured to generate a refresh end pulse based on the internal refresh signal; and a drive control signal generation circuit configured to generate a drive control signal to control a drive of an active voltage that is supplied to a word line that is selected by a row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.
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September 1, 2020
April 26, 2022
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