A single-rail memory circuit includes an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array for facilitating read and write operations with respect to selected memory cells. The peripheral circuitry includes, but is not limited to, boost circuits for the rows. Each boost circuit is connected to a wordline for a row and to a discrete voltage supply line for the same row. Each boost circuit for a row is configured to increase the voltage levels on the wordline and the voltage supply line for the row during a read of any selected memory cell within the row. Increasing the voltage levels on the wordline and on the voltage supply line during the read operation effectively boosts the read current. A method of operating the memory circuit reduces the probability of a read fail.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A structure comprising: memory cells arranged in rows and columns; wordlines for the rows, wherein each wordline for each row is connected to all of the memory cells in the row; voltage supply lines for the rows, wherein each voltage supply line for each row is connected to all of the memory cells in the row; and boost circuits for the rows, wherein each boost circuit for each row is connected to the wordline for the row and to the voltage supply line for the row and comprises: two coupling capacitors connected in series between the wordline and the voltage supply line for the row; and a coupling capacitor driver with a coupling capacitor driver output node connected to an intermediate node between the two coupling capacitors.
2. The structure of claim 1 , wherein each boost circuit for each row is configured to perform boosting of voltage levels on the wordline and the voltage supply line for the row.
3. The structure of claim 1 , wherein each boost circuit for each row is configured to increase voltage levels on the wordline and the voltage supply line for the row during a read operation to read a stored data value in a memory cell in the row.
4. The structure of claim 3 , wherein the increasing of the voltage levels on the wordline and the voltage supply line for the row during the read operation boosts read current.
5. The structure of claim 3 , further comprising a positive voltage rail at a first positive voltage level, wherein each boost circuit for each row is connected to the positive voltage rail, wherein each boost circuit for each row is configured to increase a voltage level on the wordline for the row from ground to the first positive voltage level upon initiation of the read operation, and wherein each boost circuit for each row is further configured to increase the voltage levels on both the wordline and the voltage supply line for the row from the first positive voltage level to a second positive voltage level that is greater than the first positive voltage level when the voltage level on the wordline has reached the first positive voltage level.
6. The structure of claim 5 , wherein each boost circuit for each row comprises: a wordline driver with a wordline driver output node connected to the wordline; a header switch connected between the positive voltage rail and the voltage supply line for the row; a synchronization circuit connected to the wordline driver, the coupling capacitor driver, and the header switch; and a feedback path from the wordline driver output node to the synchronization circuit, wherein the feedback path ensures that the synchronization circuit causes synchronized and concurrent increasing of the voltage levels on the wordline and the voltage supply line for the row when the wordline driver has switched the voltage level on the wordline to the first positive voltage level.
7. The structure of claim 1 , wherein the memory cells comprise static random access memory cells.
8. A structure comprising: memory cells arranged in rows and columns; wordlines for the rows, wherein each wordline for each row is connected to all of the memory cells in the row; voltage supply lines for the rows, wherein each voltage supply line for each row is connected to all of the memory cells in the row; and boost circuits for the rows, wherein each boost circuit for each row is connected to the wordline for the row and to the voltage supply line for the row, wherein each boost circuit for each row comprises: two coupling capacitors connected in series between the wordline and the voltage supply line for the row; and a coupling capacitor driver with a coupling capacitor driver output node connected to an intermediate node between the two coupling capacitors, and wherein each boost circuit for each row is configured to perform synchronized and concurrent increasing of voltage levels on the wordline and the voltage supply line for the row.
9. The structure of claim 8 , further comprising: first and second bitlines for the columns, wherein each memory cell in each specific row and specific column comprises a six-transistor static random access memory cell comprising: a first inverter comprising a first pull-up transistor and a first pull-down transistor connected in series between the voltage supply line for the specific row and a ground rail; a second inverter cross-coupled to the first inverter and comprising a second pull-up transistor and a second pull-down transistor connected in series between the voltage supply line for the specific row and the ground rail; a first access transistor connected in series between a first bitline for the specific column and a first storage node at a junction between the first pull-up transistor and the first pull-down transistor; and a second access transistor connected between a second bitline for the specific column and a second storage node at a junction between the second pull-up transistor and the second pull-down transistor, wherein the wordline for the specific row is connected to gates of the first access transistor and the second access transistor.
10. The structure of claim 8 , further comprising a controller causing one boost circuit for one row at a time to perform the synchronized and concurrent increasing of the voltage levels on the wordline and the voltage supply line for the one row.
11. The structure of claim 8 , wherein each boost circuit for each row is configured to perform the synchronized and concurrent increasing of the voltage levels on the wordline and the voltage supply line for the row during a read operation in order to boost read current.
12. The structure of claim 11 , further comprising a positive voltage rail at a first positive voltage level, wherein each boost circuit for each row is connected to the positive voltage rail, wherein each boost circuit for each row is configured to increase a voltage level on the wordline for the row from ground to the first positive voltage level upon initiation of the read operation, and wherein each boost circuit for each row is further configured to increase the voltage levels on the wordline and the voltage supply line for the row from the first positive voltage level to a second positive voltage level that is greater than the first positive voltage level when the voltage level on the wordline has reached the first positive voltage level.
13. The structure of claim 12 , wherein each boost circuit for each row comprises: a wordline driver with a wordline driver output node connected to the wordline; a header switch connected between the positive voltage rail and the voltage supply line for the row; a synchronization circuit connected to the wordline driver, the coupling capacitor driver, and the header switch; and a feedback path from the wordline driver output node to the synchronization circuit, wherein the feedback path ensures that the synchronization circuit causes the synchronized and concurrent increasing of the voltage levels on the wordline and the voltage supply line for the row when the wordline driver has switched the voltage level on the wordline to the first positive voltage level.
14. The structure of claim 13 , wherein the wordline driver comprises: a first p-type field effect transistor and a first n-type field effect transistor connected in series between the positive voltage rail and a ground rail with the wordline driver output node being at a junction between the first p-type field effect transistor and the first n-type field effect transistor, wherein the coupling capacitor driver comprises: a second p-type field effect transistor and a second n-type field effect transistor connected in series between the positive voltage rail and the ground rail with the coupling capacitor driver output node being at a junction between the second p-type field effect transistor and the second n-type field effect transistor, and wherein the header switch comprises a third p-type field effect transistor.
15. The structure of claim 14 , wherein the synchronization circuit comprises: a first inverter that receives an inverted read clock signal and outputs a read clock signal, wherein the inverted read clock signal is row-specific; a second inverter that receives the read clock signal and outputs a first wordline driver control signal, wherein the first wordline driver control signal is applied to a gate of the first n-type field effect transistor of the wordline driver; an AND gate that receives the read clock signal and a feedback signal transmitted along the feedback path from the wordline driver output node and outputs a synchronization control signal; an OR gate that receives the inverted read clock signal and the synchronization control signal and outputs a second wordline driver control signal, wherein the second wordline driver control signal is applied to a gate of the first p-type field effect transistor of the wordline driver; and a NAND gate that receives the synchronization control signal and the second wordline driver control signal and outputs a coupling capacitor driver control signal, wherein the coupling capacitor driver control signal is applied to gates of the second p-type field effect transistor and the second n-type field effect transistor of the coupling capacitor driver, and wherein the read clock signal is further applied to a gate of the third p-type field effect transistor of the header switch.
16. A method comprising: providing a memory circuit comprising: memory cells arranged in rows and columns; wordlines for the rows, wherein each wordline for each row is connected to all of the memory cells in the row; and voltage supply lines for the rows, wherein each voltage supply line for each row is connected to all of the memory cells in the row; and boost circuits for the rows, wherein each boost circuit for each row is connected to the wordline for the row and to the voltage supply line for the row and comprises: two coupling capacitors connected in series between the wordline and the voltage supply line for the row; and a coupling capacitor driver with a coupling capacitor driver output node connected to an intermediate node between the two coupling capacitors; and increasing, by a boost circuit for a row, voltage levels on the wordline and the voltage supply line for the row.
17. The method of claim 16 , wherein the increasing of the voltage levels on the wordline and the voltage supply line for the row is synchronized and concurrent.
18. The method of claim 16 , wherein the increasing of the voltage levels on the wordline and the voltage supply line for the row is performed during a read operation in order to boost read current.
19. The method of claim 18 , wherein, by boosting the read current during the read operation, the method reduces a probability of a read fail.
20. The method of claim 16 , wherein the memory circuit further comprises a positive voltage rail at a first positive voltage level, wherein each boost circuit for each row is connected to the positive voltage rail, wherein the method further comprises performing a read operation to read a stored data value in a memory cell in the row, and wherein the performing of the read operation comprises: increasing, by the boost circuit for the row upon initiation of the read operation, a voltage level on the wordline for the row from ground to the first positive voltage level; and the increasing of the voltage levels on the wordline and the voltage supply line for the row, when the voltage level on the wordline for the row reaches the first positive voltage level such that the voltage levels on both the wordline and the voltage supply line for the row are increased from the first positive voltage level to a second positive voltage level that is greater than the first positive voltage level.
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December 14, 2020
May 3, 2022
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