A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate, and forming a bottom source/drain region adjacent a base of the fin. In the method, a dielectric layer, a work function metal layer and a first gate metal layer are sequentially deposited on the bottom source/drain region and around the fin. The dielectric layer, the work function metal layer and the first gate metal layer form a gate structure. The method also includes removing the dielectric layer, the work function metal layer and the first gate metal layer from an end portion of the fin, and depositing a second gate metal layer around the end portion of the fin in place of the removed dielectric layer, the removed work function metal layer and the removed first gate metal layer. The second gate metal layer contacts the end portion of the fin.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a channel region disposed on and extending perpendicularly with respect to a semiconductor substrate; a bottom source/drain region disposed adjacent a base of the channel region; a top source/drain region disposed on the channel region; a gate structure comprising a dielectric layer, a work function metal layer and a first gate metal layer disposed on the bottom source/drain region and around part of the channel region; and a second gate metal layer disposed around an end portion of channel region, wherein the second gate metal layer contacts the end portion of the channel region.
2. The semiconductor device according to claim 1 , further comprising a spacer layer disposed on the bottom source/drain region, wherein the second gate metal layer is disposed directly on the spacer layer.
3. The semiconductor device according to claim 2 , wherein the gate structure is disposed on the spacer layer.
4. The semiconductor device according to claim 1 , wherein the dielectric layer contacts the channel region, the work function metal layer is disposed on the dielectric layer and the first gate metal layer is disposed on the work function metal layer.
5. The semiconductor device according to claim 1 , wherein the second gate metal layer comprises the same material as the first gate metal layer.
6. The semiconductor device according to claim 1 , wherein the second gate metal layer comprises a different material from the first gate metal layer.
7. The semiconductor device according to claim 1 , wherein the second gate metal layer contacts sides of the end portion of the channel region extending perpendicularly with respect to the semiconductor substrate.
8. The semiconductor device according to claim 1 , wherein the second gate metal layer contacts three sides of the end portion of the channel region extending perpendicularly with respect to the semiconductor substrate.
9. The semiconductor device according to claim 1 , further comprising a spacer layer disposed on the gate structure and on the second gate metal layer.
10. The semiconductor device according to claim 1 , wherein the second gate metal layer has a vertical height the same or substantially the same as a vertical height of the gate structure.
11. A semiconductor device, comprising: a fin disposed on and extending perpendicularly with respect to a semiconductor substrate; a bottom source/drain region disposed adjacent a base of the fin; a top source/drain region disposed on the fin; a gate structure disposed on the bottom source/drain region and around part of the fin, wherein the gate structure comprises a dielectric layer contacting the fin and a first gate metal layer disposed on the dielectric layer; and a second gate metal layer disposed around an end portion of fin, wherein the second gate metal layer contacts the end portion of the fin.
12. The semiconductor device according to claim 11 , further comprising a spacer layer disposed on the bottom source/drain region, wherein the second gate metal layer is disposed directly on the spacer layer.
13. The semiconductor device according to claim 12 , wherein the gate structure is disposed on the spacer layer.
14. The semiconductor device according to claim 11 , wherein the gate structure further comprises a work function metal layer disposed between the dielectric layer and the first gate metal layer.
15. The semiconductor device according to claim 11 , wherein the second gate metal layer comprises the same material as the first gate metal layer.
16. The semiconductor device according to claim 11 , wherein the second gate metal layer comprises a different material from the first gate metal layer.
17. The semiconductor device according to claim 11 , wherein the second gate metal layer contacts sides of the end portion of the fin extending perpendicularly with respect to the semiconductor substrate.
18. The semiconductor device according to claim 11 , wherein the second gate metal layer contacts three sides of the end portion of the fin extending perpendicularly with respect to the semiconductor substrate.
19. The semiconductor device according to claim 11 , further comprising a spacer layer disposed on the gate structure and on the second gate metal layer.
20. The semiconductor device according to claim 11 , wherein the second gate metal layer has a vertical height the same or substantially the same as a vertical height of the gate structure.
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December 23, 2020
May 10, 2022
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