Novel voltage converter circuits are provided which step-up very low DC input voltages to higher voltages capable of supporting low-power loads. According to embodiments, a voltage step-up power converter circuit may be formed of an oscillator sub-circuit which receives a DC voltage and outputs an AC voltage; a voltage doubler sub-circuit which receives the AC voltage and outputs an augmented AC voltage; and a voltage step-up converter sub-circuit which receives the augmented AC voltage, as a control voltage, and the initial DC voltage and outputs a voltage which is more than the initial DC voltage. These circuits allow electrical energy to be harvested from very low voltage sources and to convert it as efficiently as possible to run a load.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A voltage step-up converter circuit comprising: an oscillator sub-circuit which receives a DC voltage and outputs an AC voltage; a voltage doubler sub-circuit which receives the AC voltage and outputs an augmented AC voltage; and a voltage step-up converter sub-circuit which receives the augmented AC voltage, as a control voltage, and the initial DC voltage and outputs a voltage which is more than the initial DC voltage.
2. The converter circuit of claim 1 , wherein the oscillator sub-circuit is configured as a Hartley oscillator.
3. The converter circuit of claim 2 , wherein the Hartley oscillator comprises: a transistor, two inductors connected in series; a fixed or variable equivalent capacitance connected in parallel with the series-connected inductors, and wherein a feedback signal to the transistor needed for oscillation is provided by one of the inductors.
4. The converter circuit of claim 3 , wherein the two series-connected inductors are magnetically coupled and comprise a coupled inductor having two windings, or a tapped inductor having one tap point.
5. The converter circuit of claim 3 , wherein the transistor comprises a depletion-mode transistor or a normally-on transistor.
6. The converter circuit of claim 1 , wherein the voltage doubler sub-circuit is configured as a Villard circuit.
7. The converter circuit of claim 6 , wherein the Villard circuit comprises a diode and a capacitor connected in series.
8. The converter circuit of claim 6 , wherein the Villard circuit provides a DC offset to the AC voltage it receives.
9. The converter circuit of claim 1 , wherein the voltage step-up converter sub-circuit comprises: a coupled inductor having a primary winding and a secondary winding; a transistor connected to the primary winding; and a diode connected to the secondary winding, wherein the voltage output of voltage step-up converter sub-circuit is more than the initial DC voltage and is based on the ratio of turns of the primary and secondary windings of the coupled inductor and on the duty cycle of the transistor or the duration of time the transistor is in an on-state.
10. The converter circuit of claim 9 , wherein the coupled inductor comprises a transformer.
11. The converter circuit of claim 9 , wherein the voltage step-up converter is configured as a flyback converter sub-circuit comprising: a capacitor in series with the diode connected to the secondary winding, wherein a load is parallel with the capacitor.
12. The converter circuit of claim 9 , wherein the diode of the voltage step-up converter sub-circuit comprises a light-emitting diode (LED), which is capable of reverse-voltage blocking.
13. The converter circuit of claim 9 , wherein the portion of the converter circuit connected to the primary winding and the portion of the converter circuit connected to the secondary winding are connected together.
14. The converter circuit of claim 9 , wherein the transistor comprises an enhancement-mode transistor or a normally-off transistor.
15. The converter circuit of claim 1 , further comprising a DC source which outputs the initial DC voltage.
16. The converter circuit of claim 15 , wherein the DC source comprises a thermoelectric generator, a battery, or a PV cell.
17. The converter circuit of claim 1 , further comprising a load.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 18, 2020
May 24, 2022
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