Semiconductor packages and forming methods thereof

1. A semiconductor package, comprising: a redistribution layer structure, having a first side and a second side opposite to the first side; a first semiconductor chip, electrically connected to the first side of the redistribution layer structure; a circuit board structure, disposed over and electrically connected to the first side of the redistribution layer structure, wherein the circuit board structure comprises a first mask layer having an opening pattern corresponding to the first semiconductor chip; and an encapsulation layer, laterally encapsulating a sidewall of the circuit board structure and filling in a vertical space between the first semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.

2. The semiconductor package of claim 1 , wherein the opening pattern of the first mask layer comprises a main pattern, and a width of the main pattern is greater than a width of the first semiconductor chip.

3. The semiconductor package of claim 2 , wherein the opening pattern of the first mask layer further comprises a plurality of channel patterns, and each of the plurality of channel patterns extends outwardly from the main pattern.

4. The semiconductor package of claim 3 , wherein each of the plurality of channel patterns is located in a pattern-sparse region of the first mask layer.

5. The semiconductor package of claim 1 , wherein the first semiconductor chip is a passive integrated device.

6. The semiconductor package of claim 1 , wherein the circuit board structure is bonded to the redistribution layer structure through a plurality of first bumps.

7. The semiconductor package of claim 6 , wherein the first mask layer surrounds portions of the first bumps.

8. The semiconductor package of claim 1 , further comprising a second semiconductor chip electrically connected to the second side of the redistribution layer structure.

9. The semiconductor package of claim 8 , wherein the second semiconductor chip is an active integrated device.

10. A semiconductor package, comprising: a circuit board structure, disposed over a first side of the redistribution layer structure and comprising a first mask layer facing the first side of the redistribution layer structure; and a first semiconductor chip, disposed between the first mask layer of the circuit board structure and the redistribution layer, wherein a projection area of an opening pattern of the first mask layer on the first side of the redistribution layer structure is greater than a projection area of the first semiconductor chip on the first side of the redistribution layer structure, wherein the opening pattern of the first mask layer comprises a main pattern corresponding to the first semiconductor chip and a plurality of channel patterns extending outwardly from the main pattern.

11. The semiconductor package of claim 10 , wherein the circuit board structure further comprises a plurality of first bumps penetrating through the first mask layer and bonded to the first side of the redistribution layer structure.

12. The semiconductor package of claim 10 , wherein each of the plurality of channel patterns is located in a pattern-sparse region of the first mask layer.

13. The semiconductor package of claim 10 , wherein the circuit board structure further comprises a core layer and a first build-up layer and a second build-up layer disposed on opposite sides of the core layer, the first mask layer is disposed on the first build-up layer, and the opening pattern of the first mask layer does not expose the first build-up layer.

14. The semiconductor package of claim 10 , wherein the circuit board structure further comprises a core layer and a first build-up layer and a second build-up layer disposed on opposite sides of the core layer, the first mask layer is disposed on the first build-up layer, and the opening pattern of the first mask layer exposes the first build-up layer.

15. The semiconductor package of claim 10 , wherein a vertical distance from a surface of the opening pattern of the first mask layer to a surface of the first semiconductor chip is about 65 nm or more.

16. The semiconductor package of claim 10 , wherein a horizontal distance from an edge of opening pattern of the first mask layer to an edge of the first semiconductor chip is about 50 nm or more.

17. The semiconductor package of claim 10 , further comprising an encapsulation layer disposed over the first side of the redistribution layer structure and aside the first semiconductor chip and the circuit board structure.

18. A method of forming a semiconductor package, comprising: forming a redistribution layer structure over a carrier; bonding a first semiconductor chip to a first side of the redistribution layer structure; providing a circuit board structure, wherein the circuit board structure comprises a first mask layer with an opening pattern therein; bonding the circuit board structure to the first side of the redistribution layer structure with the opening pattern of the first mask layer corresponding to the first semiconductor chip, wherein the opening pattern of the first mask layer comprises a main pattern corresponding to the first semiconductor chip and a plurality of channel patterns extending outwardly from the main pattern; and forming an encapsulation layer to fill a space between the circuit board structure and each of the first semiconductor chip and the redistribution layer structure.

19. The method of claim 18 , wherein the opening pattern of the first mask layer comprises a main pattern over corresponding to the first semiconductor chip and a plurality of channel patterns extending outwardly from the main pattern.

20. The method of claim 18 , further comprising: releasing the carrier from the redistribution layer structure; and bonding a second semiconductor chip to a second side of the redistribution layer structure opposite to the first side.