Apparatuses and techniques are described for avoiding current consumption peaks during a program operation for a memory device. The timing of scan operations of latches is adjusted to avoid overlapping with an increase in word line voltages. The scan operations can include a pre-charge select scan, which identifies memory cells subject to a verify test, and a fill operation for latches of memory cells which fail a verify test in a prior program loop. The pre-charge select scan can occur before the increase in the word line voltages, while the fill operation occurs after the increase in word line voltages. In another approach, the start of the increase in the word line voltages is delayed when a state bit scan is expected to take a relatively long time, e.g., when a verify test is passed in a prior program loop.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus, comprising: a control circuit configured to connect to a set of memory cells, the set of memory cells are arranged in NAND strings and connected to a set of word lines, each NAND string is connected to respective latches, and the control circuit, to perform a program operation for the set of memory cells, is configured to: apply a program pulse to a selected word line of the set of word lines in a current program loop of the program operation; and in connection with a verify test in the current program loop which follows the applying of the program pulse, perform a pre-charge select scan of the latches to identify memory cells subject to the verify test in the current program loop, increase a bit line voltage to a sense voltage for the identified memory cells subject to the verify test, and increase voltages of unselected word lines of the set of word lines from an initial level to a read pass level for the verify test, the pre-charge select scan is timed to not overlap with the increasing of the voltages of the unselected word lines from the initial level to the read pass level.
2. The apparatus of claim 1 , wherein: the control circuit is configured to perform a verify test of a data state in a prior program loop which is before the current program loop, and during the current program loop, perform a state bit scan of the latches to determine whether the data state passes the verify test of the prior program loop, and set a start time for the increasing of the voltages of the unselected word lines from the initial level to the read pass level as a function of whether the data state passes the verify test of the prior program loop.
3. The apparatus of claim 2 , wherein: the start time is later when the data state passes the verify test of the prior program loop than when the data state does not pass the verify test.
4. The apparatus of claim 1 , wherein: the control circuit is configured to perform a verify test for a data state in a prior program loop which is before the current program loop, and during the current program loop, perform a state bit scan of the latches to determine whether the data state passes the verify test of the prior program loop, the data state passes the verify test of the prior program loop when a number of memory cells which fail the verify test is less than a threshold number, and to perform a fill operation for latches for the memory cells which fail the verify test to indicate that their programming is completed; when the data state passes the verify test of the prior program loop, the pre-charge select scan is performed before the increasing of the voltages of the unselected word lines from the initial level to the read pass level and the fill operation is performed after the increasing of the voltages of the unselected word lines from the initial level to the read pass level; and when the data state does not pass the verify test of the prior program loop, the pre-charge select scan and the fill operation are performed before the increasing of the voltages of the unselected word lines from the initial level to the read pass level.
5. The apparatus of claim 1 , wherein: the control circuit is configured to perform a verify test for a data state in a prior program loop which is before the current program loop, and during the current program loop, perform a state bit scan to determine that the data state passes the verify test of the prior program loop, the data state passes the verify test of the prior program loop when a number of memory cells which fail the verify test is less than a threshold number, and to perform a fill operation for latches of the memory cells which fail the verify test to indicate that their programming is completed.
6. The apparatus of claim 5 , wherein: the fill operation is timed to not overlap with the increasing of the voltages of the unselected word lines from the initial level to the read pass level.
7. The apparatus of claim 5 , wherein: the state bit scan is timed to not overlap with the increasing of the voltages of the unselected word lines from the initial level to the read pass level.
8. The apparatus of claim 5 , wherein: the pre-charge select scan is performed prior to the increasing of the voltages of the unselected word lines from the initial level to the read pass level, and the fill operation is performed after the increasing of the voltages of the unselected word lines from the initial level to the read pass level.
9. A method, comprising: applying a program pulse to a selected word line of a set of word lines in a current program loop of a program operation, the set of word lines are connected to a set of memory cells, the set of memory cells are arranged in NAND strings and each NAND string is connected to respective latches; preparing for a verify test in the current program loop which follows the applying of the program pulse, the preparing for the verify test comprises performing a pre-charge select scan of the latches to identify memory cells subject to the verify test in the current program loop, increasing a bit line voltage to a sense voltage for the identified memory cells subject to the verify test, and increasing voltages of unselected word lines of the set of word lines from an initial level to a read pass level, the pre-charge select scan is timed to not overlap with the increasing of the voltages of the unselected word lines from the initial level to the read pass level; and performing the verify test while the bit line voltage is at the sense voltage for the identified memory cells subject to the verify test and the voltages of the unselected word lines of the set of word lines are at the read pass level.
10. The method of claim 9 , further comprising: performing a verify test of a data state in a prior program loop which is before the current program loop; during the current program loop, perform a state bit scan of the latches to determine whether the data state passes the verify test of the prior program loop; and delay the increasing of the voltages of unselected word lines of the set of word lines from the initial level to the read pass level when the data state passes the verify test of the prior program loop.
11. The method of claim 10 , wherein: the delay is sufficiently long to prevent the pre-charge select scan from overlapping with the increasing of the voltages of the unselected word lines from the initial level to the read pass level.
12. The method of claim 10 , wherein the data state passes the verify test of the prior program loop when a number of memory cells which fail the verify test is less than a threshold number, the method further comprising, when the data state passes the verify test of the prior program loop, performing a fill operation for latches of the memory cells which fail the verify test to indicate that their programming is completed.
13. The method of claim 12 , further comprising: timing the fill operation to not overlap with the increasing of the voltages of the unselected word lines from the initial level to the read pass level.
14. The method of claim 12 , further comprising: performing the pre-charge select scan prior to the increasing of the voltages of the unselected word lines from the initial level to the read pass level; and performing the fill operation after the increasing of the voltages of the unselected word lines from the initial level to the read pass level.
15. An apparatus, comprising: a control circuit configured to connect to a set of memory cells, the set of memory cells are arranged in NAND strings and connected to a set of word lines, each NAND string is connected to respective latches, and the set of memory cells are configured to be programmed to a plurality of data states; a memory interface connected to the control circuit, the control circuit is configured to issue a command via the memory interface to: perform a verify test of a data state in a prior program loop which is before a current program loop; in the current program loop, perform a state bit scan to determine whether the data state passes the verify test of the prior program loop; in the current program loop, increase voltages of unselected word lines of the set of word lines from an initial level to a read pass level in connection with a verify test of a data state in the current program loop; and set a start time for the increasing of the voltages of the unselected word lines of the set of word lines from the initial level to the read pass level as a function of whether the data state passes the verify test of the prior program loop.
16. The apparatus of claim 15 , wherein: the start time is later when the data state passes the verify test of the prior program loop than when the data state does not pass the verify test.
17. The apparatus of claim 15 , wherein: the data state passes the verify test of the prior program loop when a number of memory cells which fail the verify test is less than a threshold number, and the control circuit is configured to issue a command via the memory interface to perform a fill operation for latches of memory cells which fail the verify test to indicate that their programming is completed, the fill operation is timed to not overlap with the increasing of the voltages of the unselected word lines from the initial level to the read pass level.
18. The apparatus of claim 17 , wherein the control circuit is configured to issue a command via the memory interface to: in the current program loop, perform a pre-charge select scan of the latches to identify memory cells subject to the verify test in the current program loop, the pre-charge select scan is timed to not overlap with the increasing of the voltages of the unselected word lines from the initial level to the read pass level.
19. The apparatus of claim 18 , wherein: the fill operation occurs before the pre-charge select scan, and the pre-charge select scan occurs before the start time.
20. The apparatus of claim 18 , wherein: the control circuit is configured to issue a command via the memory interface to increase a bit line voltage to a sense voltage for the identified memory cells subject to the verify test in the current program loop.
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March 1, 2021
June 14, 2022
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