Patentable/Patents/US-11363290
US-11363290

Block size restrictions for DMVR

PublishedJune 14, 2022
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

Methods of enabling and disabling a decoder-side motion vector refinement (DMVR) video decoder and/or encoder are described. One example method includes determining a width (W) and a height (H) of a video block, making a determination, based on a condition of the video block, between enabling and disabling a decoder side motion vector refinement step for a conversion between the video block and a coded representation of the video block, in a case that the determination is enabling, performing the conversion by enabling the decoder side motion vector refinement step; and in a case that the determination is disabling, performing the conversion by disabling the decoder side motion vector refinement step, wherein the decoder side motion vector refinement step includes refining value of a motion vector signaled in the coded representation and using the refined value during the conversion.

Patent Claims
20 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method of video processing, comprising: performing a conversion between a video block and a bitstream of the video block based on at least one of a width and a height of the video block; refraining from applying, in response to a ratio of the width to the height (W/H) being smaller than a first threshold value, a decoder side motion vector refinement step during the conversion; and refraining from applying, in response to the ratio of the width to the height (W/H) being greater than a second threshold value, the decoder side motion vector refinement step during the conversion, wherein W and H are the width and the height of the video block, respectively, and wherein the decoder side motion vector refinement step includes refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion, wherein the decoder side motion vector refinement step is determined to be disabled when W<=T1 or H<=T2, wherein T1 is a third threshold and equal to 4 and T2 is a fourth threshold and equal to 4.

2

2. The method of claim 1 , wherein the conversion includes decoding the bitstream into pixel values of the video block.

3

3. The method of claim 1 , wherein the conversion includes encoding pixel values of the video block into the bitstream.

4

4. The method of claim 1 , wherein the decoder side motion vector refinement step is determined to be disabled when W<=T1 and H<=T2.

5

5. The method of claim 1 , wherein the decoder side motion vector refinement step is determined to be disabled when W*H<=T0, wherein T0 is a fifth threshold and T0 is an integer value greater than or equal to 1.

6

6. The method of claim 1 , wherein the decoder side motion vector refinement step is determined to be disabled when W=4 and H=4.

7

7. The method of claim 1 , wherein the decoder side motion vector refinement step is determined to be disabled when W=4 or H=4.

8

8. The method of claim 1 , wherein the first threshold value and the second threshold value have fixed values.

9

9. The method of claim 1 , wherein the second threshold value is equal to 8.

10

10. The method of claim 1 , wherein in response to an affine mode being applied to the current block, the decoder side motion vector refinement step is refrained from the current block.

11

11. An apparatus for coding video data comprising a processor and a non-transitory memory with instructions thereon, wherein the instructions upon execution by the processor, cause the processor to: perform a conversion between a video block and a bitstream of the video block based on at least one of a width and a height of the video block; refrain from applying, in response to a ratio of the width to the height (W/H) being smaller than a first threshold value, a decoder side motion vector refinement step during the conversion; and refrain from applying, in response to the ratio of the width to the height (W/H) being greater than a second threshold value, the decoder side motion vector refinement step during the conversion, wherein W and H are the width and the height of the video block, respectively, and wherein the decoder side motion vector refinement step includes refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion, wherein the decoder side motion vector refinement step is determined to be disabled when W<=T1 or H<=T2, wherein T1 is a third threshold and equal to 4 and T2 is a fourth threshold and equal to 4.

12

12. The apparatus of claim 11 , wherein the conversion includes decoding the bitstream into pixel values of the video block.

13

13. The apparatus of claim 11 , wherein the conversion includes encoding pixel values of the video block into the bitstream.

14

14. The apparatus of claim 11 , wherein the decoder side motion vector refinement step is determined to be disabled when W<=T1 and H<=T2.

15

15. The apparatus of claim 11 , wherein the decoder side motion vector refinement step is determined to be disabled when W*H<=T0, wherein T0 is a fifth threshold and T0 is an integer value greater than or equal to 1.

16

16. The apparatus of claim 11 , wherein the decoder side motion vector refinement step is determined to be disabled when W=4 and H=4.

17

17. The apparatus of claim 11 , wherein the decoder side motion vector refinement step is determined to be disabled when W=4 or H=4.

18

18. A non-transitory computer-readable storage medium storing instructions that cause a processor to: perform a conversion between a video block and a bitstream of the video block based on at least one of a width and a height of the video block; refrain from applying, in response to a ratio of the width to the height (W/H) being smaller than a first threshold value, a decoder side motion vector refinement step during the conversion; and refrain from applying, in response to the ratio of the width to the height (W/H) being greater than a second threshold value, the decoder side motion vector refinement step during the conversion, wherein W and H are the width and the height of the video block, respectively, and wherein the decoder side motion vector refinement step includes refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion, wherein the decoder side motion vector refinement step is determined to be disabled when W<=T1 or H<=T2, wherein T1 is a third threshold and equal to 4 and T2 is a fourth threshold and equal to 4.

19

19. The non-transitory computer-readable storage medium of claim 18 , wherein the decoder side motion vector refinement step is determined to be disabled in at least one of the following conditions: when W<=T1 and H<=T2; when W*H<=T0, wherein T0 is a fifth threshold and T0 is an integer value greater than or equal to 1; when W=4 and H=4; or when W=4 or H=4.

20

20. A non-transitory computer-readable storage medium storing a bitstream of a video which is generated by a method performed by a video processing apparatus, wherein the method comprises: generating the bitstream based on at least one of a width and a height of the video block; refrain from applying, in response to a ratio of the width to the height (W/H) being smaller than a first threshold value, a decoder side motion vector refinement step during the conversion; and refrain from applying, in response to the ratio of the width to the height (W/H) being greater than a second threshold value, the decoder side motion vector refinement step during the conversion, wherein W and H are the width and the height of the video block, respectively, and wherein the decoder side motion vector refinement step includes refining a value of a motion vector signaled in the bitstream and using the refined value during the conversion, wherein the decoder side motion vector refinement step is determined to be disabled when W<=T1 or H<=T2, wherein T1 is a third threshold and equal to 4 and T2 is a fourth threshold and equal to 4.

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Patent Metadata

Filing Date

August 20, 2020

Publication Date

June 14, 2022

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Cite as: Patentable. “Block size restrictions for DMVR” (US-11363290). https://patentable.app/patents/US-11363290

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