Included are: a semiconductor layer including a drain region, a channel region, and a second LDD region between the drain region and the channel region; a gate electrode disposed overlapping the channel region; a gate wiring line electrically coupled to the gate electrode; and a second light shielding portion disposed between the second LDD region and the gate wiring line and overlapping the second LDD region and the gate wiring line in plan view.
Legal claims defining the scope of protection, as filed with the USPTO.
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June 15, 2021
June 28, 2022
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