Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating a back end of line (BEOL) metallization layer for a semiconductor structure, the method comprising: forming an inter-layer dielectric (ILD) layer above a substrate; forming a first plurality of photobuckets above the ILD layer, the first plurality of photobuckets defining all possible dielectric plug locations for the BEOL metallization layer; removing fewer than all of the first plurality of photobuckets and retaining one or more of the first plurality of photobuckets in select dielectric plug locations; forming a second plurality of photobuckets above the ILD layer, the second plurality of photobuckets defining all possible conductive tab locations for the BEOL metallization layer; removing fewer than all of the second plurality of photobuckets in select conductive tab locations and retaining one or more of the second plurality of photobuckets; subsequent to removing fewer than all of the first plurality of photobuckets and removing fewer than all of the second plurality of photobuckets, transferring an image including the select dielectric plug locations and the select conductive tab locations to the ILD layer; and forming a plurality of conductive lines, one or more dielectric plugs, and one or more conductive tabs in the ILD layer.
2. The method of claim 1 , wherein the first and second pluralities of photobuckets are formed in a two-dimensional hardmask grating structure formed above the ILD layer.
3. The method of claim 2 , further comprising: performing a tone reversal process operation between forming the first and second pluralities of photobuckets.
4. The method of claim 1 , wherein the first and second pluralities of photobuckets are formed in a one-dimensional hardmask grating structure formed above the ILD layer.
5. The method of claim 4 , wherein forming the one or more dielectric plugs comprises forming a same dielectric material as the ILD layer.
6. The method of claim 5 , wherein the one or more dielectric plugs are continuous with the ILD layer.
7. The method of claim 5 , wherein forming the one or more dielectric plugs comprises forming a different dielectric material from the ILD layer.
8. The method of claim 1 , wherein forming the one or more conductive tabs comprises forming the one or more conductive tabs continuous with the plurality of conductive lines.
9. A method of fabricating a back end of line (BEOL) metallization layer for a semiconductor structure, the method comprising: forming an inter-layer dielectric (ILD) layer above a substrate, the substrate having a top surface; forming a plurality of conductive lines in the ILD layer along a first direction, the plurality of conductive lines having a pitch of 20 nanometers or less, wherein each of the plurality of conductive lines has a longest dimension along the first direction, and wherein the longest dimension of each of the plurality of conductive lines is parallel with one another; and forming a conductive tab in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction, wherein the first direction and the second direction are parallel with the top surface of the substrate.
10. The method of claim 9 , wherein the conductive tab is continuous with the two of the plurality of conductive lines.
11. The method of claim 9 , wherein the conductive tab is co-planar with the two of the plurality of conductive lines.
12. The method of claim 9 , further comprising: forming a dielectric plug at an end of one of the plurality of conductive lines.
13. The method of claim 12 , wherein the dielectric plug is continuous with the ILD layer.
14. The method of claim 9 , further comprising: forming a conductive via above or below and electrically coupled to one of the plurality of conductive lines.
15. A method of fabricating a back end of line (BEOL) metallization layer for a semiconductor structure, the method comprising: forming an inter-layer dielectric (ILD) layer above a substrate, the substrate having a top surface; forming a plurality of conductive lines in the ILD layer along a first direction, the plurality of conductive lines each having a width of 10 nanometers or less, wherein each of the plurality of conductive lines has a longest dimension along the first direction, and wherein the longest dimension of each of the plurality of conductive lines is parallel with one another; and forming a conductive tab in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction, wherein the first direction and the second direction are parallel with the top surface of the substrate.
16. The method of claim 15 , wherein the conductive tab is continuous with the two of the plurality of conductive lines.
17. The method of claim 15 , wherein the conductive tab is co-planar with the two of the plurality of conductive lines.
18. The method of claim 15 , further comprising: forming a dielectric plug at an end of one of the plurality of conductive lines.
19. The method of claim 18 , wherein the dielectric plug is continuous with the ILD layer.
20. The method of claim 15 , further comprising: forming a conductive via above or below and electrically coupled to one of the plurality of conductive lines.
21. A method of fabricating a computing device, the method comprising: providing a board; and coupling a component to the board, the component including an integrated circuit structure, comprising: an inter-layer dielectric (ILD) layer disposed above a substrate, the substrate having a top surface; a plurality of conductive lines disposed in the ILD layer along a first direction, the plurality of conductive lines having a pitch of 20 nanometers or less, wherein each of the plurality of conductive lines has a longest dimension along the first direction, and wherein the longest dimension of each of the plurality of conductive lines is parallel with one another; and a conductive tab disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction, wherein the first direction and the second direction are parallel with the top surface of the substrate.
22. The method of claim 21 , the method further comprising: coupling a memory to the board.
23. The method of claim 21 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
24. The method of claim 21 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.
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September 18, 2020
June 28, 2022
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