Systems and methods for evaluating critical dimensions of a semiconductor device are provided. The semiconductor device includes a first layer comprising a first set of overlay markings and a second layer comprising a second set of overlay markings. The second layer is higher than the first layer. The first set of overlay markings includes a plurality of diffraction gratings. Each of the plurality of diffraction gratings has a first period. The second set of overlay markings includes a plurality diffraction grating clusters. Each of the plurality of diffraction grating clusters has a plurality of diffraction grating units. The plurality of diffraction grating units in at least one of the plurality of diffraction grating clusters have the first period. At least one of the plurality of diffraction grating units includes a diffraction grating having a second period that is smaller than the first period.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a first layer comprising a first set of overlay markings; and a second layer comprising a second set of overlay markings, the second layer being higher than the first layer, wherein: the first set of overlay markings comprises a plurality of diffraction gratings, each of the plurality of diffraction gratings having a first period; the second set of overlay markings comprises a plurality of diffraction grating clusters, each of the plurality of diffraction grating clusters having a plurality of diffraction grating units, wherein the plurality of diffraction grating units in at least one of the plurality of diffraction grating clusters have the first period and at least one of the plurality of diffraction grating units comprises a plurality of diffraction gratings having a second period that is smaller than the first period; and a first longitudinal-axis associated with a first diffraction grating of a first diffraction grating unit is oriented parallel to a second longitudinal-axis associated with the first diffraction grating unit and a third longitudinal-axis associated with a second diffraction grating of a second diffraction grating unit is oriented perpendicular to a fourth longitudinal-axis associated with the second diffraction grating unit.
2. The semiconductor device of claim 1 , wherein the plurality of diffraction gratings comprise a first group of diffraction gratings oriented in a first direction and a second group of diffraction gratings oriented in a second direction perpendicular to the first direction.
3. The semiconductor device of claim 2 , wherein at least two diffraction gratings in the first group or the second group are diagonally disposed with respect to each other.
4. The semiconductor device of claim 1 , wherein the first period is in a range between 500 nanometers to 10 micrometers.
5. The semiconductor device of claim 1 , wherein the second period is substantially the same as a structural period of an anchor pattern on the second layer.
6. The semiconductor device of claim 1 , wherein the plurality of diffraction gratings having the second period comprise linear structures.
7. The semiconductor device of claim 1 , wherein the plurality of diffraction gratings having the second period comprises comprise non-linear structures.
8. The semiconductor device of claim 1 , wherein the second period is in a range between 1 nanometer to 500 nanometers.
9. The semiconductor device of claim 1 , wherein the plurality of diffraction gratings having the second period are symmetrically arranged with respect to a geometrical center of a corresponding diffraction grating unit.
10. The semiconductor device of claim 1 , wherein the plurality of diffraction gratings having the second period have a same orientation as the at least one of the plurality of diffraction grating units.
11. The semiconductor device of claim 1 , wherein the plurality of diffraction gratings having the second period have an orientation perpendicular to the at least one of the plurality of diffraction grating units.
12. The semiconductor device of claim 1 , wherein at least one diffraction grating cluster in the second set of overlay markings misaligns with a corresponding diffraction grating in the first set of overlay markings by a predetermined offset.
13. The semiconductor device of claim 1 , wherein the first set of overlay markings and second set of overlay markings comprise at least one of a positive grating structure or a negative grating structure.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 19, 2021
July 5, 2022
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.