In some embodiments, the present disclosure relates to an integrated chip that includes a substrate and a gate electrode overlying the substrate. Further, the integrated chip includes a contact layer overlies the substrate and is laterally spaced apart from the gate electrode by a spacer structure. The spacer structure may surround outermost sidewalls of the gate electrode. A hard mask structure may be arranged over the gate electrode and between portions of the spacer structure. A contact via extends through the hard mask structure and contacts the gate electrode. The integrated chip may further include a liner layer that is arranged directly between the hard mask structure and the spacer structure, wherein the liner layer is spaced apart from the gate electrode.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated chip comprising: a substrate; a gate electrode overlying the substrate; a contact layer overlying the substrate and laterally spaced from the gate electrode; a spacer structure surrounding outermost sidewalls of the gate electrode and separating the gate electrode from the contact layer; a hard mask structure arranged over the gate electrode; a contact via extending through the hard mask structure and contacting the gate electrode; and a liner layer arranged directly between the hard mask structure and the spacer structure, wherein the contact via has a bottommost surface that has a larger width than a part of the contact via that is directly between sidewalls of the liner layer.
2. The integrated chip of claim 1 , wherein the liner layer comprises a material having a higher dielectric constant than a material of the spacer structure.
3. The integrated chip of claim 1 , wherein the contact via is directly and vertically between a bottommost surface of the liner layer and a top surface of the gate electrode.
4. The integrated chip of claim 1 , wherein a first bottom surface of the liner layer is spaced apart from the gate electrode by the hard mask structure, and wherein a second bottom surface of the liner layer is spaced apart from the gate electrode by the contact via.
5. The integrated chip of claim 1 , wherein the contact via has a middle portion arranged between and directly contacting inner sidewalls of the liner layer, wherein the contact via has a bottom portion arranged between and directly contacting inner sidewalls of the spacer structure, wherein the middle portion has a first width, wherein the bottom portion has a second width, and wherein the first width is less than the second width.
6. The integrated chip of claim 1 , wherein the contact via directly overlies a first portion of the spacer structure.
7. The integrated chip of claim 6 , wherein the first portion of the spacer structure has a varying thickness throughout its height, and wherein a topmost surface of the first portion of the spacer structure is thinner than a bottommost surface of the first portion of the spacer structure.
8. An integrated chip comprising: a substrate comprising a source/drain region; a contact layer arranged over the source/drain region; a gate electrode arranged over the substrate and laterally spaced from the contact layer; a hard mask structure arranged over the gate electrode; a contact via extending through the hard mask structure and arranged over and directly contacting an upper surface of the gate electrode; a spacer structure arranged directly between the gate electrode and the contact layer; and a liner layer contacting inner sidewalls of the spacer structure, wherein the liner layer comprises a material with a higher dielectric constant than a material of the spacer structure.
9. The integrated chip of claim 8 , wherein the material of the liner layer has a higher dielectric constant than a material of the hard mask structure.
10. The integrated chip of claim 8 , wherein the liner layer has a first portion arranged on a first side of the contact via and a second portion arranged on a second side of the contact via, and wherein the first portion is completely spaced apart from the second portion.
11. The integrated chip of claim 10 , wherein the first portion of the liner layer has a first bottom surface spaced apart from the gate electrode by the contact via.
12. The integrated chip of claim 10 , wherein the second portion of the liner layer has a bottom surface that is completely spaced apart from the gate electrode by the hard mask structure.
13. The integrated chip of claim 10 , wherein the contact via directly separates the first and second portions of the liner layer from the gate electrode.
14. The integrated chip of claim 8 , wherein the contact via directly contacts a first topmost surface of the spacer structure, and wherein the spacer structure has a thickness that is substantially uniform throughout its height.
15. An integrated chip comprising: a substrate; a gate electrode overlying the substrate; a contact layer overlying the substrate and laterally spaced from the gate electrode; a spacer structure surrounding outermost sidewalls of the gate electrode and separating the gate electrode from the contact layer; a hard mask structure arranged over the gate electrode and between portions of the spacer structure; and a liner layer arranged directly between the hard mask structure and the spacer structure, wherein a bottommost surface of the hard mask structure is arranged below a bottommost surface of the liner layer.
16. The integrated chip of claim 15 , wherein the liner layer comprises a material with a higher dielectric constant than a material of the spacer structure.
17. The integrated chip of claim 15 , wherein the hard mask structure separates the bottommost surface of the liner layer from the gate electrode.
18. The integrated chip of claim 15 , further comprising: a contact via extending through the hard mask structure and arranged over and directly contacting an upper surface of the gate electrode.
19. The integrated chip of claim 18 , wherein the contact via separates the bottommost surface of the liner layer from the upper surface of the gate electrode.
20. The integrated chip of claim 18 , wherein the contact via directly contacts the spacer structure.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 18, 2020
July 12, 2022
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