Semiconductor package

1. A semiconductor package comprising: a base chip; a first semiconductor chip disposed on the base chip; a second semiconductor chip disposed on the first semiconductor chip; a first insulating layer disposed between the base chip and the first semiconductor chip; a second insulating layer disposed between the first semiconductor chip and the second semiconductor chip; a first connection bump penetrating through the first insulating layer and connecting the base chip and the first semiconductor chip to each other; and a second connection bump penetrating through the second insulating layer and connecting the first semiconductor chip and the second semiconductor chip to each other, wherein the base chip has a width greater than a width of each of the first and second semiconductor chips, and the first insulating layer and the second insulating layer include different materials from each other.

2. The semiconductor package of claim 1 , wherein the first insulating layer is a silicon oxide layer, and the second insulating layer is a non-conductive film (NCF).

3. The semiconductor package of claim 1 , wherein the first insulating layer has a side surface coplanar with a side surface of the first semiconductor chip, and the second insulating layer has a side surface protruding further outwardly than the side surface of the first semiconductor chip and a side surface of the second semiconductor chip.

4. The semiconductor package of claim 1 , wherein the first semiconductor chip has the same width as the second semiconductor chip.

5. The semiconductor package of claim 1 , wherein the base chip includes a base body, a base upper connection pad disposed on an upper surface of the base body, and a base through-electrode penetrating through the base body and connected to the base upper connection pad, the first semiconductor chip includes a first chip body, a first lower connection pad and a first upper connection pad, respectively disposed on a lower surface and an upper surface of the first chip body, and a first through-electrode penetrating through the first chip body and connecting the first lower connection pad and the first upper connection pad to each other, the second semiconductor chip includes a second chip body, a second lower connection pad and a second upper connection pad, respectively disposed on a lower surface and an upper surface of the second chip body, and a second through-electrode penetrating through the second chip body and connecting the second lower connection pad and the second upper connection pad to each other, the first connection bump connects the base upper connection pad and the first lower connection pad to each other, and the second connection bump connects the first upper connection pad and the second lower connection pad to each other.

6. The semiconductor package of claim 5 , further comprising at least one other base upper connection pad such that a plurality of base upper connection pads spaced apart from each other are present in the base chip, and at least one other first lower connection pad such that a plurality of first lower connection pads spaced apart from each other are present in the first semiconductor chip, further comprising at least one other first connection bump such that a plurality of first connection bumps are present in the first insulating layer, respectively corresponding to the plurality of base upper connection pads and the plurality of first lower connection pads, and wherein a pitch between the plurality of first connection bumps is 10 micrometers or less.

7. The semiconductor package of claim 5 , wherein the lower surface of the first chip body is coplanar with a lower surface of the first lower connection pad, the upper surface of the first chip body is coplanar with an upper surface of the first upper connection pad, the lower surface of the second chip body is coplanar with a lower surface of the second lower connection pad, and the upper surface of the second chip body is coplanar with an upper surface of the second upper connection pad.

8. The semiconductor package of claim 1 , further comprising at least one other first semiconductor chip such that a plurality of first semiconductor chips are stacked on top of each other in a direction perpendicular to an upper surface of the base chip, further comprising at least one other second semiconductor chip such that a plurality of second semiconductor chips are stacked on top of each other in a direction perpendicular to an upper surface of the first semiconductor chip, the first insulating layer further includes one or more first insulating layers, each being disposed between the plurality of first semiconductor chips, the second insulating layer further includes one or more second insulating layers, each being disposed between the plurality of second semiconductor chips, and the number of the plurality of first semiconductor chips is smaller than the number of the plurality of second semiconductor chips.

9. The semiconductor package of claim 1 , wherein the first insulating layer has the same width as the first semiconductor chip, and the second insulating layer has a width greater than a width of the first semiconductor chip.

10. The semiconductor package of claim 1 , wherein the first connection bump includes a conductive pillar, and the second connection bump includes a solder ball.

11. The semiconductor package of claim 1 , further comprising: an encapsulant covering an upper surface of the base chip and side surfaces of each of the first and second semiconductor chips.

12. The semiconductor package of claim 11 , wherein the encapsulant has a side surface coplanar with a side surface of the base chip.

13. The semiconductor package of claim 1 , further comprising: a third semiconductor chip disposed on the second semiconductor chip; a third insulating layer disposed between the second semiconductor chip and the third semiconductor chip; and a third connection bump penetrating through the third insulating layer and connecting the second semiconductor chip and the third semiconductor chip to each other.

14. The semiconductor package of claim 13 , further comprising: an encapsulant covering an upper surface of the base chip and side surfaces of each of the second and third semiconductor chips.

15. The semiconductor package of claim 14 , wherein the third semiconductor chip has an upper surface exposed via an opening in the encapsulant.

16. A semiconductor package comprising: a base chip; a first semiconductor chip disposed on the base chip; a plurality of second semiconductor chips stacked on top of each other on the first semiconductor chip in a direction perpendicular to an upper surface of the first semiconductor chip; a first insulating layer between the base chip and the first semiconductor chip; a plurality of second insulating layers on a lower surface of each of the plurality of second semiconductor chips; a first connection bump penetrating through the first insulating layer and electrically connecting the base chip and the first semiconductor chip to each other; and a plurality of second connection bumps, respectively penetrating through the plurality of second insulating layers, and electrically connecting the first semiconductor chip and the plurality of second semiconductor chips to each other, wherein the first insulating layer has the same width as the first semiconductor chip, wherein each of the plurality of second insulating layers has a width greater than the width of the first semiconductor chip, and wherein the first insulating layer and the second insulating layer include different materials from each other.

17. The semiconductor package of claim 16 , further comprising: a third semiconductor chip disposed on an uppermost second semiconductor chip among the plurality of second semiconductor chips; a third insulating layer disposed between the uppermost second semiconductor chip and the third semiconductor chip; and a third connection bump penetrating through the third insulating layer and electrically connecting the plurality of second semiconductor chips and the third semiconductor chip.

18. The semiconductor package of claim 17 , wherein the first insulating layer is a silicon oxide layer, and the second insulating layer and the third insulating layer are non-conductive films.

19. The semiconductor package of claim 17 , wherein each of the first connection bump, the second connection bump, and the third connection bump includes a conductive pillar.

20. A semiconductor package comprising: a base chip including a base body, a base upper connection pad disposed on an upper surface of the base body, and a base through-electrode penetrating through the base body and connected to the base upper connection pad; a plurality of first semiconductor chips, disposed on the base chip, each including a first chip body, a first lower connection pad and a first upper connection pad, respectively disposed on a lower surface and an upper surface of each first chip body, and a first through-electrode penetrating through the first chip body and connecting the first lower connection pad and the first upper connection pad to each other, the plurality of first semiconductor chips being stacked on top of each other in a direction perpendicular to an upper surface of the base chip; a plurality of second semiconductor chips, disposed on the plurality of first semiconductor chips, each including a second chip body, a second lower connection pad and a second upper connection pad, respectively disposed on a lower surface and an upper surface of the second chip body, and a second through-electrode penetrating through the second chip body and connecting the second lower connection pad and the second upper connection pad to each other, the plurality of second semiconductor chips being stacked on top of each other in a direction perpendicular to an upper surface of the first semiconductor chip; a plurality of first insulating layers disposed on a lower surface of each of the plurality of first semiconductor chips; a plurality of second insulating layers disposed on a lower surface of each of the plurality of second semiconductor chips; a plurality of first connection bumps, respectively penetrating through the plurality of first insulating layers, and connecting the first lower connection pad to the base upper connection pad or the first upper connection pad; and a plurality of second connection bumps, respectively penetrating through the plurality of second insulating layers, and connecting the second lower connection pad to the first upper connection pad or the second upper connection pad, wherein the number of the plurality of first semiconductor chips is smaller than the number of the plurality of second semiconductor chips, and the plurality of first insulating layers and the plurality of second insulating layers include different materials from each other.