A semiconductor device includes a first semiconductor die, a second semiconductor die, a dielectric layer, a first redistribution layer and a second redistribution layer. The first semiconductor die includes a first bonding pad and a second bonding pad. The second semiconductor die includes a third bonding pad and a fourth bonding pad. The dielectric layer covers the first semiconductor die and the second semiconductor die, and defines a first opening exposing the first bonding pad and the second bonding pad and a second opening exposing the third bonding pad and the fourth bonding pad. The first redistribution layer is disposed on the dielectric layer, and electrically connects the first bonding pad and the third bonding pad. The second redistribution layer is disposed on the dielectric layer, and electrically connects the second bonding pad and the fourth bonding pad.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor device of claim 1, wherein a portion of the first passivation layer is disposed in the first opening of the dielectric layer.
3. The semiconductor device of claim 2, wherein the first redistribution layer includes a first portion and a second portion, the first portion is disposed on the dielectric layer, and the second portion is disposed in the first opening and contacts the first bonding pad and the first passivation layer.
4. The semiconductor device of claim 3, wherein the first redistribution layer includes a third portion connecting the first portion and the second portion, and the third portion is disposed on a surface of the dielectric layer and a sidewall of the first opening.
5. The semiconductor device of claim 1, further comprising an encapsulant covering at least a portion of the first semiconductor die, at least a portion of the second semiconductor die and at least a portion of the dielectric layer.
6. The semiconductor device of claim 1, wherein the measurement opening exposes a portion of first passivation layer on the surface of the first semiconductor die.
7. The semiconductor device of claim 1, wherein the measurement opening is disposed at a position corresponding to an outside of the first semiconductor die.
8. The semiconductor device of claim 1, wherein a depth of the measurement opening is substantially equal to a depth of the first opening.
10. The semiconductor device of claim 9, wherein the measurement circuit includes an interdigitated structure.
11. The semiconductor device of claim 9, wherein the measurement circuit includes at least two conductive segments, and a gap between the conductive segments of the measurement circuit is substantially equal to or less than a gap between the first redistribution layer and the second redistribution layer on the dielectric layer.
12. The semiconductor device of claim 11, wherein the conductive segments of the measurement circuit are isolated from each other.
13. The semiconductor device of claim 9, wherein a portion of the first redistribution layer contacts a sidewall of the first opening, and a portion of the measurement circuit contacts a sidewall of the measurement opening.
14. The semiconductor device of claim 1, wherein the measurement opening exposes a portion of the dielectric layer.
15. The semiconductor device of claim 9, wherein the first redistribution layer, the second redistribution layer and the measurement circuit are formed concurrently.
16. The semiconductor device of claim 1, wherein extending directions of two ends of the first redistribution layer are different from each other, and extending directions of two ends of the second redistribution layer are different from each other, wherein the second redistribution layer is substantially parallel with the first redistribution layer, and a length of the second redistribution layer is substantially equal to a length of the first redistribution layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 30, 2019
August 2, 2022
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