A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor device of claim 1, further comprising an indent between adjacent ones of the plurality of epitaxy regions.
3. The semiconductor device of claim 2, wherein the indent is larger than the plurality of recesses.
4. The semiconductor device of claim 3, wherein a depth of each of the recesses is in a range from about 1.5 nm to about 3.5 nm.
5. The semiconductor device of claim 4, wherein a depth difference of the plurality of recesses is in a range from about 0.5 nm to about 3 nm.
6. The semiconductor device of claim 1, wherein the plurality of residues comprise argon, neon, krypton, or xenon.
7. The semiconductor device of claim 1, wherein the conductor comprises a silicide.
9. The semiconductor device of claim 8, further comprising an indent between the first upper facet and the second upper facet, wherein sidewalls of the indent comprise a first side facet extending from the first upper facet and a second side facet extending from the second upper facet.
10. The semiconductor device of claim 8, wherein the conductor comprises a silicide covering the plurality of residues.
11. The semiconductor device of claim 10, wherein the plurality of residues comprise argon, neon, krypton, or xenon.
12. The semiconductor device of claim 10, wherein a depth difference in the plurality of recesses at an interface between the merged epitaxy regions and the silicide is in a range from 1.5 nm to 3.5 nm.
13. The semiconductor device of claim 8, wherein a pattern of the plurality of recesses is irregular.
14. The semiconductor device of claim 8, wherein a depth difference of the plurality of recesses is in a range from about 0.5 nm to about 3 nm.
17. The semiconductor device of claim 16, wherein the first epitaxy structure is doped with p-type dopants, wherein the second epitaxy structure is doped with n-type dopants, wherein a depth difference of the plurality of first recesses is 2 nm to 20 nm higher than a depth difference of the plurality of second recesses.
18. The semiconductor device of claim 17, wherein the first epitaxy structure comprises SiGe and the second epitaxy structure comprises SiP.
19. The semiconductor device of claim 17, wherein the plurality of first residues and the plurality of second residues comprise argon, neon, krypton, or xenon.
20. The semiconductor device of claim 15, wherein the first continuous epitaxial region further comprises a third faceted surface and a fourth faceted surface interposed between the first faceted surface and the fourth faceted surface, wherein the third faceted surface intersects the fourth faceted surface to form an indent, wherein a depth of the indent is greater than a depth of the plurality of first recesses.
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December 7, 2020
August 2, 2022
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