A semiconductor device is provided. The device includes a memory that stores data in a non-volatile and volatile manner and a memory controller configured to control the memory. The memory includes a word line pair including a first and second word line, a first bit line pair orthogonal to the first and the second word line and including a first bit line and a first complementary bit line, and a memory cell pair including first and second memory cells adjacent to the first memory cell in a word line direction. A left node of the first memory cell, and a right node of the first memory cell and a left node of the second memory cell, are all connected to the first word line, and a value of the data stored in the memory cell pair in the non-volatile manner is determined according to the selected first word line.
Legal claims defining the scope of protection, as filed with the USPTO.
3. The semiconductor device of claim 2, wherein the read voltage corresponds to a power supply voltage and the read inhibit voltage corresponds to a ground supply voltage.
4. The semiconductor device of claim 2, wherein the memory controller is further configured to detect the value of the data stored in the memory cell pair in the non-volatile manner to be 1 when both of the voltage level of the first bit line and the voltage level of the first complementary bit line are greater than or equal to the threshold value.
5. The semiconductor device of claim 1, wherein each of the first memory cell and the second memory cell comprises a static random access memory (SRAM) cell.
6. The semiconductor device of claim 1, wherein each of the first memory cell and the second memory cell comprises a latch circuit including four transistors.
8. The semiconductor device of claim 7, wherein the right node of the first memory cell and the left node of the second memory cell are electrically connected to each other through the right connection transistor of the first memory cell and a left connection transistor of the second memory cell.
9. The semiconductor device of claim 8, wherein the right node of the first memory cell and the left node of the second memory cell are electrically connected to each other through a contact via formed between the gate region of the right connection transistor of the first memory cell and a gate region of the left connection transistor of the second memory cell.
12. The method of claim 11, wherein the first bit line and the first complementary bit line are orthogonal to the first word line and the second word line.
13. The method of claim 11, wherein the read voltage corresponds to a power supply voltage and the read inhibit voltage corresponds to a ground supply voltage.
14. The method of claim 11, wherein each of the first memory cell and a second memory cell comprises a static random access memory (SRAM) cell.
15. The method of claim 11, wherein each of the first memory cell and a second memory cell comprises a latch circuit including four transistors.
17. The method of claim 16, wherein the right node of the first memory cell and the left node of a second memory cell are electrically connected to each other through the right connection transistor of the first memory cell and a left connection transistor of the second memory cell.
19. The method of claim 11, wherein the detecting of the value of the data stored in the memory cell pair in the non-volatile manner to be 1 comprises performing an AND operation on a logic value of the first bit line and a logic value of the voltage level of the first complementary bit line.
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August 7, 2020
August 9, 2022
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