Patentable/Patents/US-11416163
US-11416163

Systems and methods for dynamic logical block address distribution between multicores

PublishedAugust 16, 2022
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A data processing system includes a host, a plurality of memory devices configured to operate in parallel and a controller including a host interface controller and a plurality of cores, which are respectively coupled to the plurality of memory devices. The controller splits a logical block address (LBA) range associated with each of the cores into a plurality of LBA groups. When it is detected that there is imbalance of workloads among the cores, the controller identifies first and second cores contributing to the imbalance of workloads and selects a first LBA group, among the range of LBAs of the first core, and selecting a second LBA group, among the range of LBAs of the second core. The controller transfers data associated with the first LBA group to the second LBA group and reroutes data initially intended for the first LBA group to the second LBA group.

Patent Claims
10 claims

Legal claims defining the scope of protection, as filed with the USPTO.

6

6. The data processing system of claim 5, wherein the controller is further configured to determine an average number of writes of the plurality of LBA groups among the plurality of cores.

7

7. The data processing system of claim 2, wherein the controller is further configured to change all LBAs of the first LBA group to all LBAs of the second LBA group by swapping all of the LBAs of the first LBA group with all of the LBAs of the second LBA group.

8

8. The data processing system of claim 2, wherein the controller is further configured to swap at least one LBA of the first LBA group with at least one LBA of the second LBA group to mix remaining LBAs of the first LBA group with the at least one LBA of the second LBA group and mix the at least one LBA of the first LBA group with remaining LBAs of the second LBA group.

9

9. The data processing system of claim 2, wherein the controller is further configured to split the respective LBA range for each of the plurality of cores into the plurality of LBA groups associated with the respective core based on a set pattern.

10

10. The data processing system of claim 9, wherein the set pattern is indicated by a pseudo-random sequence.

16

16. The method of claim 15, wherein the detecting of whether there is an imbalance of workloads further includes determining an average number of writes of the plurality of LBA groups among the plurality of cores.

17

17. The method of claim 12, wherein the rerouting of data initially intended for the first LBA group to the second LBA group includes changing all LBAs of the first LBA group to all LBAs of the second LBA group by swapping all of the LBAs of the first LBA group with all of the LBAs of the second LBA group.

18

18. The method of claim 12, wherein the rerouting of data initially intended for the first LBA group to the second LBA group includes swapping at least one LBA of the first LBA group with at least one LBA of the second LBA group to mix remaining LBAs of the first LBA group with the at least one LBA of the second LBA group and to mix the at least one LBA of the first LBA group with remaining LBAs of the second LBA group.

19

19. The method of claim 12, wherein the splitting of the respective LBA range for each of the plurality of cores includes splitting the respective LBA range for each of the plurality of cores into the plurality of LBA groups associated with the respective core based on a set pattern.

20

20. The method of claim 19, wherein the set pattern is indicated by a pseudo-random sequence.

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Patent Metadata

Filing Date

April 9, 2020

Publication Date

August 16, 2022

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Cite as: Patentable. “Systems and methods for dynamic logical block address distribution between multicores” (US-11416163). https://patentable.app/patents/US-11416163

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