A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor device of claim 1, wherein a maximum thickness of the etch stop pattern is less than a thickness of the etch stop layer, and wherein a maximum width of the etch stop pattern is confined within a width of the surface treatment region.
4. The semiconductor device of claim 1, wherein the first concentration of carbon in the surface treatment region increases with distance from a top surface of the surface treatment region toward the first interlayer insulating layer.
6. The semiconductor device of claim 1, wherein the surface treatment region defines an upper surface of the etch stop layer, and the etch stop pattern contacts the upper surface of the etch stop layer.
8. The semiconductor device of claim 7, wherein a third dielectric constant of the first etch stop layer is higher than the second dielectric constant of the second etch stop layer, and wherein the surface treatment region having the etch stop pattern thereon comprises a hydrophilic surface and the another region comprises a hydrophobic surface.
13. The semiconductor device of claim 11, wherein a maximum thickness of the etch stop pattern is less than a thickness of the etch stop layer.
17. The semiconductor device of claim 16, wherein a maximum thickness of the etch stop pattern is less than a thickness of the etch stop layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 22, 2020
August 23, 2022
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.