Patentable/Patents/US-11430944
US-11430944

Interconnect structures for logic and memory devices and methods of fabrication

PublishedAugust 30, 2022
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

An apparatus includes a first interconnect structure above a substrate, a memory device above and coupled with the first interconnect structure in a memory region. The memory device includes a non-volatile memory element, an electrode on the non-volatile memory element, and a metallization structure on a portion of the electrode. The apparatus further includes a second interconnect structure in a logic region above the substrate, where the second interconnect structure is laterally distant from the first interconnect structure. The logic region further includes a second metallization structure coupled to the second interconnect structure and a conductive structure between the second metallization structure and the second interconnect structure. The apparatus further includes a dielectric spacer that extends from the memory device to the conductive structure.

Patent Claims
16 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The apparatus of claim 1, wherein the first structure includes a liner layer and a fill metal, and the second structure includes the liner layer and the fill metal, wherein the liner layer includes ruthenium, cobalt or tantalum, and wherein the fill metal includes copper or tungsten.

3

3. The apparatus of claim 1, wherein the third structure has a first portion on the second interconnect structure and a second portion adjacent to the dielectric spacer.

4

4. The apparatus of claim 3, wherein the first portion has a thickness as measured vertically upward from an upper surface of the second interconnect structure, and wherein the thickness is between 2 nm and 5 nm.

5

5. The apparatus of claim 3, wherein the second portion has a thickness as measured laterally from the dielectric, and wherein the thickness is between 1 nm and 3 nm.

6

6. The apparatus of claim 3, wherein the first portion has a thickness, as measured vertically upward from an upper surface of the second interconnect structure, and wherein the thickness is non-uniform.

7

7. The apparatus of claim 1, wherein the third structure includes one or more of ruthenium, titanium or tantalum.

8

8. The apparatus of claim 7, wherein the third structure includes trace amount of oxygen.

9

9. The apparatus of claim 1, wherein the second structure has a first portion and a second portion, wherein the third structure is between the first portion of the second structure and the dielectric, and wherein the second portion is adjacent to the dielectric spacer.

11

11. The apparatus of claim 10, wherein a section of the second electrode portion extends along a sidewall of the first electrode portion.

12

12. The apparatus of claim 1, wherein the first structure has a lateral dimension that is greater than a lateral dimension of the electrode.

14

14. The apparatus of claim 13, wherein the first electrode portion comprises a metal and the second electrode portion comprises the metal and oxygen.

15

15. The apparatus of claim 13, wherein the first metallization structure is in contact with the first electrode portion and the second electrode portion.

16

16. The apparatus of claim 13, wherein a section of the second electrode portion extends along a sidewall of the first electrode portion.

17

17. The apparatus of claim 13, wherein the conductive structure includes one or more of ruthenium, titanium or tantalum.

19

19. The system of claim 18, wherein the conductive structure includes one or more of ruthenium, titanium or tantalum.

20

20. The system of claim 18, wherein the conductive structure is a first conductive structure and the system further comprises: a second conductive structure between the third interconnect structure and a third metallization structure in the first region.

Classification Codes (CPC)

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Patent Metadata

Filing Date

March 19, 2019

Publication Date

August 30, 2022

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Cite as: Patentable. “Interconnect structures for logic and memory devices and methods of fabrication” (US-11430944). https://patentable.app/patents/US-11430944

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