A variable gain amplifier and an electronic apparatus. The variable gain amplifier includes a first transconductance stage circuit and a second transconductance stage circuit, where the first transconductance stage circuit includes a first amplifying circuit and a second amplifying circuit, the second transconductance stage circuit includes a third amplifying circuit and a fourth amplifying circuit, the first amplifying circuit and the fourth amplifying circuit form a differential input pair, and the second amplifying circuit and the third amplifying circuit form a differential input pair, and where each amplifying circuit of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit includes a plurality of parallel transistors, and bias control of the plurality of transistors is independent of each other.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The variable gain amplifier according to claim 1, wherein the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit have a same structure.
4. The variable gain amplifier according to claim 3, wherein, when the variable gain amplifier performs gain switching, a bias current output by an amplifying circuit of at least one of the first differential input pair or the second differential input pair decrements, and a bias current output by the other amplifying circuit of the at least one of the first differential input pair or the second differential input pair increments.
6. The variable gain amplifier according to claim 5, wherein at least one of the first degeneration circuit or the second degeneration circuit comprises at least one of a resistor or an inductor.
7. The variable gain amplifier according to claim 5, wherein the plurality of transistors is a plurality of triodes.
8. The variable gain amplifier according to claim 7, wherein in each of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit, bases of the plurality of transistors are configured to separately receive an input voltage, emitters of the plurality of transistors are separately coupled to ground through at least one of the first degeneration circuit or the second degeneration circuit, and collectors of the plurality of transistors are short-circuited together and are configured to output a bias current.
9. The variable gain amplifier according to claim 5, wherein the plurality of transistors are metal-oxide semiconductor (MOS) transistors.
10. The variable gain amplifier according to claim 9, wherein in each of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit, gates of the plurality of transistors are configured to separately receive an input voltage, sources of the plurality of transistors are separately coupled to ground through at least one of the first degeneration circuit or the second degeneration circuit, and drains of the plurality of transistors are short-circuited together and are configured to output a bias current.
14. The detection apparatus according to claim 11, wherein the detection apparatus is at least one of a phased array receiver, a phased array transmitter, or a phased array transceiver.
16. The variable gain amplifier according to claim 15, wherein the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit have a same circuit structure.
17. The variable gain amplifier according to claim 15, wherein, when the variable gain amplifier performs gain switching, a bias current output by an amplifying circuit of at least one of the first differential input pair or the second differential input pair decrements, and a bias current output by the other amplifying circuit of the at least one of the first differential input pair or the second differential input pair increments.
19. The variable gain amplifier according to claim 18, wherein in each of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit, bases of the plurality of transistors are configured to separately receive an input voltage, wherein emitters of the plurality of transistors are separately coupled to ground through at least one of the first degeneration circuit or the second degeneration circuit, and wherein collectors of the plurality of transistors are short-circuited together and are configured to output a bias current.
20. The variable gain amplifier according to claim 18, wherein in each of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit, gates of the plurality of transistors are configured to separately receive an input voltage, sources of the plurality of transistors are separately coupled to ground through at least one of the first degeneration circuit or the second degeneration circuit, and drains of the plurality of transistors are short-circuited together and are configured to output a bias current.
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March 29, 2021
August 30, 2022
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